/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#ifndef __T5W_H
#define __T5W_H

#define		HHI_CHECK_CLK_RESULT		(0x004 << 2)
#define		HHI_HRX_CLK_CTRL0		(0x008 << 2)
#define		HHI_HRX_CLK_CTRL1		(0x009 << 2)
#define		HHI_HRX_CLK_CTRL2		(0x00a << 2)
#define		HHI_HRX_CLK_CTRL3		(0x00b << 2)
#define		HHI_DEMOD_32K_CNTL0		(0x010 << 2)
#define		HHI_DEMOD_32K_CNTL1		(0x011 << 2)
#define		HHI_GP0_PLL_CNTL0		(0x020 << 2)
#define		HHI_GP0_PLL_CNTL1		(0x021 << 2)
#define		HHI_GP0_PLL_CNTL2		(0x022 << 2)
#define		HHI_GP0_PLL_CNTL3		(0x023 << 2)
#define		HHI_GP0_PLL_CNTL4		(0x024 << 2)
#define		HHI_GP0_PLL_CNTL5		(0x025 << 2)
#define		HHI_GP0_PLL_CNTL6		(0x026 << 2)
#define		HHI_GP0_PLL_STS			(0x027 << 2)
#define		HHI_GP1_PLL_CNTL0		(0x028 << 2)
#define		HHI_GP1_PLL_CNTL1		(0x029 << 2)
#define		HHI_GP1_PLL_CNTL2		(0x02a << 2)
#define		HHI_GP1_PLL_CNTL3		(0x02b << 2)
#define		HHI_GP1_PLL_STS			(0x02f << 2)
#define		HHI_HIFI_PLL_CNTL0		(0x036 << 2)
#define		HHI_HIFI_PLL_CNTL1		(0x037 << 2)
#define		HHI_HIFI_PLL_CNTL2		(0x038 << 2)
#define		HHI_HIFI_PLL_CNTL3		(0x039 << 2)
#define		HHI_HIFI_PLL_CNTL4		(0x03a << 2)
#define		HHI_HIFI_PLL_CNTL5		(0x03b << 2)
#define		HHI_HIFI_PLL_CNTL6		(0x03c << 2)
#define		HHI_HIFI_PLL_STS		(0x03d << 2)
#define		HHI_VIID_CLK_DIV		(0x04a << 2)
#define		HHI_VIID_CLK_CNTL		(0x04b << 2)
#define		HHI_VID_CLK_DIV			(0x059 << 2)
#define		HHI_MPEG_CLK_CNTL		(0x05d << 2)
#define		HHI_VID_CLK_CNTL		(0x05f << 2)
#define		HHI_TSIN_DEGLITCH_CLK_CNTL	(0x060 << 2)
#define		HHI_TS_CLK_CNTL			(0x064 << 2)
#define		HHI_VID_CLK_CNTL2		(0x065 << 2)
#define		HHI_MALI_CLK_CNTL		(0x06c << 2)
#define		HHI_VPU_CLKC_CTRL		(0x06d << 2)
#define		HHI_VPU_CLK_CTRL		(0x06f << 2)
#define		HHI_HDMI_CLK_CNTL		(0x073 << 2)
#define		HHI_DEMOD_CLK_CNTL		(0x074 << 2)
#define		HHI_DEMOD_CLK_CNTL1		(0x075 << 2)
#define		HHI_ETH_CLK_CNTL		(0x076 << 2)
#define		HHI_VDEC_CLK_CNTL		(0x078 << 2)
#define		HHI_VDEC2_CLK_CNTL		(0x079 << 2)
#define		HHI_VDEC3_CLK_CNTL		(0x07a << 2)
#define		HHI_VDEC4_CLK_CNTL		(0x07b << 2)
#define		HHI_HDCP22_CLK_CNTL		(0x07c << 2)
#define		HHI_VAPBCLK_CNTL		(0x07d << 2)
#define		HHI_TVFECLK_CNTL		(0x07e << 2)
#define		HHI_GE2DCLK_CNTL		(0x07f << 2)
#define		HHI_HDMIRX_CLK_CNTL		(0x080 << 2)
#define		HHI_HDMIRX_AUD_CLK_CNTL		(0x081 << 2)
#define		HHI_VPU_CLKB_CTRL		(0x083 << 2)
#define		HHI_GEN_CLK_CNTL		(0x08a << 2)
#define		HHI_AUDPLL_CLK_OUT_CNTL		(0x08c << 2)
#define		HHI_HDMIRX_METER_CLK_CNTL	(0x08d << 2)
#define		HHI_VDIN_MEAS_CLK_CNTL		(0x094 << 2)
#define		HHI_NAND_CLK_CNTL		(0x097 << 2)
#define		HHI_SD_EMMC_CLK_CNTL		(0x099 << 2)
#define		HHI_TCON_CLK_CNTL		(0x09c << 2)
#define		HHI_VIID_CLK0_DIV		(0x0a0 << 2)
#define		HHI_VIID_CLK0_CTRL		(0x0a1 << 2)
#define		HHI_VID_CLK0_DIV		(0x0a2 << 2)
#define		HHI_VID_CLK0_CTRL2		(0x0a4 << 2)
#define		HHI_VIID_CLK1_DIV		(0x0a8 << 2)
#define		HHI_VIID_CLK1_CTRL		(0x0a9 << 2)
#define		HHI_VID_CLK1_DIV		(0x0aa << 2)
#define		HHI_VID_CLK1_CTRL2		(0x0ac << 2)
#define		HHI_VIID_CLK2_DIV		(0x0b0 << 2)
#define		HHI_VIID_CLK2_CTRL		(0x0b1 << 2)
#define		HHI_VID_CLK2_DIV		(0x0b2 << 2)
#define		HHI_VID_CLK2_CTRL		(0x0b3 << 2)
#define		HHI_VID_CLK2_CTRL2		(0x0b4 << 2)
#define		HHI_HDMI_AXI_CLK_CNTL		(0x0b8 << 2)
#define		HHI_MPLL_CNTL0			(0x0c0 << 2)
#define		HHI_MPLL_CNTL1			(0x0c1 << 2)
#define		HHI_MPLL_CNTL2			(0x0c2 << 2)
#define		HHI_MPLL_CNTL3			(0x0c3 << 2)
#define		HHI_MPLL_CNTL4			(0x0c4 << 2)
#define		HHI_MPLL_CNTL5			(0x0c5 << 2)
#define		HHI_MPLL_CNTL6			(0x0c6 << 2)
#define		HHI_MPLL_CNTL7			(0x0c7 << 2)
#define		HHI_MPLL_CNTL8			(0x0c8 << 2)
#define		HHI_MPLL_STS			(0x0c9 << 2)
#define		HHI_FIX_PLL_CNTL0		(0x0d0 << 2)
#define		HHI_FIX_PLL_CNTL1		(0x0d1 << 2)
#define		HHI_FIX_PLL_CNTL2		(0x0d2 << 2)
#define		HHI_FIX_PLL_CNTL3		(0x0d3 << 2)
#define		HHI_FIX_PLL_CNTL4		(0x0d4 << 2)
#define		HHI_FIX_PLL_CNTL5		(0x0d5 << 2)
#define		HHI_FIX_PLL_CNTL6		(0x0d6 << 2)
#define		HHI_FIX_PLL_STS			(0x0d7 << 2)
#define		HHI_SYS_PLL_CNTL0		(0x0e0 << 2)
#define		HHI_SYS_PLL_CNTL1		(0x0e1 << 2)
#define		HHI_SYS_PLL_CNTL2		(0x0e2 << 2)
#define		HHI_SYS_PLL_CNTL3		(0x0e3 << 2)
#define		HHI_SYS_PLL_CNTL4		(0x0e4 << 2)
#define		HHI_SYS_PLL_CNTL5		(0x0e5 << 2)
#define		HHI_SYS_PLL_CNTL6		(0x0e6 << 2)
#define		HHI_SYS_PLL_STS			(0x0e7 << 2)
#define		HHI_SYS1_PLL_CNTL0		(0x0e8 << 2)
#define		HHI_SYS1_PLL_CNTL1		(0x0e9 << 2)
#define		HHI_SYS1_PLL_CNTL2		(0x0ea << 2)
#define		HHI_SYS1_PLL_STS		(0x0ec << 2)
#define		HHI_VID_LOCK_CLK_CNTL		(0x0f2 << 2)
#define		HHI_ATV_DMD_SYS_CLK_CNTL	(0x0f3 << 2)
#define		HHI_BT656_CLK_CNTL		(0x0f5 << 2)
#define		HHI_CDAC_CLK_CNTL		(0x0f6 << 2)
#define		HHI_SPICC_CLK_CNTL		(0x0f7 << 2)
#define		HHI_SPICC_CLK_CNTL1		(0x0f8 << 2)

/* HIU 0xff63c000 base */
#define		HHI_DADC_CNTL			(0x027 << 2)
#define		HHI_DADC_CNTL2			(0x028 << 2)
#define		HHI_DADC_RDBK0_I		(0x029 << 2)
#define		HHI_DADC_CNTL3			(0x02a << 2)
#define		HHI_DADC_CNTL4			(0x02b << 2)
#define		HHI_CVBS_DETECT_CNTL		(0x02e << 2)
#define		HHI_XTAL_DIVN_CNTL		(0x02f << 2)
#define		HHI_GCLK_MPEG0			(0x050 << 2)
#define		HHI_GCLK_MPEG1			(0x051 << 2)
#define		HHI_GCLK_MPEG2			(0x052 << 2)
#define		HHI_GCLK_OTHER			(0x054 << 2)
#define		HHI_GCLK_SP_MPEG		(0x055 << 2)

#define		HHI_SYS_CPU_CLK_CNTL1		(0x057 << 2)
#define		HHI_SYS_CPU_CLK_CNTL		(0x067 << 2)
#define		HHI_VID_PLL_CLK_DIV		(0x068 << 2)
#define		HHI_VIPNANOQ_CNTL		(0x071 << 2)
#define		HHI_VIPNANOQ_CLK_CNTL		(0x072 << 2)
#define		HHI_SYS_CPU_CLK_CNTL2		(0x084 << 2)
#define		HHI_SYS_CPU_CLK_CNTL3		(0x085 << 2)
#define		HHI_SYS_CPU_CLK_CNTL4		(0x086 << 2)
#define		HHI_SYS_CPU_CLK_CNTL5		(0x087 << 2)
#define		HHI_SYS_CPU_CLK_CNTL6		(0x088 << 2)
#define		HHI_SYS_CPU_CLK_RESULT		(0x089 << 2)

#endif /* __T5W_H */
