/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
 */

#ifndef __ADDR_DTMB_CHE_H__
#define __ADDR_DTMB_CHE_H__

#define  DTMB_CHE_IBDFE_CONF0               (0x8b)
#define  DTMB_CHE_TE_HREB_SNR               (0x8d)
#define  DTMB_CHE_MC_SC_TIMING_POWTHR       (0x8e)
#define  DTMB_CHE_MC_SC_PROTECT_GD          (0x8f)
#define  DTMB_CHE_TIMING_LIMIT              (0x90)
#define  DTMB_CHE_TPS_CONFIG                (0x91)
#define  DTMB_CHE_FD_TD_STEPSIZE            (0x92)
#define  DTMB_CHE_QSTEP_SET                 (0x93)
#define  DTMB_CHE_SEG_CONFIG                (0x94)
#define  DTMB_CHE_FD_TD_LEAKSIZE_CONFIG1    (0x95)
#define  DTMB_CHE_FD_TD_LEAKSIZE_CONFIG2    (0x96)
#define  DTMB_CHE_FD_TD_COEFF               (0x97)
#define  DTMB_CHE_M_CCI_THR_CONFIG1         (0x98)
#define  DTMB_CHE_M_CCI_THR_CONFIG2         (0x99)
#define  DTMB_CHE_M_CCI_THR_CONFIG3         (0x9a)
#define  DTMB_CHE_CCIDET_CONFIG             (0x9b)
#define  DTMB_CHE_IBDFE_CONFIG1             (0x9d)
#define  DTMB_CHE_IBDFE_CONFIG2             (0x9e)
#define  DTMB_CHE_IBDFE_CONFIG3             (0x9f)
#define  DTMB_CHE_TD_COEFF                  (0xa0)
#define  DTMB_CHE_FD_TD_STEPSIZE_ADJ        (0xa1)
#define  DTMB_CHE_FD_COEFF_FRZ              (0xa2)
#define  DTMB_CHE_FD_COEFF                  (0xa3)
#define  DTMB_CHE_FD_LEAKSIZE               (0xa4)
#define  DTMB_CHE_IBDFE_CONFIG4             (0xa5)
#define  DTMB_CHE_IBDFE_CONFIG5             (0xa6)
#define  DTMB_CHE_IBDFE_CONFIG6             (0xa7)
#define  DTMB_CHE_IBDFE_CONFIG7             (0xa8)
#define  DTMB_CHE_DCM_SC_MC_GD_LEN          (0xa9)
#define  DTMB_CHE_EQMC_PICK_THR             (0xaa)
#define  DTMB_CHE_EQMC_THRESHOLD            (0xab)
#define  DTMB_CHE_EQSC_PICK_THR             (0xad)
#define  DTMB_CHE_EQSC_THRESHOLD            (0xae)
#define  DTMB_CHE_PROTECT_GD_TPS            (0xaf)
#define  DTMB_CHE_FD_TD_STEPSIZE_THR1       (0xb0)
#define  DTMB_CHE_TDFD_SWITCH_SYM1          (0xb1)
#define  DTMB_CHE_TDFD_SWITCH_SYM2          (0xb2)
#define  DTMB_CHE_EQ_CONFIG                 (0xb3)
#define  DTMB_CHE_EQSC_SNR_IMP_THR1         (0xb4)
#define  DTMB_CHE_EQSC_SNR_IMP_THR2         (0xb5)
#define  DTMB_CHE_EQMC_SNR_IMP_THR1         (0xb6)
#define  DTMB_CHE_EQMC_SNR_IMP_THR2         (0xb7)
#define  DTMB_CHE_EQSC_SNR_DROP_THR         (0xb8)
#define  DTMB_CHE_EQMC_SNR_DROP_THR         (0xb9)
#define  DTMB_CHE_M_CCI_THR                 (0xba)
#define  DTMB_CHE_TPS_MC                    (0xbb)
#define  DTMB_CHE_TPS_SC                    (0xbc)
#define  DTMB_CHE_CHE_SET_FSM               (0xbd)
#define  DTMB_CHE_ZERO_NUM_THR              (0xbe)
#define  DTMB_CHE_TIMING_READY              (0xbf)

#endif
