/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#ifndef __T5M_CLKC_H
#define __T5M_CLKC_H

/*
 * CLKID index values
 */
#define CLKID_SYS_PLL_DCO		0
#define CLKID_SYS_PLL			1
#define CLKID_SYS1_PLL_DCO		2
#define CLKID_SYS1_PLL			3
#define CLKID_FIXED_PLL_DCO		4
#define CLKID_FIXED_PLL			5
#define CLKID_FCLK_DIV2_DIV		6
#define CLKID_FCLK_DIV2			7
#define CLKID_FCLK_DIV3_DIV		8
#define CLKID_FCLK_DIV3			9
#define CLKID_FCLK_DIV4_DIV		10
#define CLKID_FCLK_DIV4			11
#define CLKID_FCLK_DIV5_DIV		12
#define CLKID_FCLK_DIV5			13
#define CLKID_FCLK_DIV7_DIV		14
#define CLKID_FCLK_DIV7			15
#define CLKID_FCLK_DIV2P5_DIV		16
#define CLKID_FCLK_DIV2P5		17
#define CLKID_GP0_PLL_DCO		18
#define CLKID_GP0_PLL			19
#define CLKID_CPU_DYN_CLK		20
#define CLKID_CPU_CLK			21
#define CLKID_DSU_DYN_CLK		22
#define CLKID_DSU_PRE_CLK		23
#define CLKID_DSU_CLK			24
#define CLKID_HIFI_PLL_DCO		25
#define CLKID_HIFI_PLL			26
#define CLKID_HIFI1_PLL_DCO		27
#define CLKID_HIFI1_PLL			28
#define CLKID_MPLL_50M_DIV		29
#define CLKID_MPLL_50M			30
#define CLKID_BASE			31

#define CLKID_RTC_32K_CLKIN		(CLKID_BASE + 0)
#define CLKID_RTC_32K_DIV		(CLKID_BASE + 1)
#define CLKID_RTC_32K_XATL		(CLKID_BASE + 2)
#define CLKID_RTC_32K_SEL		(CLKID_BASE + 3)
#define CLKID_RTC_CLK			(CLKID_BASE + 4)
#define CLKID_SYS_CLK			(CLKID_BASE + 5)
#define CLKID_AXI_CLK			(CLKID_BASE + 6)
#define CLKID_CECB_32K_CLKIN		(CLKID_BASE + 7)
#define CLKID_CECB_32K_DIV		(CLKID_BASE + 8)
#define CLKID_CECB_32K_SEL_PRE		(CLKID_BASE + 9)
#define CLKID_CECB_32K_SEL		(CLKID_BASE + 10)
#define CLKID_CECB_32K_CLKOUT		(CLKID_BASE + 11)
#define CLKID_SC_CLK_SEL		(CLKID_BASE + 12)
#define CLKID_SC_CLK_DIV		(CLKID_BASE + 13)
#define CLKID_SC_CLK			(CLKID_BASE + 14)
#define CLKID_24M_CLK_GATE		(CLKID_BASE + 15)
#define CLKID_24M_DIV2			(CLKID_BASE + 16)
#define CLKID_12M_CLK			(CLKID_BASE + 17)
#define CLKID_25M_CLK_DIV		(CLKID_BASE + 18)
#define CLKID_25M_CLK			(CLKID_BASE + 19)
#define VIDEO_BASE			(CLKID_BASE + 20)

#define CLKID_VCLK_SEL			(VIDEO_BASE + 0)
#define CLKID_VCLK2_SEL			(VIDEO_BASE + 1)
#define CLKID_VCLK_INPUT		(VIDEO_BASE + 2)
#define CLKID_VCLK2_INPUT		(VIDEO_BASE + 3)
#define CLKID_VCLK_DIV			(VIDEO_BASE + 4)
#define CLKID_VCLK2_DIV			(VIDEO_BASE + 5)
#define CLKID_VCLK			(VIDEO_BASE + 6)
#define CLKID_VCLK2			(VIDEO_BASE + 7)
#define CLKID_VCLK_DIV1			(VIDEO_BASE + 8)
#define CLKID_VCLK_DIV2_EN		(VIDEO_BASE + 9)
#define CLKID_VCLK_DIV4_EN		(VIDEO_BASE + 10)
#define CLKID_VCLK_DIV6_EN		(VIDEO_BASE + 11)
#define CLKID_VCLK_DIV12_EN		(VIDEO_BASE + 12)
#define CLKID_VCLK2_DIV1		(VIDEO_BASE + 13)
#define CLKID_VCLK2_DIV2_EN		(VIDEO_BASE + 14)
#define CLKID_VCLK2_DIV4_EN		(VIDEO_BASE + 15)
#define CLKID_VCLK2_DIV6_EN		(VIDEO_BASE + 16)
#define CLKID_VCLK2_DIV12_EN		(VIDEO_BASE + 17)
#define CLKID_VCLK_DIV2			(VIDEO_BASE + 18)
#define CLKID_VCLK_DIV4			(VIDEO_BASE + 19)
#define CLKID_VCLK_DIV6			(VIDEO_BASE + 20)
#define CLKID_VCLK_DIV12		(VIDEO_BASE + 21)
#define CLKID_VCLK2_DIV2		(VIDEO_BASE + 22)
#define CLKID_VCLK2_DIV4		(VIDEO_BASE + 23)
#define CLKID_VCLK2_DIV6		(VIDEO_BASE + 24)
#define CLKID_VCLK2_DIV12		(VIDEO_BASE + 25)
#define CLKID_CTS_ENCI_SEL		(VIDEO_BASE + 26)
#define CLKID_CTS_ENCP_SEL		(VIDEO_BASE + 27)
#define CLKID_CTS_VDAC_SEL		(VIDEO_BASE + 28)
#define CLKID_HDMI_TX_SEL		(VIDEO_BASE + 29)
#define CLKID_CTS_ENCI			(VIDEO_BASE + 30)
#define CLKID_CTS_ENCP			(VIDEO_BASE + 31)
#define CLKID_CTS_VDAC			(VIDEO_BASE + 32)
#define CLKID_HDMI_TX			(VIDEO_BASE + 33)
#define CLKID_MALI_0_SEL		(VIDEO_BASE + 34)
#define CLKID_MALI_0_DIV		(VIDEO_BASE + 35)
#define CLKID_MALI_0			(VIDEO_BASE + 36)
#define CLKID_MALI_1_SEL		(VIDEO_BASE + 37)
#define CLKID_MALI_1_DIV		(VIDEO_BASE + 38)
#define CLKID_MALI_1			(VIDEO_BASE + 39)
#define CLKID_MALI			(VIDEO_BASE + 40)
#define CLKID_VDEC_0_SEL		(VIDEO_BASE + 41)
#define CLKID_VDEC_0_DIV		(VIDEO_BASE + 42)
#define CLKID_VDEC_0			(VIDEO_BASE + 43)
#define CLKID_VDEC_1_SEL		(VIDEO_BASE + 44)
#define CLKID_VDEC_1_DIV		(VIDEO_BASE + 45)
#define CLKID_VDEC_1			(VIDEO_BASE + 46)
#define CLKID_VDEC			(VIDEO_BASE + 47)
#define CLKID_HCODEC_0_SEL		(VIDEO_BASE + 48)
#define CLKID_HCODEC_0_DIV		(VIDEO_BASE + 49)
#define CLKID_HCODEC_0			(VIDEO_BASE + 50)
#define CLKID_HCODEC_1_SEL		(VIDEO_BASE + 51)
#define CLKID_HCODEC_1_DIV		(VIDEO_BASE + 52)
#define CLKID_HCODEC_1			(VIDEO_BASE + 53)
#define CLKID_HCODEC			(VIDEO_BASE + 54)
#define CLKID_HEVCB_0_SEL		(VIDEO_BASE + 55)
#define CLKID_HEVCB_0_DIV		(VIDEO_BASE + 56)
#define CLKID_HEVCB_0			(VIDEO_BASE + 57)
#define CLKID_HEVCB_1_SEL		(VIDEO_BASE + 58)
#define CLKID_HEVCB_1_DIV		(VIDEO_BASE + 59)
#define CLKID_HEVCB_1			(VIDEO_BASE + 60)
#define CLKID_HEVCB			(VIDEO_BASE + 61)
#define CLKID_VPU_0_SEL			(VIDEO_BASE + 62)
#define CLKID_VPU_0_DIV			(VIDEO_BASE + 63)
#define CLKID_VPU_0			(VIDEO_BASE + 64)
#define CLKID_VPU_1_SEL			(VIDEO_BASE + 65)
#define CLKID_VPU_1_DIV			(VIDEO_BASE + 66)
#define CLKID_VPU_1			(VIDEO_BASE + 67)
#define CLKID_VPU			(VIDEO_BASE + 68)
#define CLKID_VPU_CLKB_TMP_SEL		(VIDEO_BASE + 69)
#define CLKID_VPU_CLKB_TMP_DIV		(VIDEO_BASE + 70)
#define CLKID_VPU_CLKB_TMP		(VIDEO_BASE + 71)
#define CLKID_VPU_CLKB_DIV		(VIDEO_BASE + 72)
#define CLKID_VPU_CLKB			(VIDEO_BASE + 73)
#define CLKID_VAPB_0_SEL		(VIDEO_BASE + 74)
#define CLKID_VAPB_0_DIV		(VIDEO_BASE + 75)
#define CLKID_VAPB_0			(VIDEO_BASE + 76)
#define CLKID_VAPB_1_SEL		(VIDEO_BASE + 77)
#define CLKID_VAPB_1_DIV		(VIDEO_BASE + 78)
#define CLKID_VAPB_1			(VIDEO_BASE + 79)
#define CLKID_VAPB			(VIDEO_BASE + 80)
#define CLKID_GE2D_GATE			(VIDEO_BASE + 81)
#define CLKID_VDIN_MEAS_SEL		(VIDEO_BASE + 82)
#define CLKID_VDIN_MEAS_DIV		(VIDEO_BASE + 83)
#define CLKID_VDIN_MEAS			(VIDEO_BASE + 84)
#define CLKID_VID_LOCK_DIV		(VIDEO_BASE + 85)
#define CLKID_VID_LOCK			(VIDEO_BASE + 86)

#define PERI_BASE			(VIDEO_BASE + 87)
#define CLKID_SD_EMMC_C_SEL		(PERI_BASE + 0)
#define CLKID_SD_EMMC_C_DIV		(PERI_BASE + 1)
#define CLKID_SD_EMMC_C			(PERI_BASE + 2)
#define CLKID_SD_EMMC_B_SEL		(PERI_BASE + 6)
#define CLKID_SD_EMMC_B_DIV		(PERI_BASE + 7)
#define CLKID_SD_EMMC_B			(PERI_BASE + 8)
#define CLKID_CDAC_CLK_SEL		(PERI_BASE + 9)
#define CLKID_CDAC_CLK_DIV		(PERI_BASE + 10)
#define CLKID_CDAC_CLK			(PERI_BASE + 11)
#define CLKID_SPICC0_SEL		(PERI_BASE + 12)
#define CLKID_SPICC0_DIV		(PERI_BASE + 13)
#define CLKID_SPICC0			(PERI_BASE + 14)
#define CLKID_SPICC1_SEL		(PERI_BASE + 15)
#define CLKID_SPICC1_DIV		(PERI_BASE + 16)
#define CLKID_SPICC1			(PERI_BASE + 17)
#define CLKID_SPICC2_SEL		(PERI_BASE + 18)
#define CLKID_SPICC2_DIV		(PERI_BASE + 19)
#define CLKID_SPICC2			(PERI_BASE + 20)
#define CLKID_PWM_A_SEL			(PERI_BASE + 21)
#define CLKID_PWM_A_DIV			(PERI_BASE + 22)
#define CLKID_PWM_A			(PERI_BASE + 23)
#define CLKID_PWM_B_SEL			(PERI_BASE + 24)
#define CLKID_PWM_B_DIV			(PERI_BASE + 25)
#define CLKID_PWM_B			(PERI_BASE + 26)
#define CLKID_PWM_C_SEL			(PERI_BASE + 27)
#define CLKID_PWM_C_DIV			(PERI_BASE + 28)
#define CLKID_PWM_C			(PERI_BASE + 29)
#define CLKID_PWM_D_SEL			(PERI_BASE + 30)
#define CLKID_PWM_D_DIV			(PERI_BASE + 31)
#define CLKID_PWM_D			(PERI_BASE + 32)
#define CLKID_PWM_E_SEL			(PERI_BASE + 33)
#define CLKID_PWM_E_DIV			(PERI_BASE + 34)
#define CLKID_PWM_E			(PERI_BASE + 35)
#define CLKID_PWM_F_SEL			(PERI_BASE + 36)
#define CLKID_PWM_F_DIV			(PERI_BASE + 37)
#define CLKID_PWM_F			(PERI_BASE + 38)
#define CLKID_PWM_G_SEL			(PERI_BASE + 39)
#define CLKID_PWM_G_DIV			(PERI_BASE + 40)
#define CLKID_PWM_G			(PERI_BASE + 41)
#define CLKID_PWM_H_SEL			(PERI_BASE + 42)
#define CLKID_PWM_H_DIV			(PERI_BASE + 43)
#define CLKID_PWM_H			(PERI_BASE + 44)
#define CLKID_SARADC_SEL		(PERI_BASE + 45)
#define CLKID_SARADC_DIV		(PERI_BASE + 46)
#define CLKID_SARADC			(PERI_BASE + 47)
#define CLKID_GEN_SEL			(PERI_BASE + 48)
#define CLKID_GEN_DIV			(PERI_BASE + 49)
#define CLKID_GEN			(PERI_BASE + 50)
#define CLKID_ETH_RMII_SEL		(PERI_BASE + 51)
#define CLKID_ETH_RMII_DIV		(PERI_BASE + 52)
#define CLKID_ETH_RMII			(PERI_BASE + 53)
#define CLKID_ETH_DIV8			(PERI_BASE + 54)
#define CLKID_ETH_125M			(PERI_BASE + 55)
#define CLKID_TS_CLK_DIV		(PERI_BASE + 56)
#define CLKID_TS_CLK			(PERI_BASE + 57)

#define MEDIA_BASE			(PERI_BASE + 58)
#define CLKID_HDMIRX_2M_SEL		(MEDIA_BASE + 0)
#define CLKID_HDMIRX_2M_DIV		(MEDIA_BASE + 1)
#define CLKID_HDMIRX_2M			(MEDIA_BASE + 2)
#define CLKID_HDMIRX_5M_SEL		(MEDIA_BASE + 3)
#define CLKID_HDMIRX_5M_DIV		(MEDIA_BASE + 4)
#define CLKID_HDMIRX_5M			(MEDIA_BASE + 5)
#define CLKID_HDMIRX_CFG_SEL		(MEDIA_BASE + 6)
#define CLKID_HDMIRX_CFG_DIV		(MEDIA_BASE + 7)
#define CLKID_HDMIRX_CFG		(MEDIA_BASE + 8)
#define CLKID_HDMIRX_HDCP_SEL		(MEDIA_BASE + 9)
#define CLKID_HDMIRX_HDCP_DIV		(MEDIA_BASE + 10)
#define CLKID_HDMIRX_HDCP		(MEDIA_BASE + 11)
#define CLKID_HDMIRX_AUD_PLL_SEL	(MEDIA_BASE + 12)
#define CLKID_HDMIRX_AUD_PLL_DIV	(MEDIA_BASE + 13)
#define CLKID_HDMIRX_AUD_PLL		(MEDIA_BASE + 14)
#define CLKID_HDMIRX_ACR_SEL		(MEDIA_BASE + 15)
#define CLKID_HDMIRX_ACR_DIV		(MEDIA_BASE + 16)
#define CLKID_HDMIRX_ACR		(MEDIA_BASE + 17)
#define CLKID_HDMIRX_METER_SEL		(MEDIA_BASE + 18)
#define CLKID_HDMIRX_METER_DIV		(MEDIA_BASE + 19)
#define CLKID_HDMIRX_METER		(MEDIA_BASE + 20)
#define CLKID_ADC_EXTCLK_SEL		(MEDIA_BASE + 21)
#define CLKID_ADC_EXTCLK_DIV		(MEDIA_BASE + 22)
#define CLKID_ADC_EXTCLK		(MEDIA_BASE + 23)
#define CLKID_CTS_DEMOD_CORE_SEL	(MEDIA_BASE + 24)
#define CLKID_CTS_DEMOD_CORE_DIV	(MEDIA_BASE + 25)
#define CLKID_CTS_DEMOD_CORE		(MEDIA_BASE + 26)
#define CLKID_CTS_DEMOD_CORE_T2_SEL	(MEDIA_BASE + 27)
#define CLKID_CTS_DEMOD_CORE_T2_DIV	(MEDIA_BASE + 28)
#define CLKID_CTS_DEMOD_CORE_T2		(MEDIA_BASE + 29)
#define CLKID_CTS_TCON_PLL_CLK_SEL	(MEDIA_BASE + 30)
#define CLKID_CTS_TCON_PLL_CLK_DIV	(MEDIA_BASE + 31)
#define CLKID_CTS_TCON_PLL_CLK		(MEDIA_BASE + 32)
#define CLKID_ME_0_SEL			(MEDIA_BASE + 33)
#define CLKID_ME_0_DIV			(MEDIA_BASE + 34)
#define CLKID_ME_0			(MEDIA_BASE + 35)
#define CLKID_ME_1_SEL			(MEDIA_BASE + 36)
#define CLKID_ME_1_DIV			(MEDIA_BASE + 37)
#define CLKID_ME_1			(MEDIA_BASE + 38)
#define CLKID_ME_SEL			(MEDIA_BASE + 39)
#define CLKID_ME			(MEDIA_BASE + 40)
#define CLKID_FRC_0_SEL			(MEDIA_BASE + 41)
#define CLKID_FRC_0_DIV			(MEDIA_BASE + 42)
#define CLKID_FRC_0			(MEDIA_BASE + 43)
#define CLKID_FRC_1_SEL			(MEDIA_BASE + 44)
#define CLKID_FRC_1_DIV			(MEDIA_BASE + 45)
#define CLKID_FRC_1			(MEDIA_BASE + 46)
#define CLKID_FRC_SEL			(MEDIA_BASE + 47)
#define CLKID_FRC			(MEDIA_BASE + 48)
#define CLKID_CTS_USB2_250M_SEL		(MEDIA_BASE + 49)
#define CLKID_CTS_USB2_250M_DIV		(MEDIA_BASE + 50)
#define CLKID_CTS_USB2_250M		(MEDIA_BASE + 51)
#define CLKID_DEMOD_32K_CLKIN		(MEDIA_BASE + 52)
#define CLKID_DEMOD_32K_DIV		(MEDIA_BASE + 53)
#define CLKID_DEMOD_32K			(MEDIA_BASE + 54)
#define CLKID_TSIN_0_SEL		(MEDIA_BASE + 55)
#define CLKID_TSIN_0_DIV		(MEDIA_BASE + 56)
#define CLKID_TSIN_0			(MEDIA_BASE + 57)
#define CLKID_TSIN_1_SEL		(MEDIA_BASE + 58)
#define CLKID_TSIN_1_DIV		(MEDIA_BASE + 59)
#define CLKID_TSIN_1			(MEDIA_BASE + 60)
#define CLKID_TSIN_SEL			(MEDIA_BASE + 61)
#define CLKID_TSIN			(MEDIA_BASE + 62)

/*CLKCTRL_SYS_CLK_EN0_REG0*/
#define SYS_BASE			(MEDIA_BASE + 63)
#define CLKID_SYS_CLK_DOS		(SYS_BASE + 0)
#define CLKID_SYS_CLK_ETHPHY		(SYS_BASE + 1)
#define CLKID_SYS_CLK_DEMOD		(SYS_BASE + 2)
#define CLKID_SYS_CLK_MALI		(SYS_BASE + 3)
#define CLKID_SYS_CLK_AOCPU		(SYS_BASE + 4)
#define CLKID_SYS_CLK_CEC		(SYS_BASE + 5)
#define CLKID_SYS_CLK_AMPIPE_ETH	(SYS_BASE + 6)
#define CLKID_SYS_CLK_AM2AXI1		(SYS_BASE + 7)
#define CLKID_SYS_CLK_AM2AXI2		(SYS_BASE + 8)
#define CLKID_SYS_CLK_LED_CTRL		(SYS_BASE + 9)
#define CLKID_SYS_CLK_SD_EMMC_B		(SYS_BASE + 10)
#define CLKID_SYS_CLK_SD_EMMC_C		(SYS_BASE + 11)
#define CLKID_SYS_CLK_SMARTCARD		(SYS_BASE + 12)
#define CLKID_SYS_CLK_ACODEC		(SYS_BASE + 13)
#define CLKID_SYS_CLK_SPIFC		(SYS_BASE + 14)
#define CLKID_SYS_CLK_MSR_CLK		(SYS_BASE + 15)
#define CLKID_SYS_CLK_IR_CTRL		(SYS_BASE + 16)
#define CLKID_SYS_CLK_AUDIO		(SYS_BASE + 17)
#define CLKID_SYS_CLK_TVFE		(SYS_BASE + 18)
#define CLKID_SYS_CLK_ETH		(SYS_BASE + 19)
#define CLKID_SYS_CLK_UART_A		(SYS_BASE + 20)
#define CLKID_SYS_CLK_UART_B		(SYS_BASE + 21)
#define CLKID_SYS_CLK_UART_C		(SYS_BASE + 22)
#define CLKID_SYS_CLK_CIPLUS		(SYS_BASE + 23)
#define CLKID_SYS_CLK_SPICC2		(SYS_BASE + 24)
#define CLKID_SYS_CLK_G2D		(SYS_BASE + 25)
#define CLKID_SYS_CLK_SPICC0		(SYS_BASE + 26)
#define CLKID_SYS_CLK_SPICC1		(SYS_BASE + 27)
#define CLKID_SYS_CLK_USB		(SYS_BASE + 28)
#define CLKID_SYS_CLK_M31PHY		(SYS_BASE + 29)
#define CLKID_SYS_CLK_I2C_M_A		(SYS_BASE + 30)
#define CLKID_SYS_CLK_I2C_M_B		(SYS_BASE + 31)
#define CLKID_SYS_CLK_I2C_M_C		(SYS_BASE + 32)
#define CLKID_SYS_CLK_I2C_M_D		(SYS_BASE + 33)
#define CLKID_SYS_CLK_I2C_M_E		(SYS_BASE + 34)
#define CLKID_SYS_CLK_I2C_S_A		(SYS_BASE + 35)
#define CLKID_SYS_CLK_HDMI20_ACE_CLK	(SYS_BASE + 36)
#define CLKID_SYS_CLK_HDMIRX_PCLK	(SYS_BASE + 37)
#define CLKID_SYS_CLK_MMC_PCLK		(SYS_BASE + 38)
#define CLKID_SYS_CLK_MMC_DMC		(SYS_BASE + 39)
#define CLKID_SYS_CLK_RSA		(SYS_BASE + 40)
#define CLKID_SYS_CLK_ATV_DMD		(SYS_BASE + 41)
#define CLKID_SYS_CLK_ADEC_TOP		(SYS_BASE + 42)
#define CLKID_SYS_CLK_VPU_INTR		(SYS_BASE + 43)
#define CLKID_SYS_CLK_FRC_INTR		(SYS_BASE + 44)
#define CLKID_SYS_CLK_SAR_ADC		(SYS_BASE + 45)
#define CLKID_SYS_CLK_GIC		(SYS_BASE + 46)
#define CLKID_SYS_CLK_TS_CPU		(SYS_BASE + 47)
#define CLKID_SYS_CLK_TS_VPU		(SYS_BASE + 48)
#define CLKID_SYS_CLK_PWM_AB		(SYS_BASE + 49)
#define CLKID_SYS_CLK_PWM_CD		(SYS_BASE + 50)
#define CLKID_SYS_CLK_PWM_EF		(SYS_BASE + 51)
#define CLKID_SYS_CLK_PWM_GH		(SYS_BASE + 52)
#define CLKID_SYS_CLK_TCON		(SYS_BASE + 53)
#define NR_CLKS				(SYS_BASE + 54)

#endif /* __T5M_CLKC_H */
