/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#ifndef VDEC_REGS_HEADER_
#define VDEC_REGS_HEADER_

#define VDEC_ASSIST_MMC_CTRL0       0x0001
#define VDEC_ASSIST_MMC_CTRL1       0x0002
/*add from M8M2*/
#define VDEC_ASSIST_MMC_CTRL2       0x0003
#define VDEC_ASSIST_MMC_CTRL3       0x0004
/**/
#define VDEC_ASSIST_AMR1_INT0       0x0025
#define VDEC_ASSIST_AMR1_INT1       0x0026
#define VDEC_ASSIST_AMR1_INT2       0x0027
#define VDEC_ASSIST_AMR1_INT3       0x0028
#define VDEC_ASSIST_AMR1_INT4       0x0029
#define VDEC_ASSIST_AMR1_INT5       0x002a
#define VDEC_ASSIST_AMR1_INT6       0x002b
#define VDEC_ASSIST_AMR1_INT7       0x002c
#define VDEC_ASSIST_AMR1_INT8       0x002d
#define VDEC_ASSIST_AMR1_INT9       0x002e
#define VDEC_ASSIST_AMR1_INTA       0x002f
#define VDEC_ASSIST_AMR1_INTB       0x0030
#define VDEC_ASSIST_AMR1_INTC       0x0031
#define VDEC_ASSIST_AMR1_INTD       0x0032
#define VDEC_ASSIST_AMR1_INTE       0x0033
#define VDEC_ASSIST_AMR1_INTF       0x0034
#define VDEC_ASSIST_AMR2_INT0       0x0035
#define VDEC_ASSIST_AMR2_INT1       0x0036
#define VDEC_ASSIST_AMR2_INT2       0x0037
#define VDEC_ASSIST_AMR2_INT3       0x0038
#define VDEC_ASSIST_AMR2_INT4       0x0039
#define VDEC_ASSIST_AMR2_INT5       0x003a
#define VDEC_ASSIST_AMR2_INT6       0x003b
#define VDEC_ASSIST_AMR2_INT7       0x003c
#define VDEC_ASSIST_AMR2_INT8       0x003d
#define VDEC_ASSIST_AMR2_INT9       0x003e
#define VDEC_ASSIST_AMR2_INTA       0x003f
#define VDEC_ASSIST_AMR2_INTB       0x0040
#define VDEC_ASSIST_AMR2_INTC       0x0041
#define VDEC_ASSIST_AMR2_INTD       0x0042
#define VDEC_ASSIST_AMR2_INTE       0x0043
#define VDEC_ASSIST_AMR2_INTF       0x0044
#define VDEC_ASSIST_MBX_SSEL        0x0045
#define VDEC_ASSIST_TIMER0_LO       0x0060
#define VDEC_ASSIST_TIMER0_HI       0x0061
#define VDEC_ASSIST_TIMER1_LO       0x0062
#define VDEC_ASSIST_TIMER1_HI       0x0063
#define VDEC_ASSIST_DMA_INT         0x0064
#define VDEC_ASSIST_DMA_INT_MSK     0x0065
#define VDEC_ASSIST_DMA_INT2        0x0066
#define VDEC_ASSIST_DMA_INT_MSK2    0x0067
#define VDEC_ASSIST_MBOX0_IRQ_REG   0x0070
#define VDEC_ASSIST_MBOX0_CLR_REG   0x0071
#define VDEC_ASSIST_MBOX0_MASK      0x0072
#define VDEC_ASSIST_MBOX0_FIQ_SEL   0x0073
#define VDEC_ASSIST_MBOX1_IRQ_REG   0x0074
#define VDEC_ASSIST_MBOX1_CLR_REG   0x0075
#define VDEC_ASSIST_MBOX1_MASK      0x0076
#define VDEC_ASSIST_MBOX1_FIQ_SEL   0x0077
#define VDEC_ASSIST_MBOX2_IRQ_REG   0x0078
#define VDEC_ASSIST_MBOX2_CLR_REG   0x0079
#define VDEC_ASSIST_MBOX2_MASK      0x007a
#define VDEC_ASSIST_MBOX2_FIQ_SEL   0x007b

#endif
