/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#define PDID_T7_DSPA		0
#define PDID_T7_DSPB		1
#define PDID_T7_DOS_HCODEC	2
#define PDID_T7_DOS_HEVC	3
#define PDID_T7_DOS_VDEC	4
#define PDID_T7_DOS_WAVE	5
#define PDID_T7_VPU_HDMI	6
#define PDID_T7_USB_COMB	7
#define PDID_T7_PCIE		8
#define PDID_T7_GE2D		9
#define PDID_T7_SRAMA		10
#define PDID_T7_SRAMB		11
#define PDID_T7_HDMIRX		12
#define PDID_T7_VI_CLK1		13
#define PDID_T7_VI_CLK2		14
#define PDID_T7_ETH			15
#define PDID_T7_ISP			16
#define PDID_T7_MIPI_ISP	17
#define PDID_T7_GDC			18
#define PDID_T7_CVE			18
#define PDID_T7_DEWARP		19
#define PDID_T7_SDIO_A		20
#define PDID_T7_SDIO_B		21
#define PDID_T7_EMMC		22
#define PDID_T7_MALI_SC0	23
#define PDID_T7_MALI_SC1	24
#define PDID_T7_MALI_SC2	25
#define PDID_T7_MALI_SC3	26
#define PDID_T7_MALI_TOP	27
#define PDID_T7_NNA_CORE0	28
#define PDID_T7_NNA_CORE1	29
#define PDID_T7_NNA_CORE2	30
#define PDID_T7_NNA_CORE3	31
#define PDID_T7_NNA_TOP		32
#define PDID_T7_DDR0		33
#define PDID_T7_DDR1		34
#define PDID_T7_DMC0		35
#define PDID_T7_DMC1		36
#define PDID_T7_NOC			37
#define PDID_T7_NIC2		38
#define PDID_T7_NIC3		39
#define PDID_T7_CCI			40
#define PDID_T7_MIPI_DSI0	41
#define PDID_T7_SPICC0		42
#define PDID_T7_SPICC1		43
#define PDID_T7_SPICC2		44
#define PDID_T7_SPICC3		45
#define PDID_T7_SPICC4		46
#define PDID_T7_SPICC5		47
#define PDID_T7_EDP0		48
#define PDID_T7_EDP1		49
#define PDID_T7_MIPI_DSI1	50
#define PDID_T7_AUDIO		51
