/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#ifndef VPP_REGS_V2_HEADER_
#define VPP_REGS_V2_HEADER_

#define VPP_CCORING_CTRL                        0x1d62
#define VPP_VE_ENABLE_CTRL                      0x1d63
#define VPP_BLACKEXT_CTRL                       0x1d64
#define VPP_VE_DEMO_CTRL                        0x1d65
#define VPP_DNLP_CTRL_00                        0x1d66
#define VPP_DNLP_CTRL_01                        0x1d67
#define VPP_DNLP_CTRL_02                        0x1d68
#define VPP_DNLP_CTRL_03                        0x1d69
#define VPP_DNLP_CTRL_04                        0x1d6a
#define VPP_DNLP_CTRL_05                        0x1d6b
#define VPP_DNLP_CTRL_06                        0x1d6c
#define VPP_DNLP_CTRL_07                        0x1d6d
#define VPP_DNLP_CTRL_08                        0x1d6e
#define VPP_DNLP_CTRL_09                        0x1d6f
#define VPP_DNLP_CTRL_10                        0x1d70
#define VPP_DNLP_CTRL_11                        0x1d71
#define VPP_DNLP_CTRL_12                        0x1d72
#define VPP_DNLP_CTRL_13                        0x1d73
#define VPP_DNLP_CTRL_14                        0x1d74
#define VPP_DNLP_CTRL_15                        0x1d75
#define VPP_CHROMA_ADDR_PORT                    0x1d76
#define VPP_CHROMA_DATA_PORT                    0x1d77
#define VPP_BLUE_STRETCH_1                      0x1dc0
#define VPP_BLUE_STRETCH_2                      0x1dc1
#define VPP_BLUE_STRETCH_3                      0x1dc2
#define VPP_BLUE_STRETCH_4                      0x1dc3
#define VPP_BLUE_STRETCH_5                      0x1dc4
#define VPP_VE_DEMO_CENTER_BAR                  0x1dc5
#define VPP_VE_DEMO_CENTER                      0x1dc6
#define VPP_VADJ1_MISC                          0x1d80
#define VPP_VADJ1_BLACK_VAL                     0x1d81
#define VPP_VADJ1_Y                             0x1d82
#define VPP_VADJ1_MA_MB                         0x1d83
#define VPP_VADJ1_MC_MD                         0x1d84
#define VPP_VADJ1_CURV_0                        0x1d85
#define VPP_VADJ1_CURV_1                        0x1d86
#define VPP_VADJ1_CURV_2                        0x1d87
#define VPP_VADJ1_CURV_3                        0x1d88
#define VPP_VD1_RGB_CTRST                       0x1d89
#define VPP_VD1_RGB_BRGHT                       0x1d8a
#define VPP_VD1_RGB_DLUT_0_3                    0x1d8b
#define VPP_VD1_RGB_DLUT_4_7                    0x1d8c
#define VPP_VD1_RGB_DLUT_8_11                   0x1d8d
#define VPP_VD1_MATRIX_COEF00_01                0x1d90
#define VPP_VD1_MATRIX_COEF02_10                0x1d91
#define VPP_VD1_MATRIX_COEF11_12                0x1d92
#define VPP_VD1_MATRIX_COEF20_21                0x1d93
#define VPP_VD1_MATRIX_COEF22                   0x1d94
#define VPP_VD1_MATRIX_COEF13_14                0x1d95
#define VPP_VD1_MATRIX_COEF23_24                0x1d96
#define VPP_VD1_MATRIX_COEF15_25                0x1d97
#define VPP_VD1_MATRIX_CLIP                     0x1d98
#define VPP_VD1_MATRIX_OFFSET0_1                0x1d99
#define VPP_VD1_MATRIX_OFFSET2                  0x1d9a
#define VPP_VD1_MATRIX_PRE_OFFSET0_1            0x1d9b
#define VPP_VD1_MATRIX_PRE_OFFSET2              0x1d9c
#define VPP_VD1_MATRIX_EN_CTRL                  0x1d9d
#define VPP_VD1_MATRIX_SAT                      0x1d9e

#define VPP_SLICE1_CCORING_CTRL                  0x2862
#define VPP_SLICE1_VE_ENABLE_CTRL                0x2863
#define VPP_SLICE1_BLACKEXT_CTRL                 0x2864
#define VPP_SLICE1_VE_DEMO_CTRL                  0x2865
#define VPP_SLICE1_DNLP_CTRL_00                  0x2866
#define VPP_SLICE1_DNLP_CTRL_01                  0x2867
#define VPP_SLICE1_DNLP_CTRL_02                  0x2868
#define VPP_SLICE1_DNLP_CTRL_03                  0x2869
#define VPP_SLICE1_DNLP_CTRL_04                  0x286a
#define VPP_SLICE1_DNLP_CTRL_05                  0x286b
#define VPP_SLICE1_DNLP_CTRL_06                  0x286c
#define VPP_SLICE1_DNLP_CTRL_07                  0x286d
#define VPP_SLICE1_DNLP_CTRL_08                  0x286e
#define VPP_SLICE1_DNLP_CTRL_09                  0x286f
#define VPP_SLICE1_DNLP_CTRL_10                  0x2870
#define VPP_SLICE1_DNLP_CTRL_11                  0x2871
#define VPP_SLICE1_DNLP_CTRL_12                  0x2872
#define VPP_SLICE1_DNLP_CTRL_13                  0x2873
#define VPP_SLICE1_DNLP_CTRL_14                  0x2874
#define VPP_SLICE1_DNLP_CTRL_15                  0x2875
#define VPP_SLICE1_CHROMA_ADDR_PORT              0x2876
#define VPP_SLICE1_CHROMA_DATA_PORT              0x2877
#define VPP_SLICE1_BLUE_STRETCH_1                0x28c0
#define VPP_SLICE1_BLUE_STRETCH_2                0x28c1
#define VPP_SLICE1_BLUE_STRETCH_3                0x28c2
#define VPP_SLICE1_BLUE_STRETCH_4                0x28c3
#define VPP_SLICE1_BLUE_STRETCH_5                0x28c4
#define VPP_SLICE1_VE_DEMO_CENTER_BAR            0x28c5
#define VPP_SLICE1_VE_DEMO_CENTER                0x28c6
#define VPP_SLICE1_VADJ1_MISC                    0x2880
#define VPP_SLICE1_VADJ1_BLACK_VAL               0x2881
#define VPP_SLICE1_VADJ1_Y                       0x2882
#define VPP_SLICE1_VADJ1_MA_MB                   0x2883
#define VPP_SLICE1_VADJ1_MC_MD                   0x2884
#define VPP_SLICE1_VADJ1_CURV_0                  0x2885
#define VPP_SLICE1_VADJ1_CURV_1                  0x2886
#define VPP_SLICE1_VADJ1_CURV_2                  0x2887
#define VPP_SLICE1_VADJ1_CURV_3                  0x2888
#define VPP_SLICE1_VD1_RGB_CTRST                 0x2889
#define VPP_SLICE1_VD1_RGB_BRGHT                 0x288a
#define VPP_SLICE1_VD1_RGB_DLUT_0_3              0x288b
#define VPP_SLICE1_VD1_RGB_DLUT_4_7              0x288c
#define VPP_SLICE1_VD1_RGB_DLUT_8_11             0x288d
#define VPP_SLICE1_VD1_MATRIX_COEF00_01          0x2890
#define VPP_SLICE1_VD1_MATRIX_COEF02_10          0x2891
#define VPP_SLICE1_VD1_MATRIX_COEF11_12          0x2892
#define VPP_SLICE1_VD1_MATRIX_COEF20_21          0x2893
#define VPP_SLICE1_VD1_MATRIX_COEF22             0x2894
#define VPP_SLICE1_VD1_MATRIX_COEF13_14          0x2895
#define VPP_SLICE1_VD1_MATRIX_COEF23_24          0x2896
#define VPP_SLICE1_VD1_MATRIX_COEF15_25          0x2897
#define VPP_SLICE1_VD1_MATRIX_CLIP               0x2898
#define VPP_SLICE1_VD1_MATRIX_OFFSET0_1          0x2899
#define VPP_SLICE1_VD1_MATRIX_OFFSET2            0x289a
#define VPP_SLICE1_VD1_MATRIX_PRE_OFFSET0_1      0x289b
#define VPP_SLICE1_VD1_MATRIX_PRE_OFFSET2        0x289c
#define VPP_SLICE1_VD1_MATRIX_EN_CTRL            0x289d
#define VPP_SLICE1_VD1_MATRIX_SAT                0x289e

#define VPP_SLICE2_CCORING_CTRL                  0x2962
#define VPP_SLICE2_VE_ENABLE_CTRL                0x2963
#define VPP_SLICE2_BLACKEXT_CTRL                 0x2964
#define VPP_SLICE2_VE_DEMO_CTRL                  0x2965
#define VPP_SLICE2_DNLP_CTRL_00                  0x2966
#define VPP_SLICE2_DNLP_CTRL_01                  0x2967
#define VPP_SLICE2_DNLP_CTRL_02                  0x2968
#define VPP_SLICE2_DNLP_CTRL_03                  0x2969
#define VPP_SLICE2_DNLP_CTRL_04                  0x296a
#define VPP_SLICE2_DNLP_CTRL_05                  0x296b
#define VPP_SLICE2_DNLP_CTRL_06                  0x296c
#define VPP_SLICE2_DNLP_CTRL_07                  0x296d
#define VPP_SLICE2_DNLP_CTRL_08                  0x296e
#define VPP_SLICE2_DNLP_CTRL_09                  0x296f
#define VPP_SLICE2_DNLP_CTRL_10                  0x2970
#define VPP_SLICE2_DNLP_CTRL_11                  0x2971
#define VPP_SLICE2_DNLP_CTRL_12                  0x2972
#define VPP_SLICE2_DNLP_CTRL_13                  0x2973
#define VPP_SLICE2_DNLP_CTRL_14                  0x2974
#define VPP_SLICE2_DNLP_CTRL_15                  0x2975
#define VPP_SLICE2_CHROMA_ADDR_PORT              0x2976
#define VPP_SLICE2_CHROMA_DATA_PORT              0x2977
#define VPP_SLICE2_BLUE_STRETCH_1                0x29c0
#define VPP_SLICE2_BLUE_STRETCH_2                0x29c1
#define VPP_SLICE2_BLUE_STRETCH_3                0x29c2
#define VPP_SLICE2_BLUE_STRETCH_4                0x29c3
#define VPP_SLICE2_BLUE_STRETCH_5                0x29c4
#define VPP_SLICE2_VE_DEMO_CENTER_BAR            0x29c5
#define VPP_SLICE2_VE_DEMO_CENTER                0x29c6
#define VPP_SLICE2_VADJ1_MISC                    0x2980
#define VPP_SLICE2_VADJ1_BLACK_VAL               0x2981
#define VPP_SLICE2_VADJ1_Y                       0x2982
#define VPP_SLICE2_VADJ1_MA_MB                   0x2983
#define VPP_SLICE2_VADJ1_MC_MD                   0x2984
#define VPP_SLICE2_VADJ1_CURV_0                  0x2985
#define VPP_SLICE2_VADJ1_CURV_1                  0x2986
#define VPP_SLICE2_VADJ1_CURV_2                  0x2987
#define VPP_SLICE2_VADJ1_CURV_3                  0x2988
#define VPP_SLICE2_VD1_RGB_CTRST                 0x2989
#define VPP_SLICE2_VD1_RGB_BRGHT                 0x298a
#define VPP_SLICE2_VD1_RGB_DLUT_0_3              0x298b
#define VPP_SLICE2_VD1_RGB_DLUT_4_7              0x298c
#define VPP_SLICE2_VD1_RGB_DLUT_8_11             0x298d
#define VPP_SLICE2_VD1_MATRIX_COEF00_01          0x2990
#define VPP_SLICE2_VD1_MATRIX_COEF02_10          0x2991
#define VPP_SLICE2_VD1_MATRIX_COEF11_12          0x2992
#define VPP_SLICE2_VD1_MATRIX_COEF20_21          0x2993
#define VPP_SLICE2_VD1_MATRIX_COEF22             0x2994
#define VPP_SLICE2_VD1_MATRIX_COEF13_14          0x2995
#define VPP_SLICE2_VD1_MATRIX_COEF23_24          0x2996
#define VPP_SLICE2_VD1_MATRIX_COEF15_25          0x2997
#define VPP_SLICE2_VD1_MATRIX_CLIP               0x2998
#define VPP_SLICE2_VD1_MATRIX_OFFSET0_1          0x2999
#define VPP_SLICE2_VD1_MATRIX_OFFSET2            0x299a
#define VPP_SLICE2_VD1_MATRIX_PRE_OFFSET0_1      0x299b
#define VPP_SLICE2_VD1_MATRIX_PRE_OFFSET2        0x299c
#define VPP_SLICE2_VD1_MATRIX_EN_CTRL            0x299d
#define VPP_SLICE2_VD1_MATRIX_SAT                0x299e

#define VPP_SLICE3_CCORING_CTRL                  0x2a62
#define VPP_SLICE3_VE_ENABLE_CTRL                0x2a63
#define VPP_SLICE3_BLACKEXT_CTRL                 0x2a64
#define VPP_SLICE3_VE_DEMO_CTRL                  0x2a65
#define VPP_SLICE3_DNLP_CTRL_00                  0x2a66
#define VPP_SLICE3_DNLP_CTRL_01                  0x2a67
#define VPP_SLICE3_DNLP_CTRL_02                  0x2a68
#define VPP_SLICE3_DNLP_CTRL_03                  0x2a69
#define VPP_SLICE3_DNLP_CTRL_04                  0x2a6a
#define VPP_SLICE3_DNLP_CTRL_05                  0x2a6b
#define VPP_SLICE3_DNLP_CTRL_06                  0x2a6c
#define VPP_SLICE3_DNLP_CTRL_07                  0x2a6d
#define VPP_SLICE3_DNLP_CTRL_08                  0x2a6e
#define VPP_SLICE3_DNLP_CTRL_09                  0x2a6f
#define VPP_SLICE3_DNLP_CTRL_10                  0x2a70
#define VPP_SLICE3_DNLP_CTRL_11                  0x2a71
#define VPP_SLICE3_DNLP_CTRL_12                  0x2a72
#define VPP_SLICE3_DNLP_CTRL_13                  0x2a73
#define VPP_SLICE3_DNLP_CTRL_14                  0x2a74
#define VPP_SLICE3_DNLP_CTRL_15                  0x2a75
#define VPP_SLICE3_CHROMA_ADDR_PORT              0x2a76
#define VPP_SLICE3_CHROMA_DATA_PORT              0x2a77
#define VPP_SLICE3_BLUE_STRETCH_1                0x2ac0
#define VPP_SLICE3_BLUE_STRETCH_2                0x2ac1
#define VPP_SLICE3_BLUE_STRETCH_3                0x2ac2
#define VPP_SLICE3_BLUE_STRETCH_4                0x2ac3
#define VPP_SLICE3_BLUE_STRETCH_5                0x2ac4
#define VPP_SLICE3_VE_DEMO_CENTER_BAR            0x2ac5
#define VPP_SLICE3_VE_DEMO_CENTER                0x2ac6
#define VPP_SLICE3_VADJ1_MISC                    0x2a80
#define VPP_SLICE3_VADJ1_BLACK_VAL               0x2a81
#define VPP_SLICE3_VADJ1_Y                       0x2a82
#define VPP_SLICE3_VADJ1_MA_MB                   0x2a83
#define VPP_SLICE3_VADJ1_MC_MD                   0x2a84
#define VPP_SLICE3_VADJ1_CURV_0                  0x2a85
#define VPP_SLICE3_VADJ1_CURV_1                  0x2a86
#define VPP_SLICE3_VADJ1_CURV_2                  0x2a87
#define VPP_SLICE3_VADJ1_CURV_3                  0x2a88
#define VPP_SLICE3_VD1_RGB_CTRST                 0x2a89
#define VPP_SLICE3_VD1_RGB_BRGHT                 0x2a8a
#define VPP_SLICE3_VD1_RGB_DLUT_0_3              0x2a8b
#define VPP_SLICE3_VD1_RGB_DLUT_4_7              0x2a8c
#define VPP_SLICE3_VD1_RGB_DLUT_8_11             0x2a8d
#define VPP_SLICE3_VD1_MATRIX_COEF00_01          0x2a90
#define VPP_SLICE3_VD1_MATRIX_COEF02_10          0x2a91
#define VPP_SLICE3_VD1_MATRIX_COEF11_12          0x2a92
#define VPP_SLICE3_VD1_MATRIX_COEF20_21          0x2a93
#define VPP_SLICE3_VD1_MATRIX_COEF22             0x2a94
#define VPP_SLICE3_VD1_MATRIX_COEF13_14          0x2a95
#define VPP_SLICE3_VD1_MATRIX_COEF23_24          0x2a96
#define VPP_SLICE3_VD1_MATRIX_COEF15_25          0x2a97
#define VPP_SLICE3_VD1_MATRIX_CLIP               0x2a98
#define VPP_SLICE3_VD1_MATRIX_OFFSET0_1          0x2a99
#define VPP_SLICE3_VD1_MATRIX_OFFSET2            0x2a9a
#define VPP_SLICE3_VD1_MATRIX_PRE_OFFSET0_1      0x2a9b
#define VPP_SLICE3_VD1_MATRIX_PRE_OFFSET2        0x2a9c
#define VPP_SLICE3_VD1_MATRIX_EN_CTRL            0x2a9d
#define VPP_SLICE3_VD1_MATRIX_SAT                0x2a9e

#define VD_PROC_SR0_CTRL                        0x2800
#define VD_PROC_SR1_CTRL                        0x2801
#define VD_PROC_S0_IN_SIZE                      0x2802
#define VD_PROC_S0_OUT_SIZE                     0x2803
#define VD_PROC_S0_PPS_IN_SIZE                  0x2804
#define VD_PROC_S0_SR0_IN_SIZE                  0x2805
#define VD_PROC_S0_SR1_IN_SIZE                  0x2806
#define VD_PROC_S1_IN_SIZE                      0x2807
#define VD_PROC_S1_OUT_SIZE                     0x2808
#define VD_PROC_S1_SR0_IN_SIZE                  0x2809
#define VD_PROC_S2_IN_SIZE                      0x280a
#define VD_PROC_S2_OUT_SIZE                     0x280b
#define VD_PROC_S3_IN_SIZE                      0x280c
#define VD_PROC_S3_OUT_SIZE                     0x280d
#define VD_PROC_GCLK_CTRL                       0x280e
#define VD_PROC_BYPASS_CTRL                     0x280f
#define VD_S0_HWIN_CUT                          0x2810
#define VD_S1_HWIN_CUT                          0x2811
#define VD_S2_HWIN_CUT                          0x2812
#define VD_S3_HWIN_CUT                          0x2813

#define VPP_VD_SYS_GCLK_CTRL                    0x3200
#define VPP_VD_PREBLND_H_V_SIZE                 0x3201
#define VPP_VD_PREBLND_CTRL                     0x3202
#define VPP_PREBLEND_VD1_H_START_END            0x3203
#define VPP_PREBLEND_VD1_V_START_END            0x3204
#define VPP_PREBLEND_VD2_H_START_END            0x3205
#define VPP_PREBLEND_VD2_V_START_END            0x3206
#define VPP_VD_BLND_H_V_SIZE                    0x3209
#define VPP_VD_BLND_CTRL                        0x320a
#define VPP_BLEND_VD1_S0_H_START_END            0x320b
#define VPP_BLEND_VD1_S0_V_START_END            0x320c
#define VPP_BLEND_VD1_S1_H_START_END            0x320d
#define VPP_BLEND_VD1_S1_V_START_END            0x320e
#define VPP_BLEND_VD1_S2_H_START_END            0x320f
#define VPP_BLEND_VD1_S2_V_START_END            0x3210
#define VPP_BLEND_VD1_S3_H_START_END            0x3211
#define VPP_BLEND_VD1_S3_V_START_END            0x3212
#define VPP_VD_SYS_CTRL                         0x3217
#define VPP_VD_PRE_BLEND_CTRL                   0x3240
#define VPP_VD_PRE_BLEND_DUMMY_DATA             0x3241
#define VPP_VD_PRE_BLEND_DUMMY_ALPHA            0x3242
#define VPP_VD_PRE_BLEND_RO_CURRENT_XY          0x3243
#define VPP_VD_PRE_BLEND_DUMMY_ALPHA1           0x3244
#define VPP_VD_PRE_BLEND_OSD_FLAG_CTRL          0x3245
#define VPP_VD_BLEND_CTRL                       0x3246
#define VPP_VD_BLEND_DUMMY_DATA                 0x3247
#define VPP_VD_BLEND_DUMMY_ALPHA                0x3248
#define VPP_VD_BLEND_RO_CURRENT_XY              0x3249
#define VPP_VD_BLEND_DUMMY_ALPHA1               0x324a
#define VPP_VD_BLEND_OSD_FLAG_CTRL              0x324b

#define VD1_HDR2_CTRL                           0x25a0
#define VD1_HDR2_CLK_GATE                       0x25a1
#define VD1_HDR2_MATRIXI_COEF00_01              0x25a2
#define VD1_HDR2_MATRIXI_COEF02_10              0x25a3
#define VD1_HDR2_MATRIXI_COEF20_21              0x25a5
#define VD1_HDR2_MATRIXI_COEF22                 0x25a6
#define VD1_HDR2_MATRIXI_COEF30_31              0x25a7
#define VD1_HDR2_MATRIXI_COEF32_40              0x25a8
#define VD1_HDR2_MATRIXI_COEF41_42              0x25a9
#define VD1_HDR2_MATRIXI_OFFSET0_1              0x25aa
#define VD1_HDR2_MATRIXI_OFFSET2                0x25ab
#define VD1_HDR2_MATRIXI_PRE_OFFSET0_1          0x25ac
#define VD1_HDR2_MATRIXI_PRE_OFFSET2            0x25ad
#define VD1_HDR2_MATRIXO_COEF00_01              0x25ae
#define VD1_HDR2_MATRIXO_COEF02_10              0x25af
#define VD1_HDR2_MATRIXO_COEF11_12              0x25b0
#define VD1_HDR2_MATRIXO_COEF20_21              0x25b1
#define VD1_HDR2_MATRIXO_COEF22                 0x25b2
#define VD1_HDR2_MATRIXO_COEF30_31              0x25b3
#define VD1_HDR2_MATRIXO_COEF32_40              0x25b4
#define VD1_HDR2_MATRIXO_COEF41_42              0x25b5
#define VD1_HDR2_MATRIXO_OFFSET0_1              0x25b6
#define VD1_HDR2_MATRIXO_OFFSET2                0x25b7
#define VD1_HDR2_MATRIXO_PRE_OFFSET0_1          0x25b8
#define VD1_HDR2_MATRIXO_PRE_OFFSET2            0x25b9
#define VD1_HDR2_MATRIXI_CLIP                   0x25ba
#define VD1_HDR2_MATRIXO_CLIP                   0x25bb
#define VD1_HDR2_CGAIN_OFFT                     0x25bc
#define VD1_EOTF_LUT_ADDR_PORT                  0x25be
#define VD1_EOTF_LUT_DATA_PORT                  0x25bf
#define VD1_OETF_LUT_ADDR_PORT                  0x25c0
#define VD1_OETF_LUT_DATA_PORT                  0x25c1
#define VD1_CGAIN_LUT_ADDR_PORT                 0x25c2
#define VD1_CGAIN_LUT_DATA_PORT                 0x25c3
#define VD1_HDR2_CGAIN_COEF0                    0x25c4
#define VD1_HDR2_CGAIN_COEF1                    0x25c5
#define VD1_OGAIN_LUT_ADDR_PORT                 0x25c6
#define VD1_OGAIN_LUT_DATA_PORT                 0x25c7
#define VD1_HDR2_ADPS_CTRL                      0x25c8
#define VD1_HDR2_ADPS_ALPHA0                    0x25c9
#define VD1_HDR2_ADPS_ALPHA1                    0x25ca
#define VD1_HDR2_ADPS_BETA0                     0x25cb
#define VD1_HDR2_ADPS_BETA1                     0x25cc
#define VD1_HDR2_ADPS_BETA2                     0x25cd
#define VD1_HDR2_ADPS_COEF0                     0x25ce
#define VD1_HDR2_ADPS_COEF1                     0x25cf
#define VD1_HDR2_GMUT_CTRL                      0x25d0
#define VD1_HDR2_GMUT_COEF0                     0x25d1
#define VD1_HDR2_GMUT_COEF1                     0x25d2
#define VD1_HDR2_GMUT_COEF2                     0x25d3
#define VD1_HDR2_GMUT_COEF3                     0x25d4
#define VD1_HDR2_GMUT_COEF4                     0x25d5
#define VD1_HDR2_PIPE_CTRL1                     0x25d6
#define VD1_HDR2_PIPE_CTRL2                     0x25d7
#define VD1_HDR2_PIPE_CTRL3                     0x25d8
#define VD1_HDR2_PROC_WIN1                      0x25d9
#define VD1_HDR2_PROC_WIN2                      0x25da
#define VD1_HDR2_MATRIXI_EN_CTRL                0x25db
#define VD1_HDR2_MATRIXO_EN_CTRL                0x25dc
#define VD1_HDR2_HIST_CTRL                      0x25dd
#define VD1_HDR2_HIST_H_START_END               0x25de
#define VD1_HDR2_HIST_V_START_END               0x25df
#define VD1_HDR2_HIST_RD                        0x25e0

#define VD1_SLICE1_HDR2_CTRL                    0x26a0
#define VD1_SLICE1_HDR2_CLK_GATE                0x26a1
#define VD1_SLICE1_HDR2_MATRIXI_COEF00_01       0x26a2
#define VD1_SLICE1_HDR2_MATRIXI_COEF02_10       0x26a3
#define VD1_SLICE1_HDR2_MATRIXI_COEF11_12       0x26a4
#define VD1_SLICE1_HDR2_MATRIXI_COEF20_21       0x26a5
#define VD1_SLICE1_HDR2_MATRIXI_COEF22          0x26a6
#define VD1_SLICE1_HDR2_MATRIXI_COEF30_31       0x26a7
#define VD1_SLICE1_HDR2_MATRIXI_COEF32_40       0x26a8
#define VD1_SLICE1_HDR2_MATRIXI_COEF41_42       0x26a9
#define VD1_SLICE1_HDR2_MATRIXI_OFFSET0_1       0x26aa
#define VD1_SLICE1_HDR2_MATRIXI_OFFSET2         0x26ab
#define VD1_SLICE1_HDR2_MATRIXI_PRE_OFFSET0_1   0x26ac
#define VD1_SLICE1_HDR2_MATRIXI_PRE_OFFSET2     0x26ad
#define VD1_SLICE1_HDR2_MATRIXO_COEF00_01       0x26ae
#define VD1_SLICE1_HDR2_MATRIXO_COEF02_10       0x26af
#define VD1_SLICE1_HDR2_MATRIXO_COEF11_12       0x26b0
#define VD1_SLICE1_HDR2_MATRIXO_COEF20_21       0x26b1
#define VD1_SLICE1_HDR2_MATRIXO_COEF22          0x26b2
#define VD1_SLICE1_HDR2_MATRIXO_COEF30_31       0x26b3
#define VD1_SLICE1_HDR2_MATRIXO_COEF32_40       0x26b4
#define VD1_SLICE1_HDR2_MATRIXO_COEF41_42       0x26b5
#define VD1_SLICE1_HDR2_MATRIXO_OFFSET0_1       0x26b6
#define VD1_SLICE1_HDR2_MATRIXO_OFFSET2         0x26b7
#define VD1_SLICE1_HDR2_MATRIXO_PRE_OFFSET0_1   0x26b8
#define VD1_SLICE1_HDR2_MATRIXO_PRE_OFFSET2     0x26b9
#define VD1_SLICE1_HDR2_MATRIXI_CLIP            0x26ba
#define VD1_SLICE1_HDR2_MATRIXO_CLIP            0x26bb
#define VD1_SLICE1_HDR2_CGAIN_OFFT              0x26bc
#define VD1_SLICE1_EOTF_LUT_ADDR_PORT           0x26be
#define VD1_SLICE1_EOTF_LUT_DATA_PORT           0x26bf
#define VD1_SLICE1_OETF_LUT_ADDR_PORT           0x26c0
#define VD1_SLICE1_OETF_LUT_DATA_PORT           0x26c1
#define VD1_SLICE1_CGAIN_LUT_ADDR_PORT          0x26c2
#define VD1_SLICE1_CGAIN_LUT_DATA_PORT          0x26c3
#define VD1_SLICE1_HDR2_CGAIN_COEF0             0x26c4
#define VD1_SLICE1_HDR2_CGAIN_COEF1             0x26c5
#define VD1_SLICE1_OGAIN_LUT_ADDR_PORT          0x26c6
#define VD1_SLICE1_OGAIN_LUT_DATA_PORT          0x26c7
#define VD1_SLICE1_HDR2_ADPS_CTRL               0x26c8
#define VD1_SLICE1_HDR2_ADPS_ALPHA0             0x26c9
#define VD1_SLICE1_HDR2_ADPS_ALPHA1             0x26ca
#define VD1_SLICE1_HDR2_ADPS_BETA0              0x26cb
#define VD1_SLICE1_HDR2_ADPS_BETA1              0x26cc
#define VD1_SLICE1_HDR2_ADPS_BETA2              0x26cd
#define VD1_SLICE1_HDR2_ADPS_COEF0              0x26ce
#define VD1_SLICE1_HDR2_ADPS_COEF1              0x26cf
#define VD1_SLICE1_HDR2_GMUT_CTRL               0x26d0
#define VD1_SLICE1_HDR2_GMUT_COEF0              0x26d1
#define VD1_SLICE1_HDR2_GMUT_COEF1              0x26d2
#define VD1_SLICE1_HDR2_GMUT_COEF2              0x26d3
#define VD1_SLICE1_HDR2_GMUT_COEF3              0x26d4
#define VD1_SLICE1_HDR2_GMUT_COEF4              0x26d5
#define VD1_SLICE1_HDR2_PIPE_CTRL1              0x26d6
#define VD1_SLICE1_HDR2_PIPE_CTRL2              0x26d7
#define VD1_SLICE1_HDR2_PIPE_CTRL3              0x26d8
#define VD1_SLICE1_HDR2_PROC_WIN1               0x26d9
#define VD1_SLICE1_HDR2_PROC_WIN2               0x26da
#define VD1_SLICE1_HDR2_MATRIXI_EN_CTRL         0x26db
#define VD1_SLICE1_HDR2_MATRIXO_EN_CTRL         0x26dc
#define VD1_SLICE1_HDR2_HIST_CTRL               0x26dd
#define VD1_SLICE1_HDR2_HIST_H_START_END        0x26de
#define VD1_SLICE1_HDR2_HIST_V_START_END        0x26df
#define VD1_SLICE1_HDR2_HIST_RD                 0x26e0

#define VD1_SLICE2_HDR2_CTRL                    0x2ca0
#define VD1_SLICE2_HDR2_CLK_GATE                0x2ca1
#define VD1_SLICE2_HDR2_MATRIXI_COEF00_01       0x2ca2
#define VD1_SLICE2_HDR2_MATRIXI_COEF02_10       0x2ca3
#define VD1_SLICE2_HDR2_MATRIXI_COEF11_12       0x2ca4
#define VD1_SLICE2_HDR2_MATRIXI_COEF20_21       0x2ca5
#define VD1_SLICE2_HDR2_MATRIXI_COEF22          0x2ca6
#define VD1_SLICE2_HDR2_MATRIXI_COEF30_31       0x2ca7
#define VD1_SLICE2_HDR2_MATRIXI_COEF32_40       0x2ca8
#define VD1_SLICE2_HDR2_MATRIXI_COEF41_42       0x2ca9
#define VD1_SLICE2_HDR2_MATRIXI_OFFSET0_1       0x2caa
#define VD1_SLICE2_HDR2_MATRIXI_OFFSET2         0x2cab
#define VD1_SLICE2_HDR2_MATRIXI_PRE_OFFSET0_1   0x2cac
#define VD1_SLICE2_HDR2_MATRIXI_PRE_OFFSET2     0x2cad
#define VD1_SLICE2_HDR2_MATRIXO_COEF00_01       0x2cae
#define VD1_SLICE2_HDR2_MATRIXO_COEF02_10       0x2caf
#define VD1_SLICE2_HDR2_MATRIXO_COEF11_12       0x2cb0
#define VD1_SLICE2_HDR2_MATRIXO_COEF20_21       0x2cb1
#define VD1_SLICE2_HDR2_MATRIXO_COEF22          0x2cb2
#define VD1_SLICE2_HDR2_MATRIXO_COEF30_31       0x2cb3
#define VD1_SLICE2_HDR2_MATRIXO_COEF32_40       0x2cb4
#define VD1_SLICE2_HDR2_MATRIXO_COEF41_42       0x2cb5
#define VD1_SLICE2_HDR2_MATRIXO_OFFSET0_1       0x2cb6
#define VD1_SLICE2_HDR2_MATRIXO_OFFSET2         0x2cb7
#define VD1_SLICE2_HDR2_MATRIXO_PRE_OFFSET0_1   0x2cb8
#define VD1_SLICE2_HDR2_MATRIXO_PRE_OFFSET2     0x2cb9
#define VD1_SLICE2_HDR2_MATRIXI_CLIP            0x2cba
#define VD1_SLICE2_HDR2_MATRIXO_CLIP            0x2cbb
#define VD1_SLICE2_HDR2_CGAIN_OFFT              0x2cbc
#define VD1_SLICE2_EOTF_LUT_ADDR_PORT           0x2cbe
#define VD1_SLICE2_EOTF_LUT_DATA_PORT           0x2cbf
#define VD1_SLICE2_OETF_LUT_ADDR_PORT           0x2cc0
#define VD1_SLICE2_OETF_LUT_DATA_PORT           0x2cc1
#define VD1_SLICE2_CGAIN_LUT_ADDR_PORT          0x2cc2
#define VD1_SLICE2_CGAIN_LUT_DATA_PORT          0x2cc3
#define VD1_SLICE2_HDR2_CGAIN_COEF0             0x2cc4
#define VD1_SLICE2_HDR2_CGAIN_COEF1             0x2cc5
#define VD1_SLICE2_OGAIN_LUT_ADDR_PORT          0x2cc6
#define VD1_SLICE2_OGAIN_LUT_DATA_PORT          0x2cc7
#define VD1_SLICE2_HDR2_ADPS_CTRL               0x2cc8
#define VD1_SLICE2_HDR2_ADPS_ALPHA0             0x2cc9
#define VD1_SLICE2_HDR2_ADPS_ALPHA1             0x2cca
#define VD1_SLICE2_HDR2_ADPS_BETA0              0x2ccb
#define VD1_SLICE2_HDR2_ADPS_BETA1              0x2ccc
#define VD1_SLICE2_HDR2_ADPS_BETA2              0x2ccd
#define VD1_SLICE2_HDR2_ADPS_COEF0              0x2cce
#define VD1_SLICE2_HDR2_ADPS_COEF1              0x2ccf
#define VD1_SLICE2_HDR2_GMUT_CTRL               0x2cd0
#define VD1_SLICE2_HDR2_GMUT_COEF0              0x2cd1
#define VD1_SLICE2_HDR2_GMUT_COEF1              0x2cd2
#define VD1_SLICE2_HDR2_GMUT_COEF2              0x2cd3
#define VD1_SLICE2_HDR2_GMUT_COEF3              0x2cd4
#define VD1_SLICE2_HDR2_GMUT_COEF4              0x2cd5
#define VD1_SLICE2_HDR2_PIPE_CTRL1              0x2cd6
#define VD1_SLICE2_HDR2_PIPE_CTRL2              0x2cd7
#define VD1_SLICE2_HDR2_PIPE_CTRL3              0x2cd8
#define VD1_SLICE2_HDR2_PROC_WIN1               0x2cd9
#define VD1_SLICE2_HDR2_PROC_WIN2               0x2cda
#define VD1_SLICE2_HDR2_MATRIXI_EN_CTRL         0x2cdb
#define VD1_SLICE2_HDR2_MATRIXO_EN_CTRL         0x2cdc
#define VD1_SLICE2_HDR2_HIST_CTRL               0x2cdd
#define VD1_SLICE2_HDR2_HIST_H_START_END        0x2cde
#define VD1_SLICE2_HDR2_HIST_V_START_END        0x2cdf
#define VD1_SLICE2_HDR2_HIST_RD                 0x2ce0

#define VD1_SLICE3_HDR2_CTRL                    0x3ea0
#define VD1_SLICE3_HDR2_CLK_GATE                0x3ea1
#define VD1_SLICE3_HDR2_MATRIXI_COEF00_01       0x3ea2
#define VD1_SLICE3_HDR2_MATRIXI_COEF02_10       0x3ea3
#define VD1_SLICE3_HDR2_MATRIXI_COEF11_12       0x3ea4
#define VD1_SLICE3_HDR2_MATRIXI_COEF20_21       0x3ea5
#define VD1_SLICE3_HDR2_MATRIXI_COEF22          0x3ea6
#define VD1_SLICE3_HDR2_MATRIXI_COEF30_31       0x3ea7
#define VD1_SLICE3_HDR2_MATRIXI_COEF32_40       0x3ea8
#define VD1_SLICE3_HDR2_MATRIXI_COEF41_42       0x3ea9
#define VD1_SLICE3_HDR2_MATRIXI_OFFSET0_1       0x3eaa
#define VD1_SLICE3_HDR2_MATRIXI_OFFSET2         0x3eab
#define VD1_SLICE3_HDR2_MATRIXI_PRE_OFFSET0_1   0x3eac
#define VD1_SLICE3_HDR2_MATRIXI_PRE_OFFSET2     0x3ead
#define VD1_SLICE3_HDR2_MATRIXO_COEF00_01       0x3eae
#define VD1_SLICE3_HDR2_MATRIXO_COEF02_10       0x3eaf
#define VD1_SLICE3_HDR2_MATRIXO_COEF11_12       0x3eb0
#define VD1_SLICE3_HDR2_MATRIXO_COEF20_21       0x3eb1
#define VD1_SLICE3_HDR2_MATRIXO_COEF22          0x3eb2
#define VD1_SLICE3_HDR2_MATRIXO_COEF30_31       0x3eb3
#define VD1_SLICE3_HDR2_MATRIXO_COEF32_40       0x3eb4
#define VD1_SLICE3_HDR2_MATRIXO_COEF41_42       0x3eb5
#define VD1_SLICE3_HDR2_MATRIXO_OFFSET0_1       0x3eb6
#define VD1_SLICE3_HDR2_MATRIXO_OFFSET2         0x3eb7
#define VD1_SLICE3_HDR2_MATRIXO_PRE_OFFSET0_1   0x3eb8
#define VD1_SLICE3_HDR2_MATRIXO_PRE_OFFSET2     0x3eb9
#define VD1_SLICE3_HDR2_MATRIXI_CLIP            0x3eba
#define VD1_SLICE3_HDR2_MATRIXO_CLIP            0x3ebb
#define VD1_SLICE3_HDR2_CGAIN_OFFT              0x3ebc
#define VD1_SLICE3_EOTF_LUT_ADDR_PORT           0x3ebe
#define VD1_SLICE3_EOTF_LUT_DATA_PORT           0x3ebf
#define VD1_SLICE3_OETF_LUT_ADDR_PORT           0x3ec0
#define VD1_SLICE3_OETF_LUT_DATA_PORT           0x3ec1
#define VD1_SLICE3_CGAIN_LUT_ADDR_PORT          0x3ec2
#define VD1_SLICE3_CGAIN_LUT_DATA_PORT          0x3ec3
#define VD1_SLICE3_HDR2_CGAIN_COEF0             0x3ec4
#define VD1_SLICE3_HDR2_CGAIN_COEF1             0x3ec5
#define VD1_SLICE3_OGAIN_LUT_ADDR_PORT          0x3ec6
#define VD1_SLICE3_OGAIN_LUT_DATA_PORT          0x3ec7
#define VD1_SLICE3_HDR2_ADPS_CTRL               0x3ec8
#define VD1_SLICE3_HDR2_ADPS_ALPHA0             0x3ec9
#define VD1_SLICE3_HDR2_ADPS_ALPHA1             0x3eca
#define VD1_SLICE3_HDR2_ADPS_BETA0              0x3ecb
#define VD1_SLICE3_HDR2_ADPS_BETA1              0x3ecc
#define VD1_SLICE3_HDR2_ADPS_BETA2              0x3ecd
#define VD1_SLICE3_HDR2_ADPS_COEF0              0x3ece
#define VD1_SLICE3_HDR2_ADPS_COEF1              0x3ecf
#define VD1_SLICE3_HDR2_GMUT_CTRL               0x3ed0
#define VD1_SLICE3_HDR2_GMUT_COEF0              0x3ed1
#define VD1_SLICE3_HDR2_GMUT_COEF1              0x3ed2
#define VD1_SLICE3_HDR2_GMUT_COEF2              0x3ed3
#define VD1_SLICE3_HDR2_GMUT_COEF3              0x3ed4
#define VD1_SLICE3_HDR2_GMUT_COEF4              0x3ed5
#define VD1_SLICE3_HDR2_PIPE_CTRL1              0x3ed6
#define VD1_SLICE3_HDR2_PIPE_CTRL2              0x3ed7
#define VD1_SLICE3_HDR2_PIPE_CTRL3              0x3ed8
#define VD1_SLICE3_HDR2_PROC_WIN1               0x3ed9
#define VD1_SLICE3_HDR2_PROC_WIN2               0x3eda
#define VD1_SLICE3_HDR2_MATRIXI_EN_CTRL         0x3edb
#define VD1_SLICE3_HDR2_MATRIXO_EN_CTRL         0x3edc
#define VD1_SLICE3_HDR2_HIST_CTRL               0x3edd
#define VD1_SLICE3_HDR2_HIST_H_START_END        0x3ede
#define VD1_SLICE3_HDR2_HIST_V_START_END        0x3edf
#define VD1_SLICE3_HDR2_HIST_RD                 0x3ee0

#define VPP_GCLK_CTRL                           0x2500
#define VPP_DOLBY_CTRL                          0x2501
#define VPP_SYNC_SEL0                           0x2502
#define VPP_OUT_H_V_SIZE                        0x2503
#define VPP_OFIFO_SIZE                          0x2504
#define VPP_OFIFO_URG_CTRL                      0x2505
#define VPP_FIFO_STATUS                         0x2506
#define VPP_CLIP_MISC0                          0x2507
#define VPP_CLIP_MISC1                          0x2508
#define VPP_MISC                                0x2509
#define VPP_CRC_CHK                             0x250a
#define VPP_RO_CRCSUM                           0x250b
#define VPP_SLC_DEAL_CTRL                       0x250c
#define VPP_HWIN_SIZE                           0x250d
#define VPP_ALIGN_FIFO_SIZE                     0x250e
#define VPP_GAMMA_CTRL                          0x2530
#define VPP_GAMMA_BIN_ADDR                      0x2531
#define VPP_GAMMA_BIN_DATA                      0x2532
#define VPP_GAINOFF_CTRL0                       0x2550
#define VPP_GAINOFF_CTRL1                       0x2551
#define VPP_GAINOFF_CTRL2                       0x2552
#define VPP_GAINOFF_CTRL3                       0x2553
#define VPP_GAINOFF_CTRL4                       0x2554
#define VPP_GAINOFF_GCLK_CTRL                   0x2555
#define VPP_POST2_MATRIX_COEF00_01              0x2560
#define VPP_POST2_MATRIX_COEF02_10              0x2561
#define VPP_POST2_MATRIX_COEF11_12              0x2562
#define VPP_POST2_MATRIX_COEF20_21              0x2563
#define VPP_POST2_MATRIX_COEF22                 0x2564
#define VPP_POST2_MATRIX_COEF13_14              0x2565
#define VPP_POST2_MATRIX_COEF23_24              0x2566
#define VPP_POST2_MATRIX_COEF15_25              0x2567
#define VPP_POST2_MATRIX_CLIP                   0x2568
#define VPP_POST2_MATRIX_OFFSET0_1              0x2569
#define VPP_POST2_MATRIX_OFFSET2                0x256a
#define VPP_POST2_MATRIX_PRE_OFFSET0_1          0x256b
#define VPP_POST2_MATRIX_PRE_OFFSET2            0x256c
#define VPP_POST2_MATRIX_EN_CTRL                0x256d
#define VPP_VADJ2_MISC                          0x2570
#define VPP_VADJ2_BLACK_VAL                     0x2571
#define VPP_VADJ2_Y                             0x2572
#define VPP_VADJ2_MA_MB                         0x2573
#define VPP_VADJ2_MC_MD                         0x2574
#define VPP_VADJ2_CURV_0                        0x2575
#define VPP_VADJ2_CURV_1                        0x2576
#define VPP_VADJ2_CURV_2                        0x2577
#define VPP_VADJ2_CURV_3                        0x2578
#define VPP_POST_RGB_CTRST                      0x2579
#define VPP_POST_RGB_BRGHT                      0x257a
#define VPP_POST_RGB_DLUT_0_3                   0x257b
#define VPP_POST_RGB_DLUT_4_7                   0x257c
#define VPP_POST_RGB_DLUT_8_11                  0x257d
#define VPP_POST_MATRIX_COEF00_01               0x2580
#define VPP_POST_MATRIX_COEF02_10               0x2581
#define VPP_POST_MATRIX_COEF11_12               0x2582
#define VPP_POST_MATRIX_COEF20_21               0x2583
#define VPP_POST_MATRIX_COEF22                  0x2584
#define VPP_POST_MATRIX_COEF13_14               0x2585
#define VPP_POST_MATRIX_COEF23_24               0x2586
#define VPP_POST_MATRIX_COEF15_25               0x2587
#define VPP_POST_MATRIX_CLIP                    0x2588
#define VPP_POST_MATRIX_OFFSET0_1               0x2589
#define VPP_POST_MATRIX_OFFSET2                 0x258a
#define VPP_POST_MATRIX_PRE_OFFSET0_1           0x258b
#define VPP_POST_MATRIX_PRE_OFFSET2             0x258c
#define VPP_POST_MATRIX_EN_CTRL                 0x258d
#define VPP_POST_MATRIX_SAT                     0x258e

/*ai color ce module regs*/
#define SA_CTRL                                 0x3f00
#define SA_CM                                   0x3f04
#define SA_ADJ                                  0x3f05
#define SA_PRT                                  0x3f06
#define SA_S_GAIN_0                              0x3f07
#define SA_S_GAIN_1                              0x3f08
#define SA_S_GAIN_2                              0x3f09
#define SA_S_GAIN_3                              0x3f0a
#define SA_S_GAIN_4                              0x3f0b
#define SA_S_GAIN_5                              0x3f0c
#define SA_S_GAIN_6                              0x3f0d
#define SA_S_GAIN_7                              0x3f0e
#define SA_S_GAIN_8                              0x3f0f
#define SA_S_GAIN_9                              0x3f10
#define SA_S_GAIN_10                             0x3f11
#define SA_S_GAIN_11                             0x3f12
#define SA_S_GAIN_12                             0x3f13
#define SA_S_GAIN_13                             0x3f14
#define SA_S_GAIN_14                             0x3f15
#define SA_S_GAIN_15                             0x3f16
#define SA_S_GAIN_16                             0x3f17
#define SA_S_GAIN_17                             0x3f18
#define SA_S_GAIN_18                             0x3f19
#define SA_S_GAIN_19                             0x3f1a
#define SA_S_GAIN_20                             0x3f1b
#define SA_S_GAIN_21                             0x3f1c
#define SA_S_GAIN_22                             0x3f1d
#define SA_S_GAIN_23                             0x3f1e
#define SA_S_GAIN_24                             0x3f1f
#define SA_S_GAIN_25                             0x3f20
#define SA_S_GAIN_26                             0x3f21
#define SA_S_GAIN_27                             0x3f22
#define SA_S_GAIN_28                             0x3f23
#define SA_S_GAIN_29                             0x3f24
#define SA_S_GAIN_30                             0x3f25
#define SA_S_GAIN_31                             0x3f26
#define SA_S_GAIN_32                             0x3f27
#define SA_S_GAIN_33                             0x3f28
#define SA_S_GAIN_34                             0x3f29
#define SA_S_GAIN_35                             0x3f2a
#define SA_S_GAIN_36                             0x3f2b
#define SA_S_GAIN_37                             0x3f2c
#define SA_S_GAIN_38                             0x3f2d
#define SA_S_GAIN_39                             0x3f2e
#define SA_S_GAIN_40                             0x3f2f
#define SA_S_GAIN_41                             0x3f30
#define SA_S_GAIN_42                             0x3f31
#define SA_S_GAIN_43                             0x3f32
#define SA_S_GAIN_44                             0x3f33
#define SA_S_GAIN_45                             0x3f34
#define SA_S_GAIN_46                             0x3f35
#define SA_S_GAIN_47                             0x3f36
#define SA_S_GAIN_48                             0x3f37
#define SA_S_GAIN_49                             0x3f38
#define SA_S_GAIN_50                             0x3f39
#define SA_S_GAIN_51                             0x3f3a
#define SA_S_GAIN_52                             0x3f3b
#define SA_S_GAIN_53                             0x3f3c
#define SA_S_GAIN_54                             0x3f3d
#define SA_S_GAIN_55                             0x3f3e
#define SA_S_GAIN_56                             0x3f3f
#define SA_S_GAIN_57                             0x3f40
#define SA_S_GAIN_58                             0x3f41
#define SA_S_GAIN_59                             0x3f42
#define SA_L_GAIN_0                              0x3f43
#define SA_L_GAIN_1                              0x3f44
#define SA_L_GAIN_2                              0x3f45
#define SA_L_GAIN_3                              0x3f46
#define SA_L_GAIN_4                              0x3f47
#define SA_L_GAIN_5                              0x3f48
#define SA_L_GAIN_6                              0x3f49
#define SA_L_GAIN_7                              0x3f4a
#define SA_L_GAIN_8                              0x3f4b
#define SA_L_GAIN_9                              0x3f4c
#define SA_L_GAIN_10                             0x3f4d
#define SA_L_GAIN_11                             0x3f4e
#define SA_L_GAIN_12                             0x3f4f
#define SA_L_GAIN_13                             0x3f50
#define SA_L_GAIN_14                             0x3f51
#define SA_L_GAIN_15                             0x3f52
#define SA_L_GAIN_16                             0x3f53
#define SA_L_GAIN_17                             0x3f54
#define SA_L_GAIN_18                             0x3f55
#define SA_L_GAIN_19                             0x3f56
#define SA_L_GAIN_20                             0x3f57
#define SA_L_GAIN_21                             0x3f58
#define SA_L_GAIN_22                             0x3f59
#define SA_L_GAIN_23                             0x3f5a
#define SA_L_GAIN_24                             0x3f5b
#define SA_L_GAIN_25                             0x3f5c
#define SA_L_GAIN_26                             0x3f5d
#define SA_L_GAIN_27                             0x3f5e
#define SA_L_GAIN_28                             0x3f5f
#define SA_L_GAIN_29                             0x3f60
#define SA_L_GAIN_30                             0x3f61
#define SA_L_GAIN_31                             0x3f62

#define VI_HIST_CTRL                              0x1a40
#define VI_HIST_H_START_END                       0x1a41
#define VI_HIST_V_START_END                       0x1a42
#define VI_HIST_MAX_MIN                           0x1a43
#define VI_HIST_SPL_VAL                           0x1a44
#define VI_HIST_SPL_PIX_CNT                       0x1a45
#define VI_HIST_CHROMA_SUM                        0x1a46
#define VI_DNLP_HIST00                            0x1a47
#define VI_DNLP_HIST01                            0x1a48
#define VI_DNLP_HIST02                            0x1a49
#define VI_DNLP_HIST03                            0x1a4a
#define VI_DNLP_HIST04                            0x1a4b
#define VI_DNLP_HIST05                            0x1a4c
#define VI_DNLP_HIST06                            0x1a4d
#define VI_DNLP_HIST07                            0x1a4e
#define VI_DNLP_HIST08                            0x1a4f
#define VI_DNLP_HIST09                            0x1a50
#define VI_DNLP_HIST10                            0x1a51
#define VI_DNLP_HIST11                            0x1a52
#define VI_DNLP_HIST12                            0x1a53
#define VI_DNLP_HIST13                            0x1a54
#define VI_DNLP_HIST14                            0x1a55
#define VI_DNLP_HIST15                            0x1a56
#define VI_DNLP_HIST16                            0x1a57
#define VI_DNLP_HIST17                            0x1a58
#define VI_DNLP_HIST18                            0x1a59
#define VI_DNLP_HIST19                            0x1a5a
#define VI_DNLP_HIST20                            0x1a5b
#define VI_DNLP_HIST21                            0x1a5c
#define VI_DNLP_HIST22                            0x1a5d
#define VI_DNLP_HIST23                            0x1a5e
#define VI_DNLP_HIST24                            0x1a5f
#define VI_DNLP_HIST25                            0x1a60
#define VI_DNLP_HIST26                            0x1a61
#define VI_DNLP_HIST27                            0x1a62
#define VI_DNLP_HIST28                            0x1a63
#define VI_DNLP_HIST29                            0x1a64
#define VI_DNLP_HIST30                            0x1a65
#define VI_DNLP_HIST31                            0x1a66
#define VI_DNLP_HIST32                            0x1a67

#define VI_HIST_PIC_SIZE                          0x1a68
#define VI_HIST_BLACK_WHITE_VALUE                 0x1a69
#define VI_HIST_GCLK_CTRL                         0x1a6a
#define VI_RO_HIST_LOW_IDX                        0x1a6b
#define VI_RO_HIST_LOW                            0x1a6c

#define VI_SLICE1_HIST_CTRL                       0x1a70

#define VPP_SRSHARP0_PK_NR_EN                     0x5027
#define VPP_SRSHARP1_PK_NR_EN                     0x5227

#define VPP_SRSHARP1_DNLP_EN                      0x5245
#define VPP_SRSHARP1_DNLP_00                      0x5290
#define VPP_SRSHARP1_LC_INPUT_MUX                 0x52b1
#define VPP_SRSHARP1_LC_TOP_CTRL                  0x52c0
#define VPP_SRSHARP1_LC_HV_NUM                    0x52c1
#define VPP_SRSHARP1_LC_SAT_LUT_0_1               0x52c2
#define VPP_SRSHARP1_LC_SAT_LUT_62                0x52e1
#define VPP_SRSHARP1_LC_CURVE_BLK_HIDX_0_1        0x52e2
#define VPP_SRSHARP1_LC_CURVE_BLK_VIDX_0_1        0x52e9
#define VPP_SRSHARP1_LC_YUV2RGB_MAT_0_1           0x52ee
#define VPP_SRSHARP1_LC_RGB2YUV_MAT_0_1           0x52f3
#define VPP_SRSHARP1_LC_YUV2RGB_OFST              0x52f8
#define VPP_SRSHARP1_LC_YUV2RGB_CLIP              0x52f9
#define VPP_SRSHARP1_LC_RGB2YUV_OFST              0x52fa
#define VPP_SRSHARP1_LC_RGB2YUV_CLIP              0x52fb
#define VPP_SRSHARP1_LC_MAP_RAM_CTRL              0x52fc
#define VPP_SRSHARP1_LC_MAP_RAM_ADDR              0x52fd
#define VPP_SRSHARP1_LC_MAP_RAM_DATA              0x52fe

#define VPP_LC1_CURVE_CTRL                        0x5a40
#define VPP_LC1_CURVE_HV_NUM                      0x5a41
#define VPP_LC1_CURVE_LMT_RAT                     0x5a42
#define VPP_LC1_CURVE_CONTRAST_LH                 0x5a43
#define VPP_LC1_CURVE_CONTRAST_LMT_LH             0x5a44
#define VPP_LC1_CURVE_CONTRAST_SCL_LH             0x5a45
#define VPP_LC1_CURVE_CONTRAST_BVN_LH             0x5a46
#define VPP_LC1_CURVE_MISC0                       0x5a47
#define VPP_LC1_CURVE_YPKBV_RAT                   0x5a48
#define VPP_LC1_CURVE_YPKBV_SLP_LMT               0x5a49
#define VPP_LC1_CURVE_YMINVAL_LMT_0_1             0x5a4a
#define VPP_LC1_CURVE_YMAXVAL_LMT_0_1             0x5a50
#define VPP_LC1_CURVE_HISTVLD_THRD                0x5a56
#define VPP_LC1_CURVE_BB_MUTE_THRD                0x5a57
#define VPP_LC1_CURVE_INT_STATUS                  0x5a58
#define VPP_LC1_CURVE_YMINVAL_LMT_12_13           0x5a60
#define VPP_LC1_CURVE_YMINVAL_LMT_14_15           0x5a61
#define VPP_LC1_CURVE_YMAXVAL_LMT_12_13           0x5a62
#define VPP_LC1_CURVE_YMAXVAL_LMT_14_15           0x5a63
#define VPP_LC1_CURVE_YPKBV_LMT_0_1               0x5a64
#define VPP_LC1_CURVE_RAM_CTRL                    0x5a70
#define VPP_LC1_CURVE_RAM_ADDR                    0x5a71
#define VPP_LC1_CURVE_RAM_DATA                    0x5a72

#define VPP_LC_STTS_CTRL                          0x282e
#define VPP_LC_STTS_GCLK_CTRL0                    0x5ad6
#define VPP_LC_STTS_CTRL0                         0x5ad7
#define VPP_LC_STTS_CTRL1                         0x5ad8
#define VPP_LC_STTS1_WIDTHM1_HEIGHTM1             0x5ad9
#define VPP_LC_STTS2_WIDTHM1_HEIGHTM1             0x5ada
#define VPP_LC_STTS_MATRIX_COEF00_01              0x5adb
#define VPP_LC_STTS_MATRIX_COEF22                 0x5adf
#define VPP_LC_STTS_MATRIX_OFFSET0_1              0x5ae0
#define VPP_LC_STTS_MATRIX_OFFSET2                0x5ae1
#define VPP_LC_STTS_MATRIX_PRE_OFFSET0_1          0x5ae2
#define VPP_LC_STTS_MATRIX_PRE_OFFSET2            0x5ae3
#define VPP_LC_STTS_MATRIX_HL_COLOR               0x5ae4
#define VPP_LC_STTS_MATRIX_PROBE_POS1             0x5ae5
#define VPP_LC_STTS_MATRIX_PROBE_POS2             0x5ae6
#define VPP_LC_STTS_MATRIX_PROBE_COLOR1           0x5ae7
#define VPP_LC_STTS_MATRIX_PROBE_COLOR2           0x5ae8
#define VPP_LC_STTS_HIST_REGION_IDX               0x5ae9
#define VPP_LC_STTS_HIST_SET_REGION               0x5aea
#define VPP_LC_STTS_WHITE_INFO1                   0x5aeb
#define VPP_LC_STTS_BLACK_INFO1                   0x5aec
#define VPP_LC_STTS_WHITE_INFO2                   0x5aed
#define VPP_LC_STTS_BLACK_INFO2                   0x5aee
#define VPP_LC_STTS_DMA_ERROR_RO                  0x5aef

#define VPP_LUT3D_CTRL                            0x2540
#define VPP_LUT3D_CBUS2RAM_CTRL                   0x2541
#define VPP_LUT3D_RAM_ADDR                        0x2542
#define VPP_LUT3D_RAM_DATA                        0x2543

/* #define VDIN_HIST_MAX_MIN                        */
#define VI_HIST_MAX_BIT                    8
#define VI_HIST_MAX_WID                    8
#define VI_HIST_MIN_BIT                    0
#define VI_HIST_MIN_WID                    8

/* #define VDIN_DNLP_HIST00                         */
#define VI_HIST_ON_BIN_01_BIT              16
#define VI_HIST_ON_BIN_01_WID              16
#define VI_HIST_ON_BIN_00_BIT              0
#define VI_HIST_ON_BIN_00_WID              16

/* #define VDIN_DNLP_HIST01                         */
#define VI_HIST_ON_BIN_03_BIT              16
#define VI_HIST_ON_BIN_03_WID              16
#define VI_HIST_ON_BIN_02_BIT              0
#define VI_HIST_ON_BIN_02_WID              16

/* #defineVDIN_DNLP_HIST02                         */
#define VI_HIST_ON_BIN_05_BIT              16
#define VI_HIST_ON_BIN_05_WID              16
#define VI_HIST_ON_BIN_04_BIT              0
#define VI_HIST_ON_BIN_04_WID              16

/* #define VDIN_DNLP_HIST03                         */
#define VI_HIST_ON_BIN_07_BIT              16
#define VI_HIST_ON_BIN_07_WID              16
#define VI_HIST_ON_BIN_06_BIT              0
#define VI_HIST_ON_BIN_06_WID              16

/* #defineVDIN_DNLP_HIST04                         */
#define VI_HIST_ON_BIN_09_BIT              16
#define VI_HIST_ON_BIN_09_WID              16
#define VI_HIST_ON_BIN_08_BIT              0
#define VI_HIST_ON_BIN_08_WID              16

/* #define VDIN_DNLP_HIST05                         */
#define VI_HIST_ON_BIN_11_BIT              16
#define VI_HIST_ON_BIN_11_WID              16
#define VI_HIST_ON_BIN_10_BIT              0
#define VI_HIST_ON_BIN_10_WID              16

/* #defineVDIN_DNLP_HIST06                         */
#define VI_HIST_ON_BIN_13_BIT              16
#define VI_HIST_ON_BIN_13_WID              16
#define VI_HIST_ON_BIN_12_BIT              0
#define VI_HIST_ON_BIN_12_WID              16

/* #define VDIN_DNLP_HIST07                         */
#define VI_HIST_ON_BIN_15_BIT              16
#define VI_HIST_ON_BIN_15_WID              16
#define VI_HIST_ON_BIN_14_BIT              0
#define VI_HIST_ON_BIN_14_WID              16

/* #define VDIN_DNLP_HIST08                         */
#define VI_HIST_ON_BIN_17_BIT              16
#define VI_HIST_ON_BIN_17_WID              16
#define VI_HIST_ON_BIN_16_BIT              0
#define VI_HIST_ON_BIN_16_WID              16

/* #define VDIN_DNLP_HIST09                         */
#define VI_HIST_ON_BIN_19_BIT              16
#define VI_HIST_ON_BIN_19_WID              16
#define VI_HIST_ON_BIN_18_BIT              0
#define VI_HIST_ON_BIN_18_WID              16

/* #defineVDIN_DNLP_HIST10                         */
#define VI_HIST_ON_BIN_21_BIT              16
#define VI_HIST_ON_BIN_21_WID              16
#define VI_HIST_ON_BIN_20_BIT              0
#define VI_HIST_ON_BIN_20_WID              16

/* #define VDIN_DNLP_HIST11                         */
#define VI_HIST_ON_BIN_23_BIT              16
#define VI_HIST_ON_BIN_23_WID              16
#define VI_HIST_ON_BIN_22_BIT              0
#define VI_HIST_ON_BIN_22_WID              16

/* #defineVDIN_DNLP_HIST12                         */
#define VI_HIST_ON_BIN_25_BIT              16
#define VI_HIST_ON_BIN_25_WID              16
#define VI_HIST_ON_BIN_24_BIT              0
#define VI_HIST_ON_BIN_24_WID              16

/* #define VDIN_DNLP_HIST13                         */
#define VI_HIST_ON_BIN_27_BIT              16
#define VI_HIST_ON_BIN_27_WID              16
#define VI_HIST_ON_BIN_26_BIT              0
#define VI_HIST_ON_BIN_26_WID              16

/* #defineVDIN_DNLP_HIST14                         */
#define VI_HIST_ON_BIN_29_BIT              16
#define VI_HIST_ON_BIN_29_WID              16
#define VI_HIST_ON_BIN_28_BIT              0
#define VI_HIST_ON_BIN_28_WID              16

/* #define VDIN_DNLP_HIST15                         */
#define VI_HIST_ON_BIN_31_BIT              16
#define VI_HIST_ON_BIN_31_WID              16
#define VI_HIST_ON_BIN_30_BIT              0
#define VI_HIST_ON_BIN_30_WID              16

/* #define VDIN_DNLP_HIST16                         */
#define VI_HIST_ON_BIN_33_BIT              16
#define VI_HIST_ON_BIN_33_WID              16
#define VI_HIST_ON_BIN_32_BIT              0
#define VI_HIST_ON_BIN_32_WID              16

/* #defineVDIN_DNLP_HIST17                         */
#define VI_HIST_ON_BIN_35_BIT              16
#define VI_HIST_ON_BIN_35_WID              16
#define VI_HIST_ON_BIN_34_BIT              0
#define VI_HIST_ON_BIN_34_WID              16

/* #define VDIN_DNLP_HIST18                         */
#define VI_HIST_ON_BIN_37_BIT              16
#define VI_HIST_ON_BIN_37_WID              16
#define VI_HIST_ON_BIN_36_BIT              0
#define VI_HIST_ON_BIN_36_WID              16

/* #define VDIN_DNLP_HIST19                         */
#define VI_HIST_ON_BIN_39_BIT              16
#define VI_HIST_ON_BIN_39_WID              16
#define VI_HIST_ON_BIN_38_BIT              0
#define VI_HIST_ON_BIN_38_WID              16

/* #define VDIN_DNLP_HIST20                         */
#define VI_HIST_ON_BIN_41_BIT              16
#define VI_HIST_ON_BIN_41_WID              16
#define VI_HIST_ON_BIN_40_BIT              0
#define VI_HIST_ON_BIN_40_WID              16

/* #define VDIN_DNLP_HIST21                         */
#define VI_HIST_ON_BIN_43_BIT              16
#define VI_HIST_ON_BIN_43_WID              16
#define VI_HIST_ON_BIN_42_BIT              0
#define VI_HIST_ON_BIN_42_WID              16

/* #defineVDIN_DNLP_HIST22                         */
#define VI_HIST_ON_BIN_45_BIT              16
#define VI_HIST_ON_BIN_45_WID              16
#define VI_HIST_ON_BIN_44_BIT              0
#define VI_HIST_ON_BIN_44_WID              16

/* #define VDIN_DNLP_HIST23                         */
#define VI_HIST_ON_BIN_47_BIT              16
#define VI_HIST_ON_BIN_47_WID              16
#define VI_HIST_ON_BIN_46_BIT              0
#define VI_HIST_ON_BIN_46_WID              16

/* #defineVDIN_DNLP_HIST24                         */
#define VI_HIST_ON_BIN_49_BIT              16
#define VI_HIST_ON_BIN_49_WID              16
#define VI_HIST_ON_BIN_48_BIT              0
#define VI_HIST_ON_BIN_48_WID              16

/* #defineVDIN_DNLP_HIST25                         */
#define VI_HIST_ON_BIN_51_BIT              16
#define VI_HIST_ON_BIN_51_WID              16
#define VI_HIST_ON_BIN_50_BIT              0
#define VI_HIST_ON_BIN_50_WID              16

/* #define VDIN_DNLP_HIST26                         */
#define VI_HIST_ON_BIN_53_BIT              16
#define VI_HIST_ON_BIN_53_WID              16
#define VI_HIST_ON_BIN_52_BIT              0
#define VI_HIST_ON_BIN_52_WID              16

/* #define VDIN_DNLP_HIST27                         */
#define VI_HIST_ON_BIN_55_BIT              16
#define VI_HIST_ON_BIN_55_WID              16
#define VI_HIST_ON_BIN_54_BIT              0
#define VI_HIST_ON_BIN_54_WID              16

/* #define VDIN_DNLP_HIST28                         */
#define VI_HIST_ON_BIN_57_BIT              16
#define VI_HIST_ON_BIN_57_WID              16
#define VI_HIST_ON_BIN_56_BIT              0
#define VI_HIST_ON_BIN_56_WID              16

/* #define VDIN_DNLP_HIST29                         */
#define VI_HIST_ON_BIN_59_BIT              16
#define VI_HIST_ON_BIN_59_WID              16
#define VI_HIST_ON_BIN_58_BIT              0
#define VI_HIST_ON_BIN_58_WID              16

/* #defineVDIN_DNLP_HIST30                         */
#define VI_HIST_ON_BIN_61_BIT              16
#define VI_HIST_ON_BIN_61_WID              16
#define VI_HIST_ON_BIN_60_BIT              0
#define VI_HIST_ON_BIN_60_WID              16

/* #define VDIN_DNLP_HIST31                         */
#define VI_HIST_ON_BIN_63_BIT              16
#define VI_HIST_ON_BIN_63_WID              16
#define VI_HIST_ON_BIN_62_BIT              0
#define VI_HIST_ON_BIN_62_WID              16

/* #define VDIN_HIST_PIC_SIZE                    */
#define VI_HIST_PIC_HEIGHT_BIT                 16
#define VI_HIST_PIC_HEIGHT_WID                 13
#define VI_HIST_PIC_WIDTH_BIT                   0
#define VI_HIST_PIC_WIDTH_WID                   13

#endif

