/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_AMLOGIC_MESON_S5_RESET_H
#define _DT_BINDINGS_AMLOGIC_MESON_S5_RESET_H

/* RESET0 */
/*					0	*/
#define RESET_U3X1_M31_UTMI		1
#define RESET_U3X0_M31_UTMI		2
#define RESET_U2DRDX0			3
/*					4	*/
#define RESET_U3DRDX1			5
#define RESET_U3DRDX0			6
/*					7	*/
#define RESET_U2PHY20			8
#define RESET_U3X1_PCIE_PHY		9
#define RESET_U3X0_PCIE_PHY		10
#define RESET_APB_DECODE_DMC		11
/*					12-15	*/
#define RESET_BRG_SYS_APB_DEC		16
#define RESET_BRG_VCBUS_DEC		17
#define RESET_HDMITX_CAPB3		18
#define RESET_HDMITX			19
/*					20	*/
#define RESET_GE2D			21
/*					22	*/
#define RESET_HTXDPHY			23
#define RESET_HDMI20_AES		24
/*					25-28	*/
#define RESET_DSC_ENC_CAPB3		29
#define RESET_DSC_ENC			30
/*					31	*/

/* RESET1 */
#define RESET_AUDIO			32
#define RESET_DOS			33
#define RESET_DOS_CAPB3			34
#define RESET_DDR_APB			35
#define RESET_DDR			36
/*					37	*/
#define RESET_U3X1_PCIE_APB		38
#define RESET_U3X0_PCIE_APB		39
#define RESET_I_DEBUGB			40
#define RESET_I_DEBUGA			41
/*					42-43	*/
#define RESET_PCIE_GEN2_L1		44
#define RESET_PCIE_B_APB		45
#define RESET_PCIE_A_APB		46
#define RESET_ADLA			47
#define RESET_ETH			48
/*					49	*/
#define RESET_PCIE_GEN2_L0		50
/*					51	*/
#define RESET_U3COMBX1			52
#define RESET_U3COMBX0			53
#define RESET_U2COMBX0			54
#define RESET_NNA_NIC_4T		55
/*					56-58	*/
#define RESET_NNA_NIC_1T		59
#define RESET_NNA_NIC_MAIN		60
#define RESET_NNA_NIC_GPV		61
#define RESET_NNA_NIC_ALL		62
#define RESET_ACODEC			63

/* RESET2 */
#define RESET_IR_CTRL			64
#define RESET_TS_A55			65
/*					66-67	*/
#define RESET_SPICC_2			68
/*					69-71	*/
#define RESET_SMART_CARD		72
#define RESET_SPICC_0			73
#define RESET_SPICC_1			74
/*					75-79	*/
#define RESET_MSR_CLK			80
#define RESET_SPIFC			81
#define RESET_SAR_ADC			82
/*					83-88	*/
#define RESET_CEC			89
#define RESET_AFIFO			90
#define RESET_WATCHDOG			91
#define RESET_VID_PLL0_DIV		92
/*					93	*/
#define RESET_TMDS20_DIV		94
/*					95	*/

/* RESET3 */
/*					96-99	*/
#define RESET_PCIE_B_7			100
#define RESET_PCIE_B_6			101
#define RESET_PCIE_B_5			102
#define RESET_PCIE_B_4			103
#define RESET_PCIE_B_3			104
#define RESET_PCIE_B_2			105
#define RESET_PCIE_B_1			106
#define RESET_PCIE_B_0			107
#define RESET_PCIE_A_7			108
#define RESET_PCIE_A_6			109
#define RESET_PCIE_A_5			110
#define RESET_PCIE_A_4			111
#define RESET_PCIE_A_3			112
#define RESET_PCIE_A_2			113
#define RESET_PCIE_A_1			114
#define RESET_PCIE_A_0			115
#define RESET_VDI6			116
#define RESET_VID_LOCK			117
#define RESET_VENC2			118
#define RESET_VENC1			119
#define RESET_VENC0			120
#define RESET_VDAC			121
#define RESET_RDMA			122
#define RESET_VIU			123
#define RESET_VENC			124
/*					125-126	*/
#define RESET_A55_ACE			127

/* RESET4 */
#define RESET_PWM_AB			128
#define RESET_PWM_CD			129
#define RESET_PWM_EF			130
#define RESET_PWM_GH			131
#define RESET_PWM_IJ			132
#define RESET_VID_CMPR			133
#define RESET_VC9000E_ARESET		134
#define RESET_VC9000E_CORE		135
/*					136	*/
#define RESET_VC9000E_APB		137
#define RESET_UART_A			138
#define RESET_UART_B			139
#define RESET_UART_C			140
#define RESET_UART_D			141
#define RESET_UART_E			142
#define RESET_UART_F			143
#define RESET_I2C_S_A			144
#define RESET_I2C_M_A			145
#define RESET_I2C_M_B			146
#define RESET_I2C_M_C			147
#define RESET_I2C_M_D			148
#define RESET_I2C_M_E			149
#define RESET_I2C_M_F			150
/*					151	*/
#define RESET_UART_G			152
#define RESET_SD_EMMC_A			153
#define RESET_SD_EMMC_B			154
#define RESET_SD_EMMC_C			155
#define RESET_TS_GPU			156
#define RESET_TS_NNA			157
#define RESET_TS_VPU			158
#define RESET_TS_DOS			159

/* RESET5 */
/*					160-177	*/
#define RESET_BRG_NICSYS_NPU		178
#define RESET_BRG_NICSYS_EMMCC		179
#define RESET_BRG_NICSYS_EMMCB		180
#define RESET_BRG_NICSYS_EMMCA		181
/*					182	*/
#define RESET_BRG_NICSYS_PCIE		183
#define RESET_BRG_NICSYS_SYSCPU		184
#define RESET_BRG_NICSYS_SYS		185
/*					186-188	*/
#define RESET_BRG_NICSYS_VAPB		189
#define RESET_BRG_NICSYS_MAIN		190
#define RESET_BRG_NICSYS_ALL		191

/* RESET6 */
#define RESET_BRG_AHB_PIPE_NICDOS	192
#define RESET_BRG_AHB_PIPE_NICNNA	193
#define RESET_BRG_AHB_PIPE_NICVPU	194
#define RESET_BRG_AHB_PIPE_NICVGE	195
/*					196	*/
#define RESET_BRG_AHB_PIPE_NICSYS	197
#define RESET_BRG_VDEC_DMC_PIPEL	198
#define RESET_BRG_HEVCF_DMC_PIPEL	199
/*					200	*/
#define RESET_BRG_AXI_PIPE_NNATODDR	201
/*					202	*/
#define RESET_BRG_AXI_PIPE_NNATOSYS	203
#define RESET_BRG_AXI_PIPE_NICVPU	204
#define RESET_BRG_AXI_PIPE_NICDOS	205
#define RESET_BRG_AXI_PIPE_NICVGE	206
#define RESET_BRG_AXI_PIPE_EMMCC	207
#define RESET_BRG_APB_PIPE_NNA		208
#define RESET_BRG_APB_PIPE_FDLETOP	209
#define RESET_BRG_APB_PIPE_NOCDMC	210
#define RESET_BRG_APB_PIPE_DDR0		211
#define RESET_BRG_APB_PIPE_DDR1		212
#define RESET_BRG_APB_PIPE_GE2D		213
#define RESET_BRG_APB_PIPE_VPU		214
/*					215-217	*/
#define RESET_BRG_AMPIPE_NAND		218
#define RESET_BRG_AMPIPE_ETH		219
/*					220	*/
#define RESET_BRG_AM2AXI0		221
/*					222-223	*/

/* RESET7 */
/*					224-234	*/
#define RESET_BRG_NICVGE_SYS		235
#define RESET_BRG_NICVGE_VC9000E	236
#define RESET_BRG_NICVGE_VID_CMPR	237
#define RESET_BRG_NICVGE_GE2D		238
/*					239-241	*/
#define RESET_BRG_NICVGE_MAIN		242
#define RESET_BRG_NICVGE_ALL		243
/*					244	*/
#define RESET_BRG_NICDOS_SYS		245
#define RESET_BRG_NICDOS_VDEC		246
#define RESET_BRG_NICDOS_HEVC		247
#define RESET_BRG_NICDOS_HCODEC		248
#define RESET_BRG_NICDOS_MAIN		249
#define RESET_BRG_NICDOS_ALL		250
/*					251-252	*/
#define RESET_BRG_NICVPU_SYS		253
#define RESET_BRG_NICVPU_MAIN		254
#define RESET_BRG_NICVPU_ALL		255

#endif
