/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_AMLOGIC_MESON_T3X_RESET_H
#define _DT_BINDINGS_AMLOGIC_MESON_T3X_RESET_H

/* RESET0 */
/*					0	*/
#define RESET_U3X1_M31_UTMI		1
#define RESET_U3X0_M31_UTMI		2
#define RESET_U2DRDX0			3
#define RESET_U2DRDX1			4
#define RESET_U3DRDX1			5
#define RESET_U3DRDX0			6
#define RESET_U2PHY21			7
#define RESET_U2PHY20			8
#define RESET_U3X1_PCIE_PHY		9
#define RESET_U3X0_PCIE_PHY		10
#define RESET_APB_DECODE_DMC		11
#define RESET_HDMIRX			12
#define RESET_HDMIRX_APB		13
/*					14-15	*/
#define RESET_BRG_SYS_APB_DEC		16
#define RESET_BRG_VCBUS_DEC		17
/*					18-20	*/
#define RESET_GE2D			21
/*					22-23	*/
#define RESET_HDMI20_AES		24
#define RESET_I2C_MON			25
#define RESET_FRC_RDMA			26
#define RESET_FRC_APB			27
#define RESET_FRC			28
#define RESET_DSC_DEC_CAPB3		29
#define RESET_DSC_DEC			30
/*					31	*/

/* RESET1 */
#define RESET_AUDIO			32
#define RESET_DOS			33
#define RESET_DOS_CAPB3			34
#define RESET_DDR_APB			35
#define RESET_DDR			36
#define RESET_COMBO_DPHY_CHAN1		37
#define RESET_U3X1_PCIE_APB		38
#define RESET_U3X0_PCIE_APB		39
#define RESET_I_DEBUGB			40
#define RESET_I_DEBUGA			41
#define RESET_U2COMBX1			42
#define RESET_I_DSPA			43
#define RESET_PCIE_GEN2_L1		44
#define RESET_PCIE_B_APB		45
#define RESET_PCIE_A_APB		46
#define RESET_ADLA			47
#define RESET_ETH			48
#define RESET_DEMOD			49
#define RESET_PCIE_GEN2_L0		50
#define RESET_COMBO_DPHY_CHAN0		51
#define RESET_U3COMBX1			52
#define RESET_U3COMBX0			53
#define RESET_U2COMBX0			54
#define RESET_NNA_NIC_4T		55
/*					56-58	*/
#define RESET_NNA_NIC_1T		59
#define RESET_NNA_NIC_MAIN		60
#define RESET_NNA_NIC_GPV		61
#define RESET_NNA_NIC_ALL		62
#define RESET_ACODEC			63

/* RESET2 */
#define RESET_IR_CTRL			64
#define RESET_TS_A55			65
#define RESET_SPICC_3			66
#define RESET_TCON			67
#define RESET_SPICC_2			68
#define RESET_TVFE			69
#define RESET_ATV_DMD			70
#define RESET_ADEC			71
#define RESET_SMART_CARD		72
#define RESET_SPICC_0			73
#define RESET_SPICC_1			74
/*					75	*/
#define RESET_LED_CTRL			76
#define RESET_BRG_APB_PIPE_U2COMB0	77
#define RESET_BRG_APB_PIPE_U3COMB1	78
#define RESET_BRG_APB_PIPE_U3COMB0	79
#define RESET_MSR_CLK			80
#define RESET_SPIFC			81
#define RESET_SAR_ADC			82
#define RESET_BRG_APB_PIPE_CMPR		83
#define RESET_BRG_APB_PIPE_ACODEC	84
#define RESET_BRG_APB_PIPE_NAND		85
/*					86	*/
#define RESET_BRG_APB_PIPE_U3DRDX1	87
#define RESET_BRG_APB_PIPE_U3DRDX0	88
#define RESET_CEC			89
#define RESET_AFIFO			90
#define RESET_WATCHDOG			91
#define RESET_COMBO_DPHY_PCLK		92
#define RESET_BRG_APB_PIPE_GPIOB	93
/*					94	*/
#define RESET_BRG_APB_PIPE_U2COMB1	95

/* RESET3 */
/*					96	*/
#define RESET_SPICC_5			97
#define RESET_SPICC_4			98
#define RESET_CIPLUS			99
#define RESET_PCIE_B_0			100
#define RESET_PCIE_B_1			101
#define RESET_PCIE_B_2			102
#define RESET_PCIE_B_3			103
#define RESET_PCIE_B_4			104
#define RESET_PCIE_B_5			105
#define RESET_PCIE_B_6			106
#define RESET_PCIE_B_7			107
#define RESET_PCIE_A_0			108
#define RESET_PCIE_A_1			109
#define RESET_PCIE_A_2			110
#define RESET_PCIE_A_3			111
#define RESET_PCIE_A_4			112
#define RESET_PCIE_A_5			113
#define RESET_PCIE_A_6			114
#define RESET_PCIE_A_7			115
#define RESET_VDI6			116
#define RESET_VID_LOCK			117
#define RESET_VENC2			118
#define RESET_VENC1			119
#define RESET_VENC0			120
#define RESET_VDAC			121
#define RESET_RDMA			122
#define RESET_VIU			123
#define RESET_VENC			124
#define RESET_VCBUS			125
/*					126	*/
#define RESET_A55_ACE			127

/* RESET4 */
#define RESET_PWM_AB			128
#define RESET_PWM_CD			129
#define RESET_PWM_EF			130
#define RESET_PWM_GH			131
#define RESET_PWM_IJ			132
#define RESET_VID_CMPR			133
/*					134-137	*/
#define RESET_UART_A			138
#define RESET_UART_B			139
#define RESET_UART_C			140
#define RESET_UART_D			141
/*					142-143	*/
#define RESET_I2C_S_A			144
#define RESET_I2C_M_A			145
#define RESET_I2C_M_B			146
#define RESET_I2C_M_C			147
#define RESET_I2C_M_D			148
#define RESET_I2C_M_E			149
/*					150-152	*/
#define RESET_SD_EMMC_A			153
#define RESET_SD_EMMC_B			154
#define RESET_SD_EMMC_C			155
#define RESET_TS_GPU			156
#define RESET_TS_NNA			157
#define RESET_TS_VPU			158
#define RESET_TS_DOS			159

/* RESET5 */
/*					160-167	*/
#define RESET_BRG_AXI_PIPE_PCIE_CTRL0	168
/*					169	*/
#define RESET_BRG_AXI_PIPE_PCIE_0	170
#define RESET_BRG_AXI_PIPE_USB3B	171
#define RESET_BRG_AXI_PIPE_USB3A	172
/*					173	*/
#define RESET_BRG_AXI_PIPE_CAPU		174
/*					175-178	*/
#define RESET_BRG_NICSYS_NPU		179
#define RESET_BRG_NICSYS_EMMCC		180
#define RESET_BRG_NICSYS_EMMCB		181
#define RESET_BRG_NICSYS_EMMCA		182
#define RESET_BRG_NICSYS_PCIE		183
#define RESET_BRG_NICSYS_SYSCPU		184
#define RESET_BRG_NICSYS_SYS		185
/*					186-187	*/
#define RESET_BRG_NICSYS_DSPA		188
#define RESET_BRG_NICSYS_VAPB		189
#define RESET_BRG_NICSYS_MAIN		190
#define RESET_BRG_NICSYS_ALL		191

/* RESET6 */
#define RESET_BRG_AHB_PIPE_NICDOS	192
#define RESET_BRG_AHB_PIPE_NICNNA	193
#define RESET_BRG_AHB_PIPE_NICVPU	194
#define RESET_BRG_AHB_PIPE_NICVGE	195
/*					196	*/
#define RESET_BRG_AHB_PIPE_NICSYS	197
#define RESET_BRG_VDEC_DMC_PIPEL	198
#define RESET_BRG_HEVCF_DMC_PIPEL	199
#define RESET_BRG_AXI_PIPE_VID_CMPR	200
#define RESET_BRG_AXI_PIPE_NNATODDR	201
#define RESET_BRG_AXI_PIPE_GPU		202
#define RESET_BRG_AXI_PIPE_NNATOSYS	203
#define RESET_BRG_AXI_PIPE_NICVPU	204
#define RESET_BRG_AXI_PIPE_NICDOS	205
#define RESET_BRG_AXI_PIPE_NICVGE	206
#define RESET_BRG_AXI_PIPE_EMMCC	207
#define RESET_BRG_APB_PIPE_NNA		208
#define RESET_BRG_APB_PIPE_FDLETOP	209
#define RESET_BRG_APB_PIPE_NOCDMC	210
#define RESET_BRG_APB_PIPE_DDR0		211
#define RESET_BRG_APB_PIPE_DDR1		212
#define RESET_BRG_APB_PIPE_GE2D		213
#define RESET_BRG_APB_PIPE_VPU		214
#define RESET_BRG_CAPU_TO_U2DRDX0_APB_PIPEL	215
#define RESET_BRG_CAPU_TO_U2DRDX1_APB_PIPEL	216
#define RESET_BRG_AXI_PIPE_NICFRC	217
#define RESET_BRG_AMPIPE_NAND		218
#define RESET_BRG_AMPIPE_ETH		219
/*					220	*/
#define RESET_BRG_AM2AXI0		221
#define RESET_BRG_AM2AXI1		222
#define RESET_BRG_APB_PIPE_FRC		223

/* RESET7 */
#define RESET_BRG_NICFRC_SYS		224
#define RESET_BRG_NICFRC_MAIN		225
#define RESET_BRG_NICFRC_ALL		226
/*					227-234	*/
#define RESET_BRG_NICVGE_SYS		235
/*					236	*/
#define RESET_BRG_NICVGE_VID_CMPR	237
#define RESET_BRG_NICVGE_GE2D		238
/*					239-241	*/
#define RESET_BRG_NICVGE_MAIN		242
#define RESET_BRG_NICVGE_ALL		243
/*					244	*/
#define RESET_BRG_NICDOS_SYS		245
#define RESET_BRG_NICDOS_VDEC		246
#define RESET_BRG_NICDOS_HEVC		247
#define RESET_BRG_NICDOS_HCODEC		248
#define RESET_BRG_NICDOS_MAIN		249
#define RESET_BRG_NICDOS_ALL		250
/*					251-252	*/
#define RESET_BRG_NICVPU_SYS		253
#define RESET_BRG_NICVPU_MAIN		254
#define RESET_BRG_NICVPU_ALL		255

#endif
