/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK

#define CLKID_AO_AHB		0
#define CLKID_AO_IR_IN		1
#define CLKID_AO_I2C_M0		2
#define CLKID_AO_I2C_S0		3
#define CLKID_AO_UART		4
#define CLKID_AO_PROD_I2C	5
#define CLKID_AO_UART2		6
#define CLKID_AO_IR_OUT		7
#define CLKID_AO_SAR_ADC	8
#define CLKID_AO_MAILBOX	9
#define CLKID_AO_M3		10
#define CLKID_AO_AHB_SRAM	11
#define CLKID_AO_RTI		12
#define CLKID_AO_M4_FCLK	13
#define CLKID_AO_M4_HCLK	14
#define CLKID_AO_CLK81		15
#define CLKID_AO_SAR_ADC_SEL	16
#define CLKID_AO_SAR_ADC_DIV	17
#define CLKID_AO_SAR_ADC_CLK	18
#define CLKID_AO_CTS_OSCIN	19
#define CLKID_AO_32K_PRE	20
#define CLKID_AO_32K_DIV	21
#define CLKID_AO_32K_SEL	22
#define CLKID_AO_32K		23
#define CLKID_AO_CEC_PRE	24
#define CLKID_AO_CEC_DIV	25
#define CLKID_AO_CEC_SEL	26
#define CLKID_AO_CEC		27
#define CLKID_AO_CTS_RTC_OSCIN	28

#define NR_CLKS	29

#endif
