diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 71ad774df..f69a98b11 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -59,3 +59,4 @@ dtb-y += t5w_t962d4_at301_1.5g.dtb dtb-y += t5w_t962d4_at301_R.dtb dtb-y += t5w_t962d4_at301_1g_R.dtb dtb-y += t5w_t962d4_at301_1.5g_R.dtb +dtb-y += t3x_pxp.dtb diff --git a/arch/arm64/boot/dts/amlogic/mesont3x.dtsi b/arch/arm64/boot/dts/amlogic/mesont3x.dtsi new file mode 100644 index 000000000..56dcac668 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/mesont3x.dtsi @@ -0,0 +1,3997 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "meson-ir-map.dtsi" +#include "meson-valhall.dtsi" +#include + +/ { + cpus:cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0:cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + core4 { + cpu = <&CPU4>; + }; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55","arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>; + #cooling-cells = <2>; + //clocks = <&clkc CLKID_CPU_CLK>, + // <&clkc CLKID_CPU_DYN_CLK>, + // <&clkc CLKID_SYS_PLL>, + // <&clkc CLKID_DSU_CLK>, + // <&clkc CLKID_DSU_DYN_CLK>, + // <&clkc CLKID_GP1_PLL>; + //clock-names = "core_clk", + // "low_freq_clk_parent", + // "high_freq_clk_parent", + // "dsu_clk", + // "dsu_pre_parent", + // "dsu_pre_parent2"; + operating-points-v2 = <&a55_opp_table0>; + voltage-tolerance = <0>; + clock-latency = <50000>; + capacity-dmips-mhz = <512>; + dynamic-power-coefficient = <1024>; + cpu-supply = <&vddcpua>; + cpu_supply_external_used; + dsu-opp-table = <1200000 879000 1500000 939000>; + dsu_clock_shared; + dsu-low-rate = <1000000>; + dvfs_sibling_core_num = <4>; + dvfs_sibling_cores = <0 1 2 3>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55","arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>; + #cooling-cells = <2>; + //clocks = <&clkc CLKID_CPU_CLK>, + // <&clkc CLKID_CPU_DYN_CLK>, + // <&clkc CLKID_SYS_PLL>, + // <&clkc CLKID_DSU_CLK>, + // <&clkc CLKID_DSU_DYN_CLK>, + // <&clkc CLKID_GP1_PLL>; + //clock-names = "core_clk", + // "low_freq_clk_parent", + // "high_freq_clk_parent", + // "dsu_clk", + // "dsu_pre_parent", + // "dsu_pre_parent2"; + operating-points-v2 = <&a55_opp_table0>; + voltage-tolerance = <0>; + clock-latency = <50000>; + capacity-dmips-mhz = <512>; + dynamic-power-coefficient = <1024>; + cpu-supply = <&vddcpua>; + cpu_supply_external_used; + dsu-opp-table = <1200000 879000 1500000 939000>; + dsu_clock_shared; + dsu-low-rate = <1000000>; + dvfs_sibling_core_num = <4>; + dvfs_sibling_cores = <0 1 2 3>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55","arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>; + #cooling-cells = <2>; + //clocks = <&clkc CLKID_CPU_CLK>, + // <&clkc CLKID_CPU_DYN_CLK>, + // <&clkc CLKID_SYS_PLL>, + // <&clkc CLKID_DSU_CLK>, + // <&clkc CLKID_DSU_DYN_CLK>, + // <&clkc CLKID_GP1_PLL>; + //clock-names = "core_clk", + // "low_freq_clk_parent", + // "high_freq_clk_parent", + // "dsu_clk", + // "dsu_pre_parent", + // "dsu_pre_parent2"; + operating-points-v2 = <&a55_opp_table0>; + voltage-tolerance = <0>; + clock-latency = <50000>; + capacity-dmips-mhz = <512>; + dynamic-power-coefficient = <1024>; + cpu-supply = <&vddcpua>; + cpu_supply_external_used; + dsu-opp-table = <1200000 879000 1500000 939000>; + dsu_clock_shared; + dsu-low-rate = <1000000>; + dvfs_sibling_core_num = <4>; + dvfs_sibling_cores = <0 1 2 3>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a76","arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>; + #cooling-cells = <2>; + //clocks = <&clkc CLKID_CPU_CLK>, + // <&clkc CLKID_CPU_DYN_CLK>, + // <&clkc CLKID_SYS_PLL>, + // <&clkc CLKID_DSU_CLK>, + // <&clkc CLKID_DSU_DYN_CLK>, + // <&clkc CLKID_GP1_PLL>; + //clock-names = "core_clk", + // "low_freq_clk_parent", + // "high_freq_clk_parent", + // "dsu_clk", + // "dsu_pre_parent", + // "dsu_pre_parent2"; + operating-points-v2 = <&a76_opp_table0>; + voltage-tolerance = <0>; + clock-latency = <50000>; + capacity-dmips-mhz = <512>; + dynamic-power-coefficient = <1024>; + cpu-supply = <&vddcpua>; + cpu_supply_external_used; + dsu-opp-table = <1200000 879000 1500000 939000>; + dsu_clock_shared; + dsu-low-rate = <1000000>; + dvfs_sibling_core_num = <4>; + dvfs_sibling_cores = <0 1 2 3>; + }; + + CPU4:cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a76","arm,armv8"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>; + #cooling-cells = <2>; + //clocks = <&clkc CLKID_A76_CLK>, + // <&clkc CLKID_A76_DYN_CLK>, + // <&clkc CLKID_SYS1_PLL>, + // <&clkc CLKID_DSU_CLK>, + // <&clkc CLKID_DSU_DYN_CLK>, + // <&clkc CLKID_GP1_PLL>; + //clock-names = "core_clk", + // "low_freq_clk_parent", + // "high_freq_clk_parent", + // "dsu_clk", + // "dsu_pre_parent", + // "dsu_pre_parent2"; + operating-points-v2 = <&a76_opp_table0>; + voltage-tolerance = <0>; + cpu-supply = <&vddcpub>; + dsu-supply = <&vddcpua>; + clock-latency = <50000>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <512>; + dsu-opp-table = <1200000 879000 1500000 939000>; + dsu_clock_shared; + dsu-low-rate = <1000000>; + dvfs_sibling_core_num = <1>; + dvfs_sibling_cores = <4>; + }; + + idle-states { + entry-method = "arm,psci-0.2"; + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <4000>; + exit-latency-us = <5000>; + min-residency-us = <10000>; + }; + SYSTEM_SLEEP_0: system-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000000>; + entry-latency-us = <0x3fffffff>; + exit-latency-us = <0x40000000>; + min-residency-us = <0xffffffff>; + }; + }; + }; + + dsu-pmu-0 { + compatible = "arm,dsu-pmu"; + status = "disabled"; + cpus = <&CPU0>,<&CPU1>,<&CPU2>,<&CPU3>,<&CPU4>; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + timer_bc { + /*compatible = "amlogic,bc-timer";*/ + reg= <0x0 0xfe0100D8 0x0 0x4 0x0 0xfe0100DC 0x0 0x4>; + timer_name = "Meson TimerD"; + clockevent-rating=<300>; + clockevent-shift=<20>; + clockevent-features=<0x23>; + interrupts = <0 3 1>; + bit_enable=<7>; + bit_mode=<6>; + bit_resolution=<0>; + resolution_1us=<1>; + min_delta_ns=<10>; + }; + + arm_pmu { + compatible = "arm,armv8-pmuv3"; + private-interrupts; + interrupts = , + , + , + , + ; + }; + + gic: interrupt-controller@fff01000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfff01000 0 0x1000>, + <0x0 0xfff02000 0 0x0100>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + meson_suspend:pm { + compatible = "amlogic, pm"; + status = "disabled"; + device_name = "aml_pm"; + extend_resume_reason; + reg = <0x0 0xfe010288 0x0 0x4>, /*SYSCTRL_STATUS_REG2*/ + <0x0 0xfe0102dc 0x0 0x4>; /*SYSCTRL_STICKY_REG7*/ + }; + + aml_reboot { + compatible = "aml, reboot"; + sys_reset = <0x84000009>; + sys_poweroff = <0x84000008>; + reg = <0x0 0xfe01037c 0x0 0x4>; /*SYSCTRL_SEC_STATUS_REG31*/ + dis_nb_cpus_in_shutdown; + status = "disabled"; + }; + + ram-dump { + compatible = "amlogic, ram_dump"; + status = "disabled"; + reg = <0x0 0xFE0102D8 0x0 4>; + reg-names = "SYSCTRL_STICKY_REG6"; + store_device = "data"; + }; + + dolby_fw: dolby_fw { + compatible = "amlogic, dolby_fw"; + mem_size = <0x100000>; + status = "disabled"; + }; + + secmon { + compatible = "amlogic, secmon"; + memory-region = <&secmon_reserved>; + in_base_func = <0x82000020>; + out_base_func = <0x82000021>; + reserve_mem_size = <0x00400000>; + clear_range = <0x05100000 0x200000>; + }; + + cma_shrinker: cma_shrinker { + compatible = "amlogic, cma-shrinker"; + status = "disabled"; + adj = <0 100 200 250 900 950>; + free = <8192 12288 16384 24576 28672 32768>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + cpu_info { + compatible = "amlogic, cpuinfo"; + status = "okay"; + cpuinfo_cmd = <0x82000044>; + }; + + vrtc: rtc@0xfe010288 { + compatible = "amlogic,meson-vrtc"; + reg = <0x0 0xfe010288 0x0 0x4>; + status = "disabled"; + //mboxes = <&mhu_fifo S5_REE2AO>; + }; + + pwrdm: power-domains { + compatible = "amlogic,s5-power-domain"; + #power-domain-cells = <1>; + status = "disabled"; + }; + + adla: adla@0xfe371000 { + compatible = "amlogic,adla"; + dev_name = "adla"; + status = "disabled"; + reg = <0x0 0xfe371000 0x0 0x2000 + 0x0 0xf7038000 0x0 0x40000 + >; + reg-names = "adla_reg\0adla_sram"; + interrupt-names = "adla"; + interrupts = <0 148 1>; + //clocks = <&clkc CLKID_NNA>; + //clock-names = "adla_core_clk"; + //assigned-clocks =<&clkc CLKID_NNA>; + //assigned-clock-parentsd = <&clkc CLKID_FCLK_DIV2P5>; + //assigned-clock-rates = <800000000>; + power-domains=<&pwrdm PDID_S5_NNA_4T>; + //memory-region = <&nna_cma_reserved>; + smmu; + regulator_nn; + }; + + nna_top_ports_wrapper_0: nna_top_ports_wrapper@fe370000 { + compatible = "amazon,nna-1.0"; + device-name = "acenna0"; + status = "disabled"; +// clocks = <&clkc CLKID_NNA0>; +// assigned-clocks =<&clkc CLKID_NNA0>; +// assigned-clock-parentsd = <&clkc CLKID_FCLK_DIV2P5>; +// assigned-clock-rates = <800000000>; +// clock-names = "nna_clk_gate"; + interrupt-names = "nna_interrupt"; + interrupts = <0 148 1>; + minor-number = <0>; + //power-domains = <&pwrdm PDID_P1_NNA_A>, + // <&pwrdm PDID_P1_NNA_TOP>; + //power-domain-names = "pwrc-core","pwrc-top"; + reg = <0x0 0xfe370000 0x0 0x1000>; + reg-names = "nna_irq_wrapper"; + }; + + nna_top_ports_wrapper_1: nna_top_ports_wrapper@fe371000 { + compatible = "amazon,nna-1.0"; + device-name = "acenna1"; + status = "disabled"; +// clocks = <&clkc CLKID_NNA1>; +// assigned-clocks =<&clkc CLKID_NNA1>; +// assigned-clock-parentsd = <&clkc CLKID_FCLK_DIV2P5>; +// assigned-clock-rates = <800000000>; +// clock-names = "nna_clk_gate"; + interrupt-names = "nna_interrupt"; + interrupts = <0 149 1>; + minor-number = <1>; + //power-domains = <&pwrdm PDID_P1_NNA_B>, + // <&pwrdm PDID_P1_NNA_TOP>; + //power-domain-names = "pwrc-core","pwrc-top"; + reg = <0x0 0xfe371000 0x0 0x1000>; + reg-names = "nna_irq_wrapper"; + }; + + nna_top_ports_wrapper_2: nna_top_ports_wrapper@fe372000 { + compatible = "amazon,nna-1.0"; + device-name = "acenna2"; + status = "disabled"; +// clocks = <&clkc CLKID_NNA2>; +// assigned-clocks =<&clkc CLKID_NNA2>; +// assigned-clock-parentsd = <&clkc CLKID_FCLK_DIV2P5>; +// assigned-clock-rates = <800000000>; +// clock-names = "nna_clk_gate"; + interrupt-names = "nna_interrupt"; + interrupts = <0 150 1>; + minor-number = <2>; + //power-domains = <&pwrdm PDID_P1_NNA_C>, + // <&pwrdm PDID_P1_NNA_TOP>; + //power-domain-names = "pwrc-core","pwrc-top"; + reg = <0x0 0xfe372000 0x0 0x1000>; + reg-names = "nna_irq_wrapper"; + }; + + nna_top_ports_wrapper_3: nna_top_ports_wrapper@fe373000 { + compatible = "amazon,nna-1.0"; + device-name = "acenna3"; + status = "disabled"; +// clocks = <&clkc CLKID_NNA3>; +// assigned-clocks =<&clkc CLKID_NNA3>; +// assigned-clock-parentsd = <&clkc CLKID_FCLK_DIV2P5>; +// assigned-clock-rates = <800000000>; +// clock-names = "nna_clk_gate"; + interrupt-names = "nna_interrupt"; + interrupts = <0 151 1>; + minor-number = <3>; + //power-domains = <&pwrdm PDID_P1_NNA_D>, + // <&pwrdm PDID_P1_NNA_TOP>; + //power-domain-names = "pwrc-core","pwrc-top"; + reg = <0x0 0xfe373000 0x0 0x1000>; + reg-names = "nna_irq_wrapper"; + }; + nna_top_ports_wrapper_4: nna_top_ports_wrapper@fe374000 { + compatible = "amazon,nna-1.0"; + device-name = "acenna4"; + status = "disabled"; +// clocks = <&clkc CLKID_NNA4>; +// assigned-clocks =<&clkc CLKID_NNA4>; +// assigned-clock-parentsd = <&clkc CLKID_FCLK_DIV2P5>; +// assigned-clock-rates = <800000000>; +// clock-names = "nna_clk_gate"; + interrupt-names = "nna_interrupt"; + interrupts = <0 152 1>; + minor-number = <4>; + //power-domains = <&pwrdm PDID_P1_NNA_E>, + // <&pwrdm PDID_P1_NNA_TOP>; + //power-domain-names = "pwrc-core","pwrc-top"; + reg = <0x0 0xfe374000 0x0 0x1000>; + reg-names = "nna_irq_wrapper"; + }; + nna_top_ports_wrapper_5: nna_top_ports_wrapper@fe375000 { + compatible = "amazon,nna-1.0"; + device-name = "acenna5"; + status = "disabled"; +// clocks = <&clkc CLKID_NNA5>; +// assigned-clocks =<&clkc CLKID_NNA5>; +// assigned-clock-parentsd = <&clkc CLKID_FCLK_DIV2P5>; +// assigned-clock-rates = <800000000>; +// clock-names = "nna_clk_gate"; + interrupt-names = "nna_interrupt"; + interrupts = <0 153 1>; + minor-number = <5>; + //power-domains = <&pwrdm PDID_P1_NNA_F>, + // <&pwrdm PDID_P1_NNA_TOP>; + //power-domain-names = "pwrc-core","pwrc-top"; + reg = <0x0 0xfe375000 0x0 0x1000>; + reg-names = "nna_irq_wrapper"; + }; + + jtag { + compatible = "amlogic, jtag"; + status = "disabled"; + select = "disable"; /* disable/jtag_a/jtag_b */ + pinctrl-names= "jtag_a_pins", "jtag_b_pins"; + pinctrl-0= <&jtag_a_pins>; + pinctrl-1= <&jtag_b_pins>; + }; + + hifi4dsp: hifi4dsp { + compatible = "amlogic, hifi4dsp"; + memory-region = <&dsp_fw_reserved>; + reg = <0 0xfe340018 0 0x114>, /*dspa base address*/ + <0 0xfe350018 0 0x114>, /*dspb base address*/ + <0 0xfe010258 0 0x4>, /*dspa status counter*/ + <0 0xfe01025c 0 0x4>, /*dspb status counter*/ + <0 0x30820000 0 0x80000>; /*dsp shm region*/ + dsp-monitor-period-ms = <1000>; + reg-names = "dspa_top_reg", "dspb_top_reg"; +// clocks = <&clkc CLKID_DSPA>, <&clkc CLKID_DSPB>; +// clock-names = "dspa_clk", "dspb_clk"; + dsp-start-mode = <1>; /*0:scpi start mode,1:smc start mode*/ + dsp-cnt = <2>; + dspaoffset = <0x00000>; + dspboffset = <0x800000>; + bootlocation = <1>; /*1: boot from DDR, 2: from sram, 3...*/ + boot_sram_addr = <0xfff00000>; + boot_sram_size = <0x80000>; + //dspsrambase = <0xf7100000>; + //dspsramsize = <0x100000>; + //power-domains = <&pwrdm PDID_P1_DSPA>, + // <&pwrdm PDID_P1_DSPB>; + //power-domain-names = "dspa", "dspb"; + status = "disabled"; + }; + + vddcpua: pwm_cd-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm_cd MESON_PWM_1 1500 0>; + regulator-name = "vddcpua"; + regulator-min-microvolt = <689000>; + regulator-max-microvolt = <1049000>; + regulator-always-on; + max-duty-cycle = <1500>; + /* Voltage Duty-Cycle */ + voltage-table = <1049000 0>, + <1039000 3>, + <1029000 6>, + <1019000 9>, + <1009000 12>, + <999000 14>, + <989000 17>, + <979000 20>, + <969000 23>, + <959000 26>, + <949000 29>, + <939000 31>, + <929000 34>, + <919000 37>, + <909000 40>, + <899000 43>, + <889000 45>, + <879000 48>, + <869000 51>, + <859000 54>, + <849000 56>, + <839000 59>, + <829000 62>, + <819000 65>, + <809000 68>, + <799000 70>, + <789000 73>, + <779000 76>, + <769000 79>, + <759000 81>, + <749000 84>, + <739000 87>, + <729000 89>, + <719000 92>, + <709000 95>, + <699000 98>, + <689000 100>; + status = "disabled"; + }; + + vddcpub: pwm_ab-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm_ab MESON_PWM_0 1500 0>; + regulator-name = "vddcpub"; + regulator-min-microvolt = <689000>; + regulator-max-microvolt = <1049000>; + regulator-always-on; + max-duty-cycle = <1500>; + /* Voltage Duty-Cycle */ + voltage-table = <1049000 0>, + <1039000 3>, + <1029000 6>, + <1019000 9>, + <1009000 12>, + <999000 14>, + <989000 17>, + <979000 20>, + <969000 23>, + <959000 26>, + <949000 29>, + <939000 31>, + <929000 34>, + <919000 37>, + <909000 40>, + <899000 43>, + <889000 45>, + <879000 48>, + <869000 51>, + <859000 54>, + <849000 56>, + <839000 59>, + <829000 62>, + <819000 65>, + <809000 68>, + <799000 70>, + <789000 73>, + <779000 76>, + <769000 79>, + <759000 81>, + <749000 84>, + <739000 87>, + <729000 89>, + <719000 92>, + <709000 95>, + <699000 98>, + <689000 100>; + status = "disabled"; + }; + + vddnpu: pwm_ef-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm_ef MESON_PWM_0 1500 0>; + regulator-name = "vddnpu"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <900000>; + //regulator-always-on; + max-duty-cycle = <1500>; + /* Voltage Duty-Cycle */ + voltage-table = + <900000 0>, + <890000 5>, + <880000 11>, + <870000 17>, + <860000 21>, + <850000 28>, + <840000 33>, + <830000 39>, + <820000 44>, + <810000 50>, + <800000 56>, + <790000 61>, + <780000 67>, + <770000 72>, + <760000 78>, + <750000 83>, + <740000 89>, + <730000 95>, + <720000 100>; + status = "disabled"; + }; + + vdd_npu: fixedregulator@vdd_npu { + compatible = "regulator-fixed"; + vin-supply = <&vbat>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <910000>; + regulator-max-microvolt = <910000>; + pinctrl-names = "default"; + gpio = <&gpio GPIOE_4 GPIO_ACTIVE_LOW>; + startup-delay-us = <70000>; + enable-active-low; + regulator-boot-on; + //regulator-always-on; + }; + + a76_opp_table0: a76_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <839000>; + }; + opp01 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <839000>; + }; + opp02 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <849000>; + }; + opp03 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <869000>; + }; + opp04 { + opp-hz = /bits/ 64 <1392000000>; + opp-microvolt = <889000>; + }; + opp05 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <909000>; + }; + opp06 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <929000>; + }; + opp07 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <949000>; + }; + opp08 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <969000>; + }; + opp09 { + opp-hz = /bits/ 64 <1896000000>; + opp-microvolt = <989000>; + }; + opp10 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1009000>; + }; + }; + + a55_opp_table0: a55_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <839000>; + }; + opp01 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <839000>; + }; + opp02 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <869000>; + }; + opp03 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <879000>; + }; + opp04 { + opp-hz = /bits/ 64 <1392000000>; + opp-microvolt = <919000>; + }; + opp05 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <939000>; + }; + opp06 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <959000>; + }; + opp07 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <979000>; + }; + opp08 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <989000>; + }; + opp09 { + opp-hz = /bits/ 64 <1896000000>; + opp-microvolt = <999000>; + }; + opp10 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1009000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + status = "disabled"; + }; + + saradc: saradc@fe026000 { + compatible = "amlogic,meson-g12a-saradc", + "amlogic,meson-saradc"; + status = "disabled"; + #io-channel-cells = <1>; + clocks = <&xtal>, + <&clkc CLKID_SYS_CLK_SAR_ADC>, + <&clkc CLKID_SARADC>, + <&clkc CLKID_SARADC_SEL>; + clock-names = "clkin", "core", + "adc_clk", "adc_sel"; + interrupts = ; + reg = <0x00 0xfe026000 0x00 0x48>; + }; + + vbat: fixedregulator@vbat { + compatible = "regulator-fixed"; + regulator-name = "12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc5v_reg: fixedregulator@vcc5v { + vin-supply = <&vbat>; + compatible = "regulator-fixed"; + regulator-name = "VCC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + // GPIOC_7 is OD mode + //gpio = <&gpio GPIOC_7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + apb4: apb4@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x480000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + status = "okay"; + + clkc: clock-controller { + compatible = "amlogic,s5-clkc"; + #clock-cells = <1>; + reg = <0x0 0x0 0x0 0xb54>, + <0x0 0x8000 0x0 0x34c>, + <0x0 0xe040 0x0 0xbc>; + reg-names = "basic", "pll", "cpu_clk"; + clocks = <&xtal>; + clock-names = "xtal"; + status = "disabled"; + }; + + meson_clk_msr@48000 { + compatible = "amlogic,meson-s5-clk-measure"; + reg = <0x0 0x48000 0x0 0x1c>; + status = "okay"; + }; + + watchdog@2100 { + compatible = "amlogic,meson-sc2-wdt"; + status = "disabled"; + /* 0:userspace, 1:kernel */ + amlogic,feed_watchdog_mode = <1>; + reg = <0x0 0x2100 0x0 0x10>; + clocks = <&xtal>; + }; + + periphs_pinctrl: pinctrl@4008 { + compatible = "amlogic,meson-s5-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@4008 { + reg = <0x0 0x4000 0x0 0x008c>, + <0x0 0x4200 0x0 0x026c>; + reg-names = "mux", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 0 107>; + }; + }; + + storage_pinctrl: pinctrl@86000 { + compatible = "amlogic,meson-s5-storage-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio_sto: bank@86000 { + reg = <0x0 0x86000 0x0 0x8>, + <0x0 0x86380 0x0 0x020>; + reg-names = "mux", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&storage_pinctrl 0 0 13>; + }; + }; + + gpio_intc: interrupt-controller@40c0 { + compatible = "amlogic,meson-s5-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x40c0 0x0 0x50>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <288 289 290 291 292 293 294 295 296 297 298 299 + 300 301 302 303 304 305 306 307 308 309 310 311 + 312 313 314 315 316 317 318 319>; + }; + + spicc0: spi@50000 { + compatible = "amlogic,meson-s5-spicc"; + reg = <0x0 0x50000 0x0 0x44>; + interrupts = ; + //clocks = <&clkc CLKID_SYS_CLK_SPICC0>, + // <&clkc CLKID_SPICC0>; + //clock-names = "core", "async"; + #address-cells = <1>; + #size-cells = <0>; + //power-domains = <&pwrdm PDID_T7_SPICC0>; + status = "disabled"; + }; + + spicc1: spi@52000 { + compatible = "amlogic,meson-s5-spicc"; + reg = <0x0 0x52000 0x0 0x44>; + interrupts = ; + //clocks = <&clkc CLKID_SYS_CLK_SPICC1>, + // <&clkc CLKID_SPICC1>; + //clock-names = "core", "async"; + #address-cells = <1>; + #size-cells = <0>; + //power-domains = <&pwrdm PDID_T7_SPICC1>; + status = "disabled"; + }; + + spicc2: spi@54000 { + compatible = "amlogic,meson-s5-spicc"; + reg = <0x0 0x54000 0x0 0x44>; + interrupts = ; + //clocks = <&clkc CLKID_SYS_CLK_SPICC2>, + // <&clkc CLKID_SPICC2>; + //clock-names = "core", "async"; + #address-cells = <1>; + #size-cells = <0>; + //power-domains = <&pwrdm PDID_T7_SPICC2>; + status = "disabled"; + }; + + spifc: spi@56000 { + compatible = "amlogic,meson-spifc"; + status = "disabled"; + reg = <0x0 0x56000 0x0 0x80>; +// clock-names = "default"; +// clocks = <&clkc CLKID_SYS_CLK_SPIFC>; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_all_pins>; + #address-cells = <1>; + #size-cells = <0>; + spi-nor@0 { + compatible = "jedec,spi-nor"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <16000000>; + }; + }; + + pwm_ab: pwm@58000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0x58000 0x0 0x24>, + <0x0 0x180 0x0 0x4>; + #pwm-cells = <3>; + clocks = <&clkc CLKID_PWM_A_SEL>, + <&clkc CLKID_PWM_B_SEL>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + pwm_cd: pwm@5a000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0x5a000 0x0 0x24>, + <0x0 0x184 0x0 0x4>; + #pwm-cells = <3>; + clocks = <&clkc CLKID_PWM_C_SEL>, + <&clkc CLKID_PWM_D_SEL>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + pwm_ef: pwm@5c000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0x5c000 0x0 0x24>, + <0x0 0x188 0x0 0x4>; + #pwm-cells = <3>; + clocks = <&clkc CLKID_PWM_E_SEL>, + <&clkc CLKID_PWM_F_SEL>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + pwm_gh: pwm@5e000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0x5e000 0x0 0x24>, + <0x0 0x18c 0x0 0x4>; + #pwm-cells = <3>; + clocks = <&clkc CLKID_PWM_G_SEL>, + <&clkc CLKID_PWM_H_SEL>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + pwm_ij: pwm@60000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0x60000 0x0 0x24>, + <0x0 0x190 0x0 0x4>; + #pwm-cells = <3>; + clocks = <&clkc CLKID_PWM_I_SEL>, + <&clkc CLKID_PWM_J_SEL>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + i2c0: i2c@66000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0x66000 0x0 0x48>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_SYS_CLK_I2C_M_A>; + status = "disabled"; + }; + i2c1: i2c@68000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0x68000 0x0 0x48>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_SYS_CLK_I2C_M_B>; + status = "disabled"; + }; + i2c2: i2c@6a000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0x6a000 0x0 0x48>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_SYS_CLK_I2C_M_C>; + status = "disabled"; + }; + i2c3: i2c@6c000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0x6c000 0x0 0x48>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_SYS_CLK_I2C_M_D>; + status = "disabled"; + }; + i2c4: i2c@6e000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0x6e000 0x0 0x48>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_SYS_CLK_I2C_M_E>; + status = "disabled"; + }; + i2c5: i2c@70000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0x070000 0x0 0x48>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_SYS_CLK_I2C_M_F>; + status = "disabled"; + }; + + reset: reset-controller@2000 { + compatible = "amlogic,meson-p1-reset"; + reg = <0x0 0x2000 0x0 0xa0>; + #reset-cells = <1>; + }; + + cpu_version { + compatible = "amlogic,meson-gx-ao-secure", "syscon"; + status = "disable"; + reg=<0x0 0x10220 0x0 0x140>; + }; + + gbl_timer_core: global-timer@8e000 { + compatible = "amlogic,meson-glb-timer-core"; + reg = <0x0 0x8e000 0x0 0x28>; + reg-names = "topctrl"; +// clocks = <&clkc CLKID_SYS_CLK_GLB>; +// clock-names = "glb_clk"; + }; + + gbl_timer_isp: global-timer@8e040 { + compatible = "amlogic,meson-glb-timer-isp"; + reg = <0x0 0x8e040 0x0 0x140>; + reg-names = "isp"; + }; + + gbl_timer_gpio_input: global-timer@8e180 { + compatible = "amlogic,meson-glb-timer-gpio-input"; + reg-names = "input-src-sel"; + reg = <0x0 0x8e180 0x0 0x56c>; + }; + + aml_hwspinlock_regs: syscon@e300 { + compatible = "syscon"; + reg = <0x0 0xe300 0x0 0x80>; + }; + }; + + crg21_otg: crg21otg@fe038000 { + compatible = "amlogic, amlogic-crg-otg"; + status = "disabled"; + usb2-phy-reg = <0xfe03808c>; + usb2-phy-reg-size = <0x80>; + m31-phy-reg = <0xfe074000>; + m31-phy-reg-size = <0x80>; + usb3-phy-reg = <0xfe038080>; + usb3-phy-reg-size = <0x20>; + interrupts = <0 128 IRQ_TYPE_EDGE_RISING>; + udc-name = "fdd00000.crgudc2"; + }; + + crg20: crg@fdf00000 { + compatible = "amlogic, crg"; + status = "disabled"; + reg = <0x0 0xfdf00000 0x0 0x100000>; + interrupts = <0 129 4>; + usb-phy = <&crg_phy_20>, <&crg3_phy_20>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + //clocks = <&clkc CLKID_SYS_CLK_USB>; + //clock-names = "crg_general"; + }; + + crg30_drd: crg2drd@fdd00000 { + status = "disabled"; + reg = <0x0 0xfdd00000 0x0 0x100000>; + interrupts = <0 131 4>; + usb-phy = <&usb2_m31_0_phy>, <&usb3_m31_0_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + //clocks = <&clkc CLKID_SYS_CLK_USB>; + //clock-names = "crg_general"; + }; + + crg31: crg@fde00000 { + compatible = "amlogic, crg"; + status = "disabled"; + reg = <0x0 0xfde00000 0x0 0x100000>; + interrupts = <0 130 4>; + usb-phy = <&usb2_m31_1_phy>, <&usb3_m31_1_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + //clocks = <&clkc CLKID_SYS_CLK_USB>; + //clock-names = "crg_general"; + }; + + usb2_m31_0_phy: usb2m310phy { + compatible = "amlogic, amlogic-usb2-m31-phy"; + status = "disable"; + #phy-cells = <0>; + }; + + usb3_m31_0_phy: usb3m310phy { + compatible = "amlogic, amlogic-usb3-m31-phy"; + status = "disable"; + #phy-cells = <0>; + reg = <0x0 0xfe002000 0x0 0x100>; + reset-level = <0x40>; + phy-reg = <0xfe074000>; + phy-reg-size = <0x2000>; + m31phy-reset-level-bit = <10>; + m31ctl-reset-level-bit = <6>; + m31-utmi-reset-level-bit = <2>; + u3-combx0-reset-bit = <53>; + uncomposite = <1>; + }; + + usb2_m31_1_phy: usb2m311phy { + compatible = "amlogic, amlogic-usb2-m31-phy"; + status = "disable"; + #phy-cells = <0>; + }; + + usb3_m31_1_phy: usb3m311phy { + compatible = "amlogic, amlogic-usb3-m31-phy"; + status = "disable"; + #phy-cells = <0>; + reg = <0x0 0xfe002000 0x0 0x100>; + reset-level = <0x40>; + phy-reg = <0xfe076000>; + phy-reg-size = <0x2000>; + m31phy-reset-level-bit = <9>; + m31ctl-reset-level-bit = <5>; + uncomposite = <1>; + }; + + crg_phy_20: crgphy20@fe072000 { + compatible = "amlogic, amlogic-crg-drd-usb2"; + status = "disable"; + #phy-cells = <0>; + reg = <0x0 0xfe03c000 0x0 0x80 + 0x0 0xFE002000 0x0 0x100 + 0x0 0xfe072000 0x0 0x2000>; + pll-setting-1 = <0x09400414>; + pll-setting-2 = <0x927E0000>; + pll-setting-3 = <0xac5f69e5>; + pll-setting-4 = <0xbe18>; + pll-setting-5 = <0x7>; + pll-setting-6 = <0x78000>; + pll-setting-7 = <0xe0004>; + pll-setting-8 = <0xe000c>; + dis-thred-enhance = <0x2>;/**t7-0x38:bit[26-27]**/ + version = <3>; + //power-domains = <&pwrdm PDID_SC2_USB_COMB>; + phy0-reset-level-bit = <8>; + usb-reset-bit = <3>; + reset-level = <0x40>; + pwr-ctl = <0>; + //clocks = <&clkc CLKID_SYS_CLK_USB>; + //clock-names = "crg_general"; + phy-id = <0>; + usb-phy-trim-reg = <0xfe010330>; + }; + + crg3_phy_20: crg3phy20@fe03c080 { + compatible = "amlogic, amlogic-crg-drd-usb3"; + status = "disable"; + #phy-cells = <0>; + reg = <0x0 0xfe03c080 0x0 0x20>; + phy1-reg = <0xfe072000>; + phy1-reg-size = <0x2000>; + reset-reg = <0xFE002000>; + reset-reg-size = <0x100>; + reset-level = <0x40>; + phy-id = <0>; + }; + + crg_udc_2: crgudc2@0xfdd00000 { + compatible = "amlogic, crg_udc"; + status = "disable"; + device_name = "crg_udc_2"; + reg = <0x0 0xfdd00000 0x0 0x100000>; + interrupts = <0 131 4>; + //clock-src = "usb0"; /** clock src */ + port-speed = <3>; /** 0: default, high, 1: full */ + phy-reg = <0xfe074000>; + phy-reg-size = <0x1000>; + //clocks = <&clkc CLKID_SYS_CLK_USB>; + //clock-names = "usb_general"; + phy-id = <2>; + controller-type = <4>; + }; + + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disabled"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, s4_codec_T9015"; + reg = <0x0 0xFE01A000 0x0 0x2000>; + tocodec_inout = <2>; + tdmout_index = <2>; + ch0_sel = <0>; + ch1_sel = <1>; + + reset-names = "acodec"; + resets = <&reset RESET_ACODEC>; + + status = "disabled"; + }; + + audio_data: audio_data { + compatible = "amlogic, audio_data"; + mem_in_base_cmd = <0x82000020>; + query_licence_cmd = <0x82000050>; + status = "disabled"; + }; + + amaudio: amaudio { + compatible = "amlogic, amaudio"; + reg = <0x0 0xfe440000 0x0 0x10000>; + reg-names = "otp_tee_base"; + status = "disabled"; + }; + + audiobus: audiobus@0xFE330000 { + compatible = "amlogic, audio-controller", "simple-bus"; + reg = <0x0 0xFE330000 0x0 0x3000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xFE330000 0x0 0x3000>; + chip_id = <0x3e>; + // power-domains = <&pwrdm PDID_T7_AUDIO>; + status = "disabled"; + + clkaudio: audio_clocks { + compatible = "amlogic, s5-audio-clocks"; + #clock-cells = <1>; + reg = <0x0 0x0 0x0 0xb0>; + status = "disabled"; + }; + ddr_manager { + compatible = + "amlogic, s5-audio-ddr-manager"; + interrupts = < + GIC_SPI 32 IRQ_TYPE_EDGE_RISING + GIC_SPI 33 IRQ_TYPE_EDGE_RISING + GIC_SPI 34 IRQ_TYPE_EDGE_RISING + GIC_SPI 45 IRQ_TYPE_EDGE_RISING + GIC_SPI 36 IRQ_TYPE_EDGE_RISING + GIC_SPI 37 IRQ_TYPE_EDGE_RISING + GIC_SPI 38 IRQ_TYPE_EDGE_RISING + GIC_SPI 46 IRQ_TYPE_EDGE_RISING + >; + interrupt-names = + "toddr_a", "toddr_b", "toddr_c", + "toddr_d", + "frddr_a", "frddr_b", "frddr_c", + "frddr_d"; + status = "disabled"; + }; + pcpd_monitor_a: pcpd_monitor@0 { + compatible = "amlogic, pcpda_monitor"; + interrupts = ; + interrupt-names = "irq_pcpd"; + status = "disabled"; + }; + pcpd_monitor_b: pcpd_monitor@1 { + compatible = "amlogic, pcpdb_monitor"; + interrupts = ; + interrupt-names = "irq_pcpd"; + status = "disabled"; + }; + + pinctrl_audio: pinctrl { + compatible = "amlogic, audio-pinctrl"; + status = "disabled"; + }; + };/* end of audiobus*/ + + /* eARC */ + audio_earc: bus@fe333000 { + compatible = "simple-bus"; + reg = <0x0 0xfe333000 0x0 0x1000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe333000 0x0 0x1000>; + + earc: earc@0 { + compatible = "amlogic, s5-snd-earc"; + #sound-dai-cells = <0>; + + status = "disabled"; + + reg = + <0x0 0x800 0x0 0x400>, + <0x0 0xc00 0x0 0x200>, + <0x0 0xe00 0x0 0x200>; + reg-names = + "rx_cmdc", + "rx_dmac", + "rx_top"; + + //clocks = < &clkaudio CLKID_EARCRX_CMDC + // &clkaudio CLKID_EARCRX_DMAC + // &clkc CLKID_FCLK_DIV4 + // &clkc CLKID_FCLK_DIV4 + // &clkaudio CLKID_EARCTX_CMDC + // &clkaudio CLKID_EARCTX_DMAC + // &clkc CLKID_FCLK_DIV4 + // &clkc CLKID_HIFI_PLL + // >; + //clock-names = + // "rx_cmdc", + // "rx_dmac", + // "rx_cmdc_srcpll", + // "rx_dmac_srcpll"; + + interrupts = ; + interrupt-names = "earc_rx"; + }; + }; + + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, snd-iomap"; + status = "disabled"; + #address-cells=<2>; + #size-cells=<2>; + ranges; + pdm_bus { + reg = <0x0 0xFE331000 0x0 0x400>; + }; + audiobus_base { + reg = <0x0 0xFE330000 0x0 0x1000>; + }; + audiolocker_base { + reg = <0x0 0xFE331400 0x0 0x400>; + }; + eqdrc_base { + reg = <0x0 0xFE332000 0x0 0x1000>; + }; + vad_base { + reg = <0x0 0xFE331800 0x0 0x400>; + }; + resampleA_base { + reg = <0x0 0xFE331c00 0x0 0x104>; + }; + resampleB_base { + reg = <0x0 0xFE334000 0x0 0x104>; + }; + pdm_bus_b { + reg = <0x0 0xFE334800 0x0 0x400>; + }; + }; + + pcie1: pcie@e0000000 { + compatible = "amlogic, amlogic-pcie-v3"; + reg = <0x0 0xe0000000 0x0 0x1000 + 0x0 0xfe02c000 0x0 0x2000 + 0x0 0xe0000000 0x0 0x8000000 + 0x0 0xe7e00000 0x0 0x200000 + 0x0 0xfe076000 0x0 0x2000 + 0x0 0xfe002040 0x0 0x10>; + reg-names = "apb-base", "pcictrl-base", "axi-base", + "ecam-base", "phy-base", "reset-base"; + interrupts = ; + #interrupt-cells = <1>; + msi-controller; + msi-parent = <&pcie1>; + interrupt-parent = <&gic>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 408 + IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 409 + IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 410 + IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 411 + IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ranges = + /* + * <0x81000000 0 0xe0001000 + * 0 0xe0001000 0x0 0x100000>, + */ + /*downstream I/O */ + <0x82000000 0 0xe1000000 0x0 0xe1000000 + 0 0x4000000>; + /* non-prefetched memory */ + num-lanes = <1>; + port-num = <1>; + phy-type = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcieck_1_pins>; + + //clocks = <&clkc CLKID_PCIE1_PLL + // &clkc CLKID_SYS_CLK_PCIE + // &clkc CLKID_SYS_CLK_PCIE_PHY1 + // &clkc CLKID_PCIE1_HCSL_OUT + // &clkc CLKID_PCIE_400M + // &clkc CLKID_PCIE_TL_CLK + // &clkc CLKID_PCIE_CLK>; + //clock-names = "pcie_refpll", + // "pcie", + // "pcie_phy", + // "pcie_hcsl", + // "pcie_400m_clk", + // "pcie_tl_clk", + // "cts_pcie_clk"; + /*reset-gpio-type + *0:Shared pad(no reset) + *1:OD pad2:Normal pad + */ + gpio-type = <2>; + pcie-gen2-l0-rst-bit = <12>; + pcie-apb-rst-bit = <6>; + pcie-phy-rst-bit = <9>; + pcie-a-rst-bit = <13>; + pcie-rst-bit = <4>; + pcie-rst-mask = <0xff>; + power-domains = <&pwrdm PDID_S5_PCIE1>; + status = "disabled"; + /* iommu-map = <0x100 &smmu P1_SID_PCIE 0x10>; */ + dma-ranges = <0x0 0x0 0x0 0x0 0x0 0x0 0xe0000000>; + }; + + pcie0: pcie@e8000000 { + compatible = "amlogic, amlogic-pcie-v3"; + reg = <0x0 0xe8000000 0x0 0x1000 + 0x0 0xfe02a000 0x0 0x2000 + 0x0 0xe8000000 0x0 0x8000000 + 0x0 0xefe00000 0x0 0x200000 + 0x0 0xfe074000 0x0 0x2000 + 0x0 0xfe002040 0x0 0x10>; + reg-names = "apb-base", "pcictrl-base", "axi-base", + "ecam-base", "phy-base", "reset-base"; + interrupts = ; + #interrupt-cells = <1>; + msi-controller; + msi-parent = <&pcie0>; + interrupt-parent = <&gic>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 188 + IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 91 + IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 92 + IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 93 + IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ranges = + /* + * <0x81000000 0 0xff000000 + * 0 0xe8001000 0x0 0x100000 + */ + /*downstream I/O */ + <0x82000000 0 0xe8200000 0x0 0xe8200000 + 0 0x7c00000>; + /* non-prefetched memory */ + num-lanes = <1>; + port-num = <0>; + phy-type = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcieck_0_pins>; + + //clocks = <&clkc CLKID_PCIE_PLL + // &clkc CLKID_SYS_CLK_PCIE + // &clkc CLKID_SYS_CLK_PCIE_PHY0 + // &clkc CLKID_PCIE_HCSL_OUT + // &clkc CLKID_PCIE_400M + // &clkc CLKID_PCIE_TL_CLK + // &clkc CLKID_PCIE_CLK>; + //clock-names = "pcie_refpll", + // "pcie", + // "pcie_phy", + // "pcie_hcsl", + // "pcie_400m_clk", + // "pcie_tl_clk", + // "cts_pcie_clk"; + /*reset-gpio-type + *0:Shared pad(no reset) + *1:OD pad2:Normal pad + */ + gpio-type = <2>; + pcie-gen2-l0-rst-bit = <18>; + pcie-apb-rst-bit = <7>; + pcie-phy-rst-bit = <10>; + pcie-a-rst-bit = <14>; + pcie-rst-bit = <12>; + pcie-rst-mask = <0xff>; + power-domains = <&pwrdm PDID_S5_PCIE0>; + status = "disabled"; + /* iommu-map = <0x100 &smmu P1_SID_PCIE 0x10>; */ + dma-ranges = <0x0 0x0 0x0 0x0 0x0 0x0 0xe0000000>; + }; + + sd_emmc_c: mmc@fe08c000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0xfe08c000 0x0 0x800>, + <0x0 0xfe000168 0x0 0x4>, + <0x0 0xfe086000 0x0 0x4>; + interrupts = ; + status = "disabled"; + //clocks = <&clkc CLKID_SYS_CLK_SD_EMMC_C>, + // <&clkc CLKID_SD_EMMC_C_CLK_SEL>, + // <&clkc CLKID_SD_EMMC_C_CLK>, + // <&xtal>, + // <&clkc CLKID_GP0_PLL>, + // <&clkc CLKID_GP0_PLL>; + //clock-names = "core", "mux0", "mux1", + // "clkin0", "clkin1", "clkin2"; + card_type = <1>; + src_clk_rate = <1536000000>; + mmc_debug_flag; + ignore_desc_busy; + tx_delay = <20>; + nwr_cnt = <12>; + // supports-cqe; + // resets = <&reset RESET_SD_EMMC_C>; + }; + + sd_emmc_b: sd@fe08a000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0xfe08a000 0x0 0x800>, + <0x0 0xfe00016c 0x0 0x4>, + <0x0 0xfe00400c 0x0 0x4>; + interrupts = ; + status = "disabled"; + //clocks = <&clkc CLKID_SYS_CLK_SD_EMMC_B>, + // <&clkc CLKID_SD_EMMC_B_CLK_SEL>, + // <&clkc CLKID_SD_EMMC_B_CLK>, + // <&xtal>, + // //<&clkc CLKID_FCLK_DIV2>; + // <&clkc CLKID_GP0_PLL>; + //clock-names = "core", "mux0", "mux1", + // "clkin0", "clkin1"; + card_type = <5>; + src_clk_rate = <1536000000>; + use_intf3_tuning; + mmc_debug_flag; + //resets = <&reset RESET_SD_EMMC_B>; + }; + + sd_emmc_a: sdio@fe088000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0xfe088000 0x0 0x800>, + <0x0 0xfe00016c 0x0 0x4>, + <0x0 0xfe004038 0x0 0x4>; + interrupts = ; + status = "disabled"; + //clocks = <&clkc CLKID_SYS_CLK_SD_EMMC_A>, + // <&clkc CLKID_SD_EMMC_A_CLK_SEL>, + // <&clkc CLKID_SD_EMMC_A_CLK>, + // <&xtal>, + // //<&clkc CLKID_FCLK_DIV2>; + // <&clkc CLKID_GP0_PLL>; + //clock-names = "core", "mux0", "mux1", + // "clkin0", "clkin1"; + card_type = <3>; + cap-sdio-irq; + keep-power-in-suspend; + src_clk_rate = <1536000000>; + use_intf3_tuning; + mmc_debug_flag; + //resets = <&reset RESET_SD_EMMC_A>; + }; + + ethmac: ethernet@fdc00000 { + compatible = "amlogic,meson-axg-dwmac", + "snps,dwmac-3.70a", + "snps,dwmac"; + reg = <0x0 0xfdc00000 0x0 0x10000>, + <0x0 0xfe024000 0x0 0x8>; + interrupts = ; + interrupt-names = "macirq"; + power-domains = <&pwrdm PDID_S5_ETH>; + //clocks = <&clkc CLKID_SYS_CLK_ETH>, + // <&clkc CLKID_FCLK_DIV2>, + // <&clkc CLKID_FCLK_CLK50M>; + //clock-names = "stmmaceth", "clkin0", "clkin1"; + rx-fifo-depth = <4096>; + tx-fifo-depth = <2048>; + /*1:inphy; 2:exphy;*/ + internal_phy = <2>; + cali_val = <0x80000>; + status = "disabled"; + ext_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + external_phy: ethernet-phy@0 { + reg = <0>; + max-speed = <1000>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | + GPIO_OPEN_DRAIN)>; + }; + }; + }; + + uart_A: serial@fe078000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0xfe078000 0x0 0x18>; + interrupts = <0 168 1>; + status = "disabled"; + clocks = <&xtal>; + clock-names = "clk_uart"; + xtal_tick_en = <2>; + fifosize = < 64 >; + support-sysrq = <1>; /* 0 not support*/ + }; + + uart_B: serial@fe07a000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0xfe07a000 0x0 0x18>; + interrupts = <0 169 1>; + status = "disabled"; + clocks = <&xtal>; + clock-names = "clk_uart"; + xtal_tick_en = <2>; + fifosize = < 64 >; + support-sysrq = <1>; /* 0 not support*/ + }; + + uart_C: serial@fe07c000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0xfe07c000 0x0 0x18>; + interrupts = <0 170 1>; + status = "disabled"; + clocks = <&xtal + &clkc CLKID_SYS_CLK_UART_C>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&c_uart_pins1>; + }; + + uart_D: serial@fe07e000 { + compatible = "amlogic,meson-uart"; + status = "disabled"; + reg = <0x0 0xfe07e000 0x0 0x18>; + interrupts = <0 171 1>; + clocks = <&xtal + &clkc CLKID_SYS_CLK_UART_D>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&d_uart_pins>; + }; + + uart_E: serial@fe080000 { + compatible = "amlogic,meson-uart"; + status = "disabled"; + reg = <0x0 0xfe080000 0x0 0x18>; + interrupts = <0 172 1>; + clocks = <&xtal + &clkc CLKID_SYS_CLK_UART_E>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&e_uart_pins>; + }; + + uart_F: serial@fe082000 { + compatible = "amlogic,meson-uart"; + status = "disabled"; + reg = <0x0 0xfe082000 0x0 0x18>; + interrupts = <0 180 1>; + clocks = <&xtal + &clkc CLKID_SYS_CLK_UART_F>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&f_uart_pins>; + }; + }; + + csiphy0: csiphy0@ff918000 { + compatible = "amlogic, csiphy"; + reg = <0x0 0xff918000 0x0 0x3000>, + <0x0 0xff9a0000 0x0 0x400>; + reg-names = "csi_phy","csi_aphy"; + //power-domains = <&pwrdm PDID_P1_MIPI_ISP_TOP>; +// clocks = <&clkc CLKID_CSIPHY0>; +// clock-names = "cts_mipi_csi_phy_clk"; + }; + + adapter0: adapter0@ff918000 { + compatible = "amlogic, adapter"; + reg = <0x0 0xff918000 0x0 0x6000>; + reg-names = "adapter"; + }; + + isp0: isp0@ff900000 { + compatible = "amlogic, isp"; + reg = <0x0 0xff900000 0x0 0x10000>; + /* interrupt-parent = <&intc>; */ + //power-domains = <&pwrdm PDID_P1_ISP_A>; +// clocks = <&clkc CLKID_ISP0>; +// clock-names = "cts_mipi_isp_clk"; + interrupts = <0 97 1>; + }; + + camera0 { + status = "disabled"; + compatible = "amlogic, camera"; + index = <0>; + csiphy = <&csiphy0>; + adapter = <&adapter0>; + isp = <&isp0>; + }; + + csiphy1: csiphy1@ff938000 { + compatible = "amlogic, csiphy"; + reg = <0x0 0xff938000 0x0 0x3000>, + <0x0 0xff9a0000 0x0 0x400>; + reg-names = "csi_phy","csi_aphy"; + //power-domains = <&pwrdm PDID_P1_MIPI_ISP_TOP>; +// clocks = <&clkc CLKID_CSIPHY1>; +// clock-names = "cts_mipi_csi_phy_clk"; + }; + + adapter1: adapter1@ff938000 { + compatible = "amlogic, adapter"; + reg = <0x0 0xff938000 0x0 0x6000>; + reg-names = "adapter"; + }; + + isp1: isp1@ff920000 { + compatible = "amlogic, isp"; + reg = <0x0 0xff920000 0x0 0x10000>; + /* interrupt-parent = <&intc>; */ + //power-domains = <&pwrdm PDID_P1_ISP_B>; +// clocks = <&clkc CLKID_ISP1>; +// clock-names = "cts_mipi_isp_clk"; + interrupts = <0 105 1>; + }; + + camera1 { + status = "disabled"; + compatible = "amlogic, camera"; + index = <1>; + csiphy = <&csiphy1>; + adapter = <&adapter1>; + isp = <&isp1>; + }; + + csiphy2: csiphy2@ff958000 { + compatible = "amlogic, csiphy"; + reg = <0x0 0xff958000 0x0 0x3000>, + <0x0 0xff9a0000 0x0 0x400>; + reg-names = "csi_phy","csi_aphy"; + //power-domains = <&pwrdm PDID_P1_MIPI_ISP_TOP>; +// clocks = <&clkc CLKID_CSIPHY2>; +// clock-names = "cts_mipi_csi_phy_clk"; + }; + + adapter2: adapter2@ff958000 { + compatible = "amlogic, adapter"; + reg = <0x0 0xff958000 0x0 0x6000>; + reg-names = "adapter"; + }; + + isp2: isp2@ff940000 { + compatible = "amlogic, isp"; + reg = <0x0 0xff940000 0x0 0x10000>; + /* interrupt-parent = <&intc>; */ + //power-domains = <&pwrdm PDID_P1_ISP_C>; +// clocks = <&clkc CLKID_ISP2>; +// clock-names = "cts_mipi_isp_clk"; + interrupts = <0 113 1>; + }; + + camera2 { + status = "disabled"; + compatible = "amlogic, camera"; + index = <2>; + csiphy = <&csiphy2>; + adapter = <&adapter2>; + isp = <&isp2>; + }; + + csiphy3: csiphy3@ff978000 { + compatible = "amlogic, csiphy"; + reg = <0x0 0xff978000 0x0 0x3000>, + <0x0 0xff9a0000 0x0 0x400>; + reg-names = "csi_phy","csi_aphy"; + //power-domains = <&pwrdm PDID_P1_MIPI_ISP_TOP>; +// clocks = <&clkc CLKID_CSIPHY3>; +// clock-names = "cts_mipi_csi_phy_clk"; + }; + + adapter3: adapter3@ff978000 { + compatible = "amlogic, adapter"; + reg = <0x0 0xff978000 0x0 0x6000>; + reg-names = "adapter"; + }; + + isp3: isp3@ff960000 { + compatible = "amlogic, isp"; + reg = <0x0 0xff960000 0x0 0x10000>; + /* interrupt-parent = <&intc>; */ + //power-domains = <&pwrdm PDID_P1_ISP_D>; +// clocks = <&clkc CLKID_ISP3>; +// clock-names = "cts_mipi_isp_clk"; + interrupts = <0 121 1>; + }; + + camera3 { + status = "disabled"; + compatible = "amlogic, camera"; + index = <3>; + csiphy = <&csiphy3>; + adapter = <&adapter3>; + isp = <&isp3>; + }; + + csiphy4: csiphy4@ff998000 { + compatible = "amlogic, csiphy"; + reg = <0x0 0xff998000 0x0 0x3000>, + <0x0 0xff9a0000 0x0 0x400>; + reg-names = "csi_phy","csi_aphy"; + //power-domains = <&pwrdm PDID_P1_MIPI_ISP_TOP>; +// clocks = <&clkc CLKID_CSIPHY4>; +// clock-names = "cts_mipi_csi_phy_clk"; + }; + + adapter4: adapter4@ff998000 { + compatible = "amlogic, adapter"; + reg = <0x0 0xff998000 0x0 0x6000>, + <0x0 0xff980000 0x0 0x1000>; + reg-names = "adapter","wrmif"; +// clocks = <&clkc CLKID_ISP4>; +// clock-names = "cts_mipi_wrmif_clk"; + interrupts = <0 81 1>; + }; + + camera4 { + status = "disabled"; + compatible = "amlogic, camera"; + index = <4>; + csiphy = <&csiphy4>; + adapter = <&adapter4>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "disabled"; + }; + vcodec_dos_dev: vcodec_dos_dev { + compatible = "amlogic, cpu-major-id-s5"; + dev_name = "vcodec_dos_dev"; + status = "disabled"; + reg = <0x0 0xfe320000 0x0 0x10000>, + <0x0 0xfe036000 0x0 0x2000>; + reg-names = "dosbus", + "dmcbus"; + //clocks = <&clkc CLKID_SYS_CLK_DOS + // &clkc CLKID_VDEC + // &clkc CLKID_HCODEC + // &clkc CLKID_HEVC>; + //clock-names = "vdec", + // "clk_vdec_mux", + // "clk_hcodec_mux", + // "clk_hevc_mux"; + //assigned-clock-parents = <&clkc CLKID_VDEC0>, + // <&clkc CLKID_HEVC0>; + //assigned-clocks = <&clkc CLKID_VDEC>, + // <&clkc CLKID_HEVC>; + }; + + vdec { + compatible = "amlogic, vdec-pm-pd"; + dev_name = "vdec.0"; + status = "disabled"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 10 1 + 0 17 1 + 0 18 1 + 0 16 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2", + "assist_mbox_irq_ee"; + power-domains = <&pwrdm PDID_S5_DOS_VDEC>, + <&pwrdm PDID_S5_DOS_HCODEC>, + <&pwrdm PDID_S5_DOS_HEVC_TOP>, + <&pwrdm PDID_S5_DOS_HEVC_CORE1>; + power-domain-names = "pwrc-vdec", + "pwrc-hcodec", + "pwrc-hevc", + "pwrc-hevcb"; + }; + + vcodec_dec { + compatible = "amlogic, vcodec-dec"; + dev_name = "aml-vcodec-dec"; + status = "disabled"; + }; + + di_local { + compatible = "amlogic, di-local"; + status = "disabled"; + }; + + multi-di { + compatible = "amlogic, dim-s5"; + status = "disabled"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <4>; //<1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 122 1 + 0 123 1 + 0 278 1>; + interrupt-names = "pre_irq", "post_irq", "aisr_irq"; + //clocks = <&clkc CLKID_VPU_CLKB>, + // <&clkc CLKID_VPU>; + //clock-names = "vpu_clkb", + // "vpu_mux"; + //clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + dct = <0>;//decontour disable + hf = <2>; //enable aisr + en_4k = <0>; + alloc_sct = <0>; + po_fmt = <0>; + /*************************************************** + * t3 support 4k ,same with t7 ,no canvas, + * post_nub---default is 11 + * (T7/T3/SC2/S4 new path)post 11*5222400 = 56M,local 7*4075520 = 28m + * flag_cma---0: use reserved; 1:use cma; 2:use cma as reserved 4:use codec mem + * en_4k :en_4k---0: not support 4K; 1: enable 4K + * 2: dynamic: vdin: 4k enable, other source 4k disable + * 8: when 4k,output with a resolution is below 1080p + * keep_dec_vf---0:not keep; 1: keep dec vf for p; + * 2: dynamic keep dec vf for p,other is disable + * po_fmt---1: NV21/8; 2: nv12/8; 3: AFBC 422/10BIT; + * 4: dynamic(4K AFBC,10/422); + * 6: dynamic(from decoder 4K source,out is AFBC,10/420),other is 422/10BIT + * bypass_mem---0:nr not bypass; 1: nr bypass; 2: when 4k input ,nr is bypass; + * 3: bypass nr for 4k,but not from vdin; + * alloc_sct---0:not support; bit 0: for 4k; bit 1: for 1080p + * hf---0:not enable; 1: enable + ***************************************************/ + }; + + ddr_bandwidth { + compatible = "amlogic,ddr-bandwidth-s5"; + status = "disabled"; + reg = <0 0xfe036000 0 0x200 + 0 0xfe034000 0 0x200 + 0 0xfe032000 0 0x200 + 0 0xfe030000 0 0x200 + 0 0xfe0368a4 0 0x4>; + interrupts = <0 332 IRQ_TYPE_EDGE_RISING + 0 336 IRQ_TYPE_EDGE_RISING + 0 340 IRQ_TYPE_EDGE_RISING + 0 54 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ddr_bandwidth"; + }; + + dmc_monitor { + compatible = "amlogic,dmc_monitor-s5"; + status = "disabled"; + reg = <0 0xfe036000 0 0x200 + 0 0xfe034000 0 0x200 + 0 0xfe032000 0 0x200 + 0 0xfe030000 0 0x200>; + reg_base = <0xfe036000>; + interrupts = <0 333 IRQ_TYPE_EDGE_RISING + 0 337 IRQ_TYPE_EDGE_RISING + 0 341 IRQ_TYPE_EDGE_RISING + 0 55 IRQ_TYPE_EDGE_RISING>; + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx-s5"; + dev_name = "amhdmitx"; + status = "disabled"; + //power-domains = <&pwrdm PDID_T7_VI_CLK2>; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + interrupts = <0 80 4 + 0 115 1>; + interrupt-names = "hdmitx_hpd", "vrr_vsync"; + enc_idx = <0>; + tx_max_frl_rate = <5>; /* max FRL_10G4L */ + reg = <0x0 0xff800000 0x0 0x40000>, + <0x0 0xfe3a0000 0x0 0x10000>, + <0x0 0xfe390000 0x0 0x10000>, + <0x0 0xfe010000 0x0 0x2000>, + <0x0 0xfe00c000 0x0 0x2000>, + <0x0 0xfe008000 0x0 0x2000>, + <0x0 0xfe002000 0x0 0x2000>, + <0x0 0xfe000000 0x0 0x2000>, + <0x0 0xfe004000 0x0 0x200>; + reg-names = "vpu", + "hdmitxcor", + "hdmitxtop", + "sysctrl", + "pwrctrl", + "anactrl", + "resetctrl", + "clkctrl", + "padctrl"; + + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + }; + }; + + aocec: aocec { + compatible = "amlogic, aocec-s5"; + dev_name = "aocec"; + status = "disabled"; + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* Refer to the following URL at: + * http://standards.ieee.org/develop/regauth/oui/oui.txt + */ + vendor_id = <0x000000>; + product_desc = "S5"; /* Max Chars: 16 */ + cec_osd_string = "AML_MBOX"; /* Max Chars: 14 */ + cec_version = <5>;/*5:1.4;6:2.0*/ + port_num = <1>; + output = <1>; + cec_sel = <1>;/*1:use one ip, 2:use 2 ip*/ + ee_cec; /*use cec b*/ + arc_port_mask = <0x1>; + interrupts = ;/*0:snps*/ + interrupt-names = "hdmi_aocecb"; + pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; + pinctrl-0=<&cec_b>; + pinctrl-1=<&cec_b>; + pinctrl-2=<&cec_b>; + //clocks = <&clkc CLKID_CECB_32K_CLKOUT>; + //clock-names = "cecb_clk"; + reg = <0x0 0xfe028000 0x0 0x2000 + 0x0 0xfe010000 0x0 0x2000 + 0x0 0xfe000000 0x0 0x2000 + 0x0 0xfe004000 0x0 0x2000>; + reg-names = "ao","periphs","clock","pad_reg"; + }; + + aml_dma { + compatible = "amlogic,aml_p1_dma"; + reg = <0x0 0xfe440400 0x0 0x48>; + interrupts = <0 24 1>; + status = "disabled"; + + aml_aes { + compatible = "amlogic,aes_g12a_dma"; + dev_name = "aml_aes_dma"; + status = "okay"; + iv_swap = /bits/ 8 <0x0>; + }; + + aml_sha { + compatible = "amlogic,sha_dma"; + dev_name = "aml_sha_dma"; + status = "okay"; + }; + + aml_tdes { + compatible = "amlogic,des_dma,tdes_dma"; + dev_name = "aml_tdes_dma"; + status = "okay"; + }; + + aml_sm4 { + compatible = "amlogic,sm4_dma"; + dev_name = "aml_sm4_dma"; + status = "okay"; + iv_swap = /bits/ 8 <0x0>; + }; + + crypto { + compatible = "amlogic,crypto_s5"; + dev_name = "aml_crypto_dev"; + status = "okay"; + thread = /bits/ 8 <0x5>; + interrupts = <0 29 1>; + }; + }; + + rng { + compatible = "amlogic,meson-rng"; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0xfe440788 0x0 0x0c>; + quality = /bits/ 16 <1000>; + version = <2>; + }; + + canvas: canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "disabled"; + reg = <0x0 0xfe036048 0x0 0x2000>; + }; + + codec_io: codec_io { + compatible = "amlogic, meson-s5, codec-io"; + status = "disabled"; + #address-cells=<2>; + #size-cells=<2>; + ranges; + /* use cbus space for reset_ctrl*/ + reg = <0x0 0xfe002000 0x0 0x2000>, + <0x0 0x0 0x0 0x0>, + <0x0 0x0 0x0 0x0>, + <0x0 0x0 0x0 0x00>, + <0x0 0xff800000 0x0 0x40000>, + <0x0 0xfe036000 0x0 0x2000>, + <0x0 0x0 0x0 0x0>; + reg-names = "cbus", + "dosbus", + "hiubus", + "aobus", + "vcbus", + "dmcbus", + "efusebus"; + }; + + jpegenc{ + compatible = "amlogic, jpegenc"; + dev_name = "jpegenc"; + status = "disabled"; + + //clocks = <&clkc CLKID_SYS_CLK_DOS +// &clkc CLKID_VAPB + // &clkc CLKID_HCODEC>; + + //clock-names = + // "clk_dos", +// "clk_apb_dos", + // "clk_jpeg_enc"; + +// clocks = <&clkc CLKID_HCODEC_P0>; +// clock-names = "hcodec_p0"; + power-domains = <&pwrdm PDID_S5_DOS_HCODEC>; + interrupts = <0 16 1 0 17 1 0 18 1>; + interrupt-names = "dos_mbox_slow_irq0", "dos_mbox_slow_irq1", "dos_mbox_slow_irq2"; + //reset-names = "jpegenc_rst"; + //resets = <&reset RESET_BRG_HCODEC_PIPL0>; + }; + aml_enc { + compatible = "cnm, MultiEnc"; + dev_name = "amvenc_multi"; + status = "disabled"; + config_mm_sz_mb = <200>; +// clocks = <&clkc CLKID_DOS +// &clkc CLKID_VAPB +// &clkc CLKID_WAVE_A_GATE +// &clkc CLKID_WAVE_B_GATE +// &clkc CLKID_WAVE_C_GATE>; +// clock-names = +// "clk_dos", +// "clk_apb_dos", +// "clk_MultiEnc_A", +// "clk_MultiEnc_B", +// "clk_MultiEnc_C"; + interrupts = <0 94 1 0 95 1>; + interrupt-names = "multienc_irq", "multienc_idle_irq"; + #address-cells=<2>; + #size-cells=<2>; + pwr-ctl = <0>; + //power-domains = <&pwrdm PDID_T7_DOS_WAVE>; + ranges; + io_reg_base { + reg = <0x0 0xfe310000 0x0 0x10000>; + }; + }; + + vpu: vpu { + compatible = "amlogic, vpu-s5"; + status = "disabled"; + reg = <0x0 0xfe000000 0x0 0xc00 /* clk */ + 0x0 0xfe00c000 0x0 0xb00 /* pwrctrl */ + 0x0 0xff800000 0x0 0x20000>; /* vcbus */ + //clocks = <&clkc CLKID_VAPB_0>, + // <&clkc CLKID_SYS_CLK_VPU_INTR>, + // <&clkc CLKID_VPU0>, + // <&clkc CLKID_VPU1>, + // <&clkc CLKID_VPU>; + //clock-names = "vapb_clk", + // "vpu_intr_gate", + // "vpu_clk0", + // "vpu_clk1", + // "vpu_clk"; + //clk_level = <7>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ + }; + + meson_uvm{ + compatible = "amlogic, meson_uvm"; + status = "disabled"; + }; + + meson_videotunnel{ + compatible = "amlogic, meson_videotunnel"; + status = "disabled"; + }; + + video_composer { + compatible = "amlogic, video_composer"; + dev_name = "video_composer"; + status = "disabled"; + }; + + rdma{ + compatible = "amlogic, meson-t3, rdma"; + status = "disabled"; + interrupts = ; + interrupt-names = "rdma"; + /* after sc2 */ + reset-names = "rdma"; + resets = <&reset RESET_RDMA>; + rdma_table_page_count = <16>; + }; + + dsc: dsc { + compatible = "amlogic, dsc-s5"; + status = "disabled"; + reg = <0x0 0xfe0be000 0x0 0x80>; + }; + + vclk_serve: vclk_serve { + compatible = "amlogic, vclk_serve"; + status = "disabled"; + reg = <0x0 0xfe008000 0x0 0x300 /* ana reg */ + 0x0 0xfe000000 0x0 0xc00>; /* clk reg */ + }; + + vout_mux: vout_mux { + compatible = "amlogic, vout_mux-s5"; + status = "disabled"; + //clocks = <&clkc CLKID_FCLK_DIV5>, <&clkc CLKID_VIN_MEAS>; + //clock-names = "fclk_div5", "vdin_meas_clk"; + }; + + vout: vout { + compatible = "amlogic, vout"; + status = "disabled"; + }; + + dummy_venc: dummy_venc { + compatible = "amlogic, dummy_venc_s5"; + status = "okay"; + }; + + ir: ir@8000 { + compatible = "amlogic, meson-ir"; + reg = <0x0 0xfe084040 0x0 0x44>, + <0x0 0xfe084000 0x0 0x20>; + status = "disable"; + protocol = ; + interrupts = ; + map = <&custom_maps>; + max_frame_time = <200>; + }; + + gpu_tsensor: gpu_tsensor@fe094000 { + compatible = "amlogic, r1p1-tsensor"; + status = "disabled"; + reg = <0x0 0xfe094000 0x0 0x50>; + tsensor_id = <2>; + cal_type = <0x11>; + cal_coeff = <324 424 3159 9411>; + rtemp = <115000>; + interrupts = ; + //clocks = <&clkc CLKID_TS_CLK>; + //clock-names = "ts_comp"; + #thermal-sensor-cells = <1>; + power-domains = <&pwrdm PDID_S5_MALI_TOP>; + reset-names = "ts_rst"; + resets = <&reset RESET_TS_GPU>; + }; + + a55_tsensor: a55_tsensor@fe022000 { + compatible = "amlogic, r1p1-tsensor"; + status = "disabled"; + reg = <0x0 0xfe022000 0x0 0x50>; + tsensor_id = <1>; + cal_type = <0x11>; + cal_coeff = <324 424 3159 9411>; + rtemp = <115000>; + interrupts = ; + //clocks = <&clkc CLKID_TS_CLK>; + //clock-names = "ts_comp"; + #thermal-sensor-cells = <1>; + reset-names = "ts_rst"; + resets = <&reset RESET_TS_A55>; + }; + + vpu_tsensor: vpu_tsensor@fe0a2000 { + compatible = "amlogic, r1p1-tsensor"; + status = "disabled"; + reg = <0x0 0xfe0a2000 0x0 0x50>; + tsensor_id = <3>; + cal_type = <0x11>; + cal_coeff = <324 424 3159 9411>; + rtemp = <115000>; + interrupts = ; + //clocks = <&clkc CLKID_TS_CLK>; + //clock-names = "ts_comp"; + #thermal-sensor-cells = <1>; + reset-names = "ts_rst"; + resets = <&reset RESET_TS_VPU>; + }; + + dos_tsensor: dos_tsensor@fe0a4000 { + compatible = "amlogic, r1p1-tsensor"; + status = "disabled"; + reg = <0x0 0xfe0a4000 0x0 0x50>; + tsensor_id = <4>; + cal_type = <0x11>; + cal_coeff = <324 424 3159 9411>; + rtemp = <115000>; + interrupts = ; + //clocks = <&clkc CLKID_TS_CLK>; + //clock-names = "ts_comp"; + #thermal-sensor-cells = <1>; + power-domains = <&pwrdm PDID_S5_DOS_TOP_WRAP>; + reset-names = "ts_rst"; + resets = <&reset RESET_TS_DOS>; + }; + + nna_tsensor: nna_tsensor@fe096000 { + compatible = "amlogic, r1p1-tsensor"; + status = "disabled"; + reg = <0x0 0xfe096000 0x0 0x50>; + tsensor_id = <5>; + cal_type = <0x11>; + cal_coeff = <324 424 3159 9411>; + rtemp = <115000>; + interrupts = ; + //clocks = <&clkc CLKID_TS_CLK>; + //clock-names = "ts_comp"; + #thermal-sensor-cells = <1>; + power-domains = <&pwrdm PDID_S5_NNA_4T>; + reset-names = "ts_rst"; + resets = <&reset RESET_TS_NNA>; + }; + + meson_cooldev: meson-cooldev@0 { + status = "disabled"; + compatible = "amlogic, meson-cooldev"; + cooling_devices { + cpucore_cool_cluster0 { + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + cpucore_cool_cluster1 { + cluster_id = <1>; + node_name = "cpucore_cool1"; + device_type = "cpucore"; + }; + gpufreq_cool { + dyn_coeff = <358>; + node_name = "valhall"; + device_type = "gpufreq"; + }; + gpucore_cool { + node_name = "gpucore_cooldev"; + device_type = "gpucore"; + }; + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; + }; + cpucore_cool1:cpucore_cool1 { + #cooling-cells = <2>; + }; + gpucore_cooldev:gpucore_cooldev { + #cooling-cells = <2>; + }; + };/*meson cooling devices end*/ + + thermal-zones { + gpu_thermal: gpu_thermal { + status = "disabled"; + polling-delay = <2000>; + polling-delay-passive = <500>; + sustainable-power = <5160>; + thermal-sensors = <&gpu_tsensor 1>; + trips { + gpuswitch_on: trip-point@0 { + temperature = <80000>; + hysteresis = <5000>; + type = "passive"; + }; + gpucontrol: trip-point@1 { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + gpucritical: trip-point@3 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + cooling-maps { + gpufreq_cooling_map { + trip = <&gpucontrol>; + cooling-device = <&gpu 0 3>; + contribution = <1024>; + }; + }; + }; + soc_thermal: soc_thermal { + status = "disabled"; + polling-delay = <2000>; + polling-delay-passive = <1000>; + sustainable-power = <960>; + thermal-sensors = <&a55_tsensor 0>; + trips { + a55switch_on: trip-point@0 { + temperature = <80000>; + hysteresis = <5000>; + type = "passive"; + }; + a55control: trip-point@1 { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + a55hot: trip-point@2 { + temperature = <100000>; + hysteresis = <5000>; + type = "hot"; + }; + a55critical: trip-point@3 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + cooling-maps { + cpucore_cooling_map { + trip = <&a55hot>; + cooling-device = <&cpucore_cool0 0 2>; + contribution = <1024>; + }; + cpufreq_cooling_map1 { + trip = <&a55control>; + cooling-device = <&CPU0 0 8>; + contribution = <1024>; + }; + cpufreq_cooling_map2 { + trip = <&a55control>; + cooling-device = <&CPU4 0 8>; + contribution = <1024>; + }; + }; + }; + vpu_thermal: vpu_thermal { + status = "disabled"; + polling-delay = <2000>; + polling-delay-passive = <1000>; + sustainable-power = <400>; + thermal-sensors = <&vpu_tsensor 2>; + trips { + vpuswitch_on: trip-point@0 { + temperature = <80000>; + hysteresis = <5000>; + type = "passive"; + }; + vpucontrol: trip-point@1 { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + vpucritical: trip-point@2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + dos_thermal: dos_thermal { + status = "disabled"; + polling-delay = <2000>; + polling-delay-passive = <1000>; + sustainable-power = <400>; + thermal-sensors = <&dos_tsensor 3>; + trips { + dosswitch_on: trip-point@0 { + temperature = <80000>; + hysteresis = <5000>; + type = "passive"; + }; + doscontrol: trip-point@1 { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + doscritical: trip-point@2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + nna_thermal: nna_thermal { + status = "disabled"; + polling-delay = <2000>; + polling-delay-passive = <1000>; + sustainable-power = <3550>; + thermal-sensors = <&nna_tsensor 4>; + trips { + nnaswitch_on: trip-point@0 { + temperature = <80000>; + hysteresis = <5000>; + type = "passive"; + }; + nnacontrol: trip-point@1 { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + nnacritical: trip-point@2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + };/*thermal zone end*/ + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_cma_reserved + &ion_fb_reserved + &ion_secure_reserved>; + status = "disabled"; + }; + + fb: fb { + compatible = "amlogic, fb-s5"; + memory-region = <&logo_reserved>; + status = "disabled"; + interrupts = ; + interrupt-names = "viu-vsync", "rdma"; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 2160 32>; + /*1920*1080*4*3 = 0x17BB000*/ + }; + + irblaster: meson-irblaster@fe08410c { + compatible = "amlogic, meson_irblaster"; + status = "disabled"; + reg = <0x0 0xfe08410c 0x0 0x10>; + #irblaster-cells = <2>; + interrupts = ; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0: vdin0 {/*common define*/ + compatible = "amlogic, vdin-s5"; + dev_name = "vdin0"; + status = "disabled"; + /*memory-region = <&vdin0_cma_reserved>;*/ + reserve-iomap = "true"; + flag_cma = <0x101>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + * onebuffer: + * worst case:(4096*2160*3 + 2M(afbce issue)) = 27.5M + * dw:960x540x3 = 1.5M + * total size:(27.5+1.5)x buffernumber + */ + /*cma_size = <174>;*/ + /*frame_buff_num = <6>;*/ + interrupts = <0 210 1 /* vdin0 vsync */ + 0 214 1 /* vdin1 write down*/ + /*0 206 1*/ /* vpu crash */ + /*0 213 1*/>; /* vdin0 write down*/ + interrupt-names = "vsync_int", + "mif2_meta_wr_done_int" + /*"vpu_crash_int",*/ + /*"write_done_int"*/; + rdma-irq = <2>; +// clocks = <&clkc CLKID_FCLK_DIV5>, <&clkc CLKID_VDIN_MEAS_GATE>; +// clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <0>; + /*vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + * bit4:support yuv422 10bit full pack mode (from txl new add) + * bit8:use 8bit at 4k_50/60hz_10bit + * bit9:use 10bit at 4k_50/60hz_10bit + * bit10: support 10bit when double write + */ + tv_bit_mode = <0x215>; + /* afbce_bit_mode: (amlogic frame buff compression encoder) + * bit0 -- enable afbce + * bit1 -- enable afbce compression-lossy + * bit4 -- afbce for 4k + * bit5 -- afbce for 1080p + * bit6 -- afbce for 720p + * bit7 -- afbce for smaller resolution + */ + afbce_bit_mode = <0x31>; + /* urgent_en; */ + double_write_en; + /* vdin v4l2 */ + v4l_support_en = <0>; + v4l_vd_num = <70>; + /* v4l2 capability */ + driver = "vdinvideo"; + bus_info = "vdin0 v4l2"; + version = <0x20220120>; + /* fe_ports refer to tvin.h */ + fe_ports = <0x00001001 /* CVBS1 */ + 0x00004000 /* HDMI0 */ + 0x00004001 /* HDMI1 */ + 0x00004002>; /* HDMI2 */ + /* vdin v4l2 end */ + }; + + vdin1: vdin1 {/*common define*/ + compatible = "amlogic, vdin-s5"; + dev_name = "vdin1"; + status = "disabled"; + reserve-iomap = "true"; + /*memory-region = <&vdin1_cma_reserved>;*/ + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 117 1>,<0 120 1>; + interrupt-names = "vsync_int","write_done_int"; + rdma-irq = <4>; +// clocks = <&clock CLK_FPLL_DIV5>, +// <&clock CLK_VDIN_MEAS_CLK>; +// clock-names = "fclk_div5", "cts_vdin_meas_clk"; + + vdin_id = <1>; + tv_bit_mode = <0x15>; + /* vdin v4l2 */ + v4l_support_en = <0>; + v4l_vd_num = <71>; + /* v4l2 capability */ + driver = "vdinvideo"; + bus_info = "vdin1 v4l2"; + version = <0x20220120>; + /* fe_ports refer to tvin.h */ + fe_ports = <0x0000a002 /* WB0_VD1 */ + 0x0000a003 /* WB0_VD2 */ + 0x0000a004 /* WB0_OSD1 */ + 0x0000a005 /* WB0_OSD2 */ + 0x0000a006 /* WB0_VPP */ + 0x0000a007 /* WB0_VDIN_BIST */ + 0x0000a008>; /* WB0_POST_BLEND */ + /* vdin v4l2 end */ + }; + + amlvecm: amlvecm { + compatible = "amlogic, vecm-s5"; + status = "disable"; + dev_name = "aml_vecm"; + /*status = "okay";*/ + /*gamma_en = <1>;*/ /*1:enable ;0:disable*/ + /*wb_en = <1>;*/ /*1:enable ;0:disable*/ + /*cm_en = <1>;*/ /*1:enable ;0:disable*/ + /*wb_sel = <0>;*/ /*1:mtx ;0:gainoff*/ + /*vlock_en = <1>;*/ /*1:enable;0:disable*/ + /*vlock_mode = <0x8>;*/ + /* vlock work mode: + *bit0:auto ENC + *bit1:auto PLL + *bit2:manual PLL + *bit3:manual ENC + *bit4:manual soft ENC + *bit5:manual MIX PLL ENC + */ + /* vlock_pll_m_limit = <1>;*/ + /* vlock_line_limit = <2>;*/ +// clocks = <&clkc CLKID_VID_LOCK>; +// clock-names = "cts_vid_lock_clk"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom-s5"; + dev_name = "amvideom"; + status = "disabled"; + interrupts = ; + interrupt-names = "vsync"; + }; + + vpu_security { + compatible = "amlogic, meson-s5, vpu_security"; + dev_name = "amlogic-vpu-security"; + status = "disabled"; + interrupts = ; + interrupt-names = "vpu_security"; + }; + + dmx_aucpu: aucpu { + compatible = "amlogic, aucpu"; + dev_name = "aml_aucpu"; + status = "disabled"; + interrupts = <0 77 1>; + interrupt-names = "aucpu_irq"; + #address-cells=<2>; + #size-cells=<2>; + ranges; + io_reg_base{ + reg = <0x0 0xfe09e080 0x0 0x100>; + }; + }; + + ge2d { + compatible = "amlogic, ge2d-s5"; + status = "disabled"; + interrupts = ; + interrupt-names = "ge2d"; + //clocks = <&clkc CLKID_VAPB_0>, + // <&clkc CLKID_GE2D>; + //clock-names = "clk_vapb_0", + // "clk_ge2d_gate"; + reg = <0x0 0xff840000 0x0 0x2000>; + power-domains = <&pwrdm PDID_S5_GE2D>; + }; + + vicp { + compatible = "amlogic, vicp"; + dev_name = "vicp"; + status = "disabled"; + interrupts = , + , + ; + interrupt-names = "vicp_err", "vicp_rdma", "vicp_proc"; + //clocks = <&clkc CLKID_VAPB_0>, + // <&clkc CLKID_CMPR>; + //clock-names = "clk_vapb_0", + // "clk_vicp_gate"; + reg = <0x0 0xfe03e000 0x0 0xe34>; + power-domains = <&pwrdm PDID_S5_VICP>; + }; + + aml_bt: aml_bt { + compatible = "amlogic, aml-bt"; + status = "disabled"; + }; + + aml_wifi: aml_wifi { + compatible = "amlogic, aml-wifi"; + status = "disabled"; + irq_trigger_type = "GPIO_IRQ_LOW"; + dhd_static_buf; + //pinctrl-0 = <&pwm_e_pins>; + //pinctrl-names = "default"; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef 1 30550 0>; + duty-cycle = <15270>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef 3 30500 0>; + duty-cycle = <15250>; + times = <12>; + }; + }; + + gdc { + #address-cells=<2>; + #size-cells=<2>; + status = "disabled"; + compatible = "amlogic, arm-gdc"; + reg = <0 0xfe08e000 0 0x0000100>; + interrupts = ; + interrupt-names = "gdc"; +// clocks = <&clkc CLKID_GDCCLK_0>, +// <&clkc CLKID_GDCCLK>, +// <&clkc CLKID_GDC_CLK>; +// clock-names = "mux_gate", "mux_sel", "clk_gate"; +// clk-rate = <800000000>; +// power-domains = <&pwrdm PDID_T7_GDC>; + }; + + amlgdc { + #address-cells=<2>; + #size-cells=<2>; + status = "disabled"; + compatible = "amlogic, aml-gdc-v2"; + reg = <0 0xfe040000 0 0x000015c>, + <0 0xfe03e000 0 0x000015c>, + <0 0xfe03c000 0 0x000015c>; + interrupts = , + , + ; + interrupt-names = "amlgdc", "amlgdc1", "amlgdc2"; +// clocks = <&clkc CLKID_DEWARPA>, +// <&clkc CLKID_DEWARPB>, +// <&clkc CLKID_DEWARPC>; +// clock-names = "clk_gate", +// "clk_gate1", +// "clk_gate2"; +// clk-rate = <800000000>; + //power-domains = <&pwrdm PDID_P1_DEWA>, + // <&pwrdm PDID_P1_DEWB>, + // <&pwrdm PDID_P1_DEWC>; + }; + + mhu_fifo: mhu@0 { + status = "disabled"; + compatible = "amlogic, meson_mhu_fifo"; + reg = <0x0 0xfe006000 0x0 0x1000>, /* mhu wr fifo */ + <0x0 0xfe00719C 0x0 0x80>, /* mhu set reg */ + <0x0 0xfe00721C 0x0 0x80>, /* mhu clr reg */ + <0x0 0xfe00729C 0x0 0x80>, /* mhu sts reg */ + <0x0 0xfe007044 0x0 0xc0>; /* mhu irqctrl reg */ + interrupts = <0 248 1>; /* irq top */ + mbox-irqmax = <64>; + mbox-irqctlr = <2>; + mbox-irqclr = <1>; + mbox-nums = <2>; + mbox-names = "ao_to_ap", + "ap_to_ao"; + //mboxes = <&mhu_fifo S5_AO2REE>, + //mhu_fifo <&mhu_fifo S5_REE2AO>; + mbox-id = <0x2 0x3>; + mbox-wr-rd = <1>; + #mbox-cells = <1>; + }; + + mbox_user: mbox-user@0 { + status = "disabled"; + compatible = "amlogic, meson-mbox-user"; + mbox-nums = <1>; + mbox-names = "ree2aocpu"; + //mboxes = <&mhu_fifo S5_REE2AO>; + mbox-dests = ; + }; + + aml_hwspinlock: hwlock { + status = "disabled"; + compatible = "amlogic, hwspinlock"; + syscon = <&aml_hwspinlock_regs 0 0x4>; + #hwlock-cells = <1>; + }; + + lut_dma:lut_dma { + compatible = "amlogic, meson-s5, lut_dma"; + status = "disabled"; + }; + + state_led:state_led { + compatible = "amlogic,state-led-aocpu"; + status = "disabled"; + }; + efuse: efuse{ + compatible = "amlogic, efuse"; + read_cmd = <0x82000030>; + write_cmd = <0x82000031>; + get_max_cmd = <0x82000033>; + mem_in_base_cmd = <0x82000020>; + mem_out_base_cmd = <0x82000021>; + efuse_pattern_size = <0x600>; + efuse_obj_cmd_status = <0x1>; + key = <&efusekey>; + clock-names = "efuse_clk"; + status = "disabled"; + }; + + efusekey:efusekey{ + status = "disabled"; + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + }; + + mfh: mfh { + compatible = "amlogic, mfh"; + #address-cells = <2>; + #size-cells = <2>; + memory-region = <&mfh_fw_reserved>; + //power-domains = <&pwrdm PDID_P1_M4A>, + // <&pwrdm PDID_P1_M4B>; + power-domain-names = "m4a-core","m4b-core"; +// clocks = <&clkc CLKID_M4_CLK_0>, +// <&clkc CLKID_M4_CLK_1>, +// <&clkc CLKID_M4_CLK>, +// <&clkc CLKID_M4_PLL>; +// clock-names = "m4_clk0", "m4_clk1", "m4_clk", "m4_pll"; + mfh-cnt = <2>; + mfh-addr-offset = <0x40000>; + mfh-name = "mfh_a", + "mfh_b"; + }; + + gpu_opp_table: gpu_opp_table { + compatible = "operating-points-v2"; + + opp-285 { + opp-hz = /bits/ 64 <285714281>; + opp-microvolt = <1150>; + }; + opp-400 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1150>; + }; + opp-500 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1150>; + }; + opp-666 { + opp-hz = /bits/ 64 <666666666>; + opp-microvolt = <1150>; + }; + opp-830 { + opp-hz = /bits/ 64 <830000000>; + opp-microvolt = <1150>; + }; + }; + +}; + +&periphs_pinctrl { + i2c0_pins1:i2c0_pins1 { + mux { + groups = "i2c0_scl_d", + "i2c0_sda_d"; + function = "i2c0"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + i2c0_pins2:i2c0_pins2 { + mux { + groups = "i2c0_scl_e", + "i2c0_sda_e"; + function = "i2c0"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + i2c1_pins1:i2c1_pins1 { + mux { + groups = "i2c1_scl_a", + "i2c1_sda_a"; + function = "i2c1"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + i2c1_pins2:i2c1_pins2 { + mux { + groups = "i2c1_scl_h2", + "i2c1_sda_h3"; + function = "i2c1"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + i2c1_pins3:i2c1_pins3 { + mux { + groups = "i2c1_scl_h6", + "i2c1_sda_h7"; + function = "i2c1"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + + i2c2_pins1:i2c2_pins1 { + mux { + groups = "i2c2_sda_a", + "i2c2_scl_a"; + function = "i2c2"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + i2c2_pins2:i2c2_pins2 { + mux { + groups = "i2c2_scl_t", + "i2c2_sda_t"; + function = "i2c2"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + i2c2_pins3:i2c2_pins3 { + mux { + groups = "i2c2_scl_x", + "i2c2_sda_x"; + function = "i2c2"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + i2c3_pins1:i2c3_pins1 { + mux { + groups = "i2c3_scl_h", + "i2c3_sda_h"; + function = "i2c3"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + i2c3_pins2:i2c3_pins2 { + mux { + groups = "i2c3_scl_t", + "i2c3_sda_t"; + function = "i2c3"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + i2c4_pins1:i2c4_pins1 { + mux { + groups = "i2c4_scl_e", + "i2c4_sda_e"; + function = "i2c4"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + i2c4_pins2:i2c4_pins2 { + mux { + groups = "i2c4_scl_t", + "i2c4_sda_t"; + function = "i2c4"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + i2c5_pins1:i2c5_pins1 { + mux { + groups = "i2c5_scl_z", + "i2c5_sda_z"; + function = "i2c5"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + i2c5_pins2:i2c5_pins2 { + mux { + groups = "i2c5_scl_t", + "i2c5_sda_t"; + function = "i2c5"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + i2c5_pins3:i2c5_pins3 { + mux { + groups = "i2c5_sda_a", + "i2c5_scl_a"; + function = "i2c5"; + drive-strength-microamp = <3000>; + bias-disable; + }; + }; + + a_uart_pins1:a_uart1 { + mux { + groups = "uart_a_tx_d", + "uart_a_rx_d"; + function = "uart_a"; + }; + }; + + a_uart_pins2:a_uart2 { + mux { + groups = "uart_a_tx_c", + "uart_a_rx_c"; + function = "uart_a"; + }; + }; + + b_uart_pins:b_uart { + mux { + groups = "uart_b_tx", + "uart_b_rx", + "uart_b_cts", + "uart_b_rts"; + bias-pull-up; + output-high; + function = "uart_b"; + }; + }; + + c_uart_pins1:c_uart1 { + mux { + groups = "uart_c_tx_a", + "uart_c_rx_a"; + function = "uart_c"; + }; + }; + + c_uart_pins2:c_uart2 { + mux { + groups = "uart_c_tx_d", + "uart_c_rx_d"; + function = "uart_c"; + }; + }; + + c_uart_pins3:c_uart3 { + mux { + groups = "uart_c_tx_h", + "uart_c_rx_h", + "uart_c_cts_h", + "uart_c_rts_h"; + bias-pull-up; + output-high; + function = "uart_c"; + }; + }; + + d_uart_pins:d_uart { + mux { + groups = "uart_d_tx", + "uart_d_rx"; + function = "uart_d"; + }; + }; + + e_uart_pins:e_uart { + mux { + groups = "uart_e_tx", + "uart_e_rx"; + function = "uart_e"; + }; + }; + + f_uart_pins:f_uart { + mux { + groups = "uart_f_tx", + "uart_f_rx"; + function = "uart_f"; + }; + }; + + /* sdemmc portB */ + sd_to_ao_uart_clr_pins: sd_to_ao_uart_clr_pins { + mux { + groups = "GPIOD_0", + "GPIOD_1"; + function = "gpio_periphs"; + }; + }; + + sdcard_pins: sdcard_pins { + mux { + groups = "sdcard_d0", + "sdcard_d1", + "sdcard_d2", + "sdcard_d3", + "sdcard_clk", + "sdcard_cmd"; + function = "sdcard"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + + ao_to_sd_uart_pins: ao_to_sd_uart_pins { + mux { + groups = "uart_a_tx_c", + "uart_a_rx_c"; + function = "uart_a"; + bias-pull-up; + input-enable; + }; + }; + + ao_uart_pins: ao_uart_pins { + mux { + groups = "uart_a_tx_d", + "uart_a_rx_d"; + function = "uart_a"; + bias-pull-up; + input-enable; + }; + }; + + sd_clr_all_pins: sd_clr_all_pins { + mux { + groups = "GPIOC_0", + "GPIOC_1", + "GPIOC_2", + "GPIOC_3", + "GPIOC_5"; + function = "gpio_periphs"; + output-high; + }; + mux1 { + groups = "GPIOC_4"; + function = "gpio_periphs"; + output-low; + }; + }; + + sd_clr_noall_pins: sd_clr_noall_pins { + mux { + groups = "GPIOC_0", + "GPIOC_1", + "GPIOC_4", + "GPIOC_5"; + function = "gpio_periphs"; + output-high; + }; + }; + + sd_1bit_pins: sd_1bit_pins { + mux { + groups = "sdcard_d0", + "sdcard_clk", + "sdcard_cmd"; + function = "sdcard"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + + sdcard_clk_gate_pins: sdcard_clk_gate_pins { + mux { + groups = "GPIOC_4"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + sd_iso7816_pins:sd_iso7816_pins { + mux { + groups = "iso7816_clk_z", + "iso7816_data_z"; + function = "iso7816"; + input-enable; + bias-pull-down; + }; + }; + + /* sdio port A */ + sdio_pins: sdio { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_clk", + "sdio_cmd"; + function = "sdio"; + //bias-disable; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + + sdio_clk_gate_pins: sdio_clk_gate { + mux { + groups = "GPIOX_4"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + hdmitx_hpd: hdmitx_hpd { + mux { + groups = "hdmitx_hpd_in"; + function = "hdmitx"; + bias-disable; + }; + }; + + hdmitx_hpd_gpio: hdmitx_hpd_gpio { + mux { + groups = "hdmitx_hpd_in"; + function = "gpio_periphs"; + bias-disable; + }; + }; + + hdmitx_ddc: hdmitx_ddc { + mux { + groups = "hdmitx_sda", + "hdmitx_sck"; + function = "hdmitx"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + hdmirx_a_mux:hdmirx_a_mux { + mux { + groups = "hdmirx_a_hpd", + "hdmirx_a_det", + "hdmirx_a_sda", + "hdmirx_a_sck"; + function = "hdmirx_a"; + }; + }; + + hdmirx_b_mux:hdmirx_b_mux { + mux { + groups = "hdmirx_b_hpd", + "hdmirx_b_det", + "hdmirx_b_sda", + "hdmirx_b_sck"; + function = "hdmirx_b"; + }; + }; + + hdmirx_c_mux:hdmirx_c_mux { + mux { + groups = "hdmirx_c_hpd", + "hdmirx_c_det", + "hdmirx_c_sda", + "hdmirx_c_sck"; + function = "hdmirx_c"; + }; + }; + + cec_a: cec_a { + mux { + groups = "cec_a"; + function = "cec_a"; + }; + }; + + cec_b: cec_b { + mux { + groups = "cec_b_h"; + function = "cec_b"; + }; + }; + + jtag_a_pins: jtag_a_pin { + mux { + groups = "jtag_a_tdi", + "jtag_a_tdo", + "jtag_a_clk", + "jtag_a_tms"; + function = "jtag_a"; + }; + }; + + jtag_b_pins: jtag_b_pin { + mux { + groups = "jtag_b_tdi", + "jtag_b_tdo", + "jtag_b_clk", + "jtag_b_tms"; + function = "jtag_b"; + }; + }; + + pwm_a_pins1: pwm_a_pins1 { + mux { + groups = "pwm_a_e"; + function = "pwm_a"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_a_pins2: pwm_a_pins2 { + mux { + groups = "pwm_a_x"; + function = "pwm_a"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_b_pins1: pwm_b_pins1 { + mux { + groups = "pwm_b_e"; + function = "pwm_b"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_b_pins2: pwm_b_pins2 { + mux { + groups = "pwm_b_h"; + function = "pwm_b"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_c_pins1: pwm_c_pins1 { + mux { + groups = "pwm_c_e"; + function = "pwm_c"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_c_pins2: pwm_c_pins2 { + mux { + groups = "pwm_c_c"; + function = "pwm_c"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_d_pins1: pwm_d_pins1 { + mux { + groups = "pwm_d_d"; + function = "pwm_d"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_d_pins2: pwm_d_pins2 { + mux { + groups = "pwm_d_e"; + function = "pwm_d"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_e_pins: pwm_e_pins { + mux { + groups = "pwm_e"; + function = "pwm_e"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_f_pins: pwm_f_pins { + mux { + groups = "pwm_f"; + function = "pwm_f"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_g_pins1: pwm_g_pins1 { + mux { + groups = "pwm_g_d"; + function = "pwm_g"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_g_pins2: pwm_g_pins2 { + mux { + groups = "pwm_g_x"; + function = "pwm_g"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_h_pins1: pwm_h_pins1 { + mux { + groups = "pwm_h_d"; + function = "pwm_h"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_h_pins2: pwm_h_pins2 { + mux { + groups = "pwm_h_t"; + function = "pwm_h"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_i_pins1: pwm_i_pins1 { + mux { + groups = "pwm_i_d"; + function = "pwm_i"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_i_pins2: pwm_i_pins2 { + mux { + groups = "pwm_i_t"; + function = "pwm_i"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_j_pins1: pwm_j_pins1 { + mux { + groups = "pwm_j_d"; + function = "pwm_j"; + drive-strength-microamp = <3000>; + }; + }; + + pwm_j_pins2: pwm_j_pins2 { + mux { + groups = "pwm_j_t"; + function = "pwm_j"; + drive-strength-microamp = <3000>; + }; + }; + + remote_pins: remote_pin { + mux { + groups = "remote_in_d"; + function = "remote_in"; + bias-disable; + }; + }; + + spicc0_pins_c: spicc0_pins_c { + mux { + groups = "spi_a_mosi_c", + "spi_a_miso_c", + "spi_a_clk_c"; + function = "spi_a"; + drive-strength-microamp = <2000>; + }; + }; + + spicc0_cs_pins_c: spicc0_cs_pins_c { + mux { + groups = "spi_a_ss0_c"; //GPIOC_2 + function = "spi_a"; + drive-strength-microamp = <2000>; + }; + }; + + spicc0_pins_t: spicc0_pins_t { + mux { + groups = "spi_a_mosi_t", + "spi_a_miso_t", + "spi_a_sclk_t"; + function = "spi_a"; + drive-strength-microamp = <2000>; + }; + }; + + spicc0_cs_pins_t: spicc0_cs_pins_t { + mux { + groups = "spi_a_ss0_t"; //GPIOT_4 + function = "spi_a"; + drive-strength-microamp = <2000>; + }; + }; + + spicc1_pins: spicc1_pins { + mux { + groups = "spi_b_mosi", + "spi_b_miso", + "spi_b_sclk"; + function = "spi_b"; + drive-strength-microamp = <2000>; + }; + }; + + spicc1_cs_pins: spicc1_cs_pins { + mux { + groups = "spi_b_ss0"; //GPIOH_6 + function = "spi_b"; + drive-strength-microamp = <2000>; + }; + }; + + spicc2_pins_a: spicc2_pins_a { + mux { + groups = "spi_c_mosi_a", + "spi_c_miso_a", + "spi_c_sclk_a"; + function = "spi_c"; + drive-strength-microamp = <2000>; + }; + }; + + spicc2_cs_pins_a: spicc2_cs_pins_a { + mux { + groups = "spi_c_ss0_a"; //GPIOA_2 + function = "spi_c"; + drive-strength-microamp = <2000>; + }; + }; + + spicc2_pins_x: spicc2_pins_x { + mux { + groups = "spi_c_mosi_x", + "spi_c_miso_x", + "spi_c_clk_x"; + function = "spi_c"; + drive-strength-microamp = <2000>; + }; + }; + + spicc2_cs_pins_x: spicc2_cs_pins_x { + mux { + groups = "spi_c_ss0_x"; //GPIOX_2 + function = "spi_c"; + drive-strength-microamp = <2000>; + }; + }; + + irblaster_pins1:irblaster_pin1 { + mux { + groups = "remote_out_d4"; + function = "remote_out"; + }; + }; + + irblaster_pins2:irblaster_pin2 { + mux { + groups = "remote_out_d6"; + function = "remote_out"; + }; + }; + + spdifout_d: spdifout_d { + mux { /* GPIOD_8 */ + groups = "spdif_out_d"; + function = "spdif_out"; + }; + }; + + spdifout_d_mute: spdifout_d_mute { + mux { /* GPIOD_8 */ + groups = "GPIOD_8"; + function = "gpio_periphs"; + output-low; + }; + }; + + spdifout_t: spdifout_t { + mux { /* GPIOT_3 */ + groups = "spdif_out_t"; + function = "spdif_out"; + }; + }; + + spdifout_t_mute: spdifout_t_mute { + mux { /* GPIOT_3 */ + groups = "GPIOT_3"; + function = "gpio_periphs"; + output-low; + }; + }; + + spdifin_d: spdifin_d { + mux {/* GPIOD_9 */ + groups = "spdif_in_d"; + function = "spdif_in"; + }; + }; + + spdifin_t: spdifin_t { + mux {/* GPIOT_4 */ + groups = "spdif_in_t"; + function = "spdif_in"; + }; + }; + mclk_0_pins: mclk_0_pin { + mux { /* GPIOT_14 */ + groups = "mclk_0"; + function = "mclk"; + }; + }; + mclk_1_pins: mclk_1_pin { + mux { /* GPIOT_19 */ + groups = "mclk_1"; + function = "mclk"; + }; + }; + + mclk_2_pins: mclk_2_pin { + mux { /* GPIOT_K8 */ + groups = "mclk_2"; + function = "mclk"; + }; + }; + + mclk_3_pins: mclk_3_pin { + mux { /* GPIOT_W0 */ + groups = "mclk_3_w"; + function = "mclk"; + }; + }; + lcd_vbyone_a_pins: lcd_vbyone_a_pin { + mux { + groups = "vx1_a_htpdn","vx1_a_lockn"; + function = "vx1_a"; + }; + }; + + lcd_vbyone_b_pins: lcd_vbyone_b_pin { + mux { + groups = "vx1_b_htpdn","vx1_b_lockn"; + function = "vx1_b"; + }; + }; + + lcd_edp_a_pins: lcd_edp_a_pin { + mux { + groups = "edp_a_hpd"; + function = "edp_a"; + }; + }; + + lcd_edp_b_pins: lcd_edp_b_pin { + mux { + groups = "edp_b_hpd"; + function = "edp_b"; + }; + }; + + eth_pins: eth { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rgmii_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_txen", + "eth_txd0", + "eth_txd1"; + function = "eth"; + drive-strength-microamp = <4000>; + bias-disable; + }; + }; + + eth_rgmii_pins: eth-rgmii { + mux { + groups = "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_rgmii_tx_clk", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + drive-strength-microamp = <4000>; + bias-disable; + }; + }; + + pcieck_0_pins: pcieck_0_pin { + mux { + /* GPIOT_23 */ + groups = "pcieck_b_reqn"; + function = "pcieck"; + }; + }; + + pcieck_1_pins: pcieck_1_pin { + mux { + /* GPIOX_19 */ + groups = "pcieck_c_reqn"; + function = "pcieck"; + }; + }; +}; + +&storage_pinctrl { + emmc_pins: emmc { + mux-0 { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + mux-1 { + groups = "emmc_clk"; + function = "emmc"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + emmc_ds_pins: emmc-ds { + mux { + groups = "emmc_nand_ds"; + function = "emmc"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "GPIOB_8"; + function = "gpio_storage"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + spifc_all_pins: spifc_all_pins { + mux { + groups = "spif_hold", + "spif_mo", + "spif_mi", + "spif_clk", + "spif_wp", + "spif_cs"; + function = "spif"; + drive-strength-microamp = <3000>; + }; + }; +}; + +&gpu{ + status = "disabled"; + operating-points-v2 = <&gpu_opp_table>; + reg = <0 0xFE400000 0 0x04000>, /*mali APB bus base address*/ + <0 0xFE002000 0 0x01000>; /*reset register*/ + + interrupts = , + , + ; + interrupt-names = "GPU", "MMU", "JOB"; + power-domains = <&pwrdm PDID_S5_MALI_TOP>; + num_of_pp = <2>; + system-coherency = <31>; + //clocks = <&clkc CLKID_MALI>; + //clock-names = "gpu_mux"; + + /* + * Mali clocking is provided by two identical clock paths + * MALI_0 and MALI_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + */ + //assigned-clocks = <&clkc CLKID_MALI0_SEL>, + // <&clkc CLKID_MALI0>, + // <&clkc CLKID_MALI>; /* Glitch free mux */ + //assigned-clock-parents = <&clkc CLKID_SYS2_PLL>, + // <0>, /* Do Nothing */ + // <&clkc CLKID_MALI0>; + //assigned-clock-rates = <0>, /* Do Nothing */ + // <800000000>, + // <0>; /* Do Nothing */ + + tbl = <&dvfs250_cfg + &dvfs400_cfg + &dvfs500_cfg + &dvfs666_cfg + &dvfs800_cfg + &dvfs800_cfg>; + +// reset_cfg:reset_cfg { +// reg_level = <0x16>; +// reg_mask = <0x26>; +// reg_bit = <10>; +// }; + +}; + diff --git a/arch/arm64/boot/dts/amlogic/mesont3x_drm.dtsi b/arch/arm64/boot/dts/amlogic/mesont3x_drm.dtsi new file mode 100644 index 000000000..250c86269 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/mesont3x_drm.dtsi @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include +#include "mesont3x.dtsi" + +/ { + drm_amcvbsout: drm-amcvbsout { + status = "disabled"; + compatible = "amlogic, drm-cvbsout"; + dev_name = "meson-amcvbsout"; + ports { + port { + #address-cells = <1>; + #size-cells = <0>; + cvbs_to_drm: endpoint@0 { + reg = <0>; + remote-endpoint = <&drm_to_cvbs>; + }; + }; + }; + }; + + drm_vpu: drm-vpu@0xff800000 { + status = "disabled"; + compatible = "amlogic, meson-s5-vpu"; + memory-region = <&logo_reserved>; + osd_ver = /bits/ 8 ; + reg = <0x0 0xff800000 0x0 0x40000>; + reg-names = "vcbus"; + interrupts = , + ; + interrupt-names = "viu-vsync", "viu2-vsync"; + dma-coherent; + /*EXTERNAL port for driver outside of drm.*/ + connectors_dev: port@1 { + #address-cells = <1>; + #size-cells = <0>; + drm_to_hdmitx: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmitx_to_drm>; + }; + drm_to_cvbs: endpoint@1 { + reg = <1>; + remote-endpoint = <&cvbs_to_drm>; + }; + }; + }; + + drm_subsystem: drm-subsystem { + status = "okay"; + compatible = "amlogic, drm-subsystem"; + vpu_dma_mask = <1>; /* 0: <= 4G, 1: > 4G */ + ports = <&connectors_dev>; + fbdev_sizes = <1920 1080 1920 2160 32>; + max_fb_size = <1>; /** 0:1080p fb 1:4k fb */ + max_sizes = <8192 8192>; + osd_ver = /bits/ 8 ; + vfm_mode = <1>; /** 0:drm mode 1:composer mode */ + memory-region = <&logo_reserved>; + crtc_masks = <3 7 1>; /*for encoder: 0:hdmi 1:lcd 2:cvbs*/ + crtcmask_of_osd = <0 0 1 2>; /* indicate the crtc mask of osd plane */ + crtcmask_of_video = <0 1 2>; /* indicate the crtc mask of video plane */ + logo_skip = <0>; + + vpu_topology: vpu_topology { + vpu_blocks { + osd1_block: block@0 { + id = /bits/ 8 ; + index = /bits/ 8 <0>; + type = /bits/ 8 <0>; + block_name = "osd1_block"; + num_in_links = /bits/ 8 <0x0>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &afbc1_block>; + }; + osd3_block: block@1 { + id = /bits/ 8 ; + index = /bits/ 8 <2>; + type = /bits/ 8 <0>; + block_name = "osd3_block"; + num_in_links = /bits/ 8 <0x0>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &afbc2_block>; + }; + afbc1_block: block@2 { + id = /bits/ 8 ; + index = /bits/ 8 <0>; + type = /bits/ 8 <1>; + block_name = "afbc1_block"; + num_in_links = /bits/ 8 <0x1>; + in_links = <0 &osd1_block>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &scaler1_block>; + }; + afbc2_block: block@3 { + id = /bits/ 8 ; + index = /bits/ 8 <1>; + type = /bits/ 8 <1>; + block_name = "afbc2_block"; + num_in_links = /bits/ 8 <0x1>; + in_links = <0 &osd3_block>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &scaler3_block>; + }; + scaler1_block: block@4 { + id = /bits/ 8 ; + index = /bits/ 8 <0>; + type = /bits/ 8 <2>; + block_name = "scaler1_block"; + num_in_links = /bits/ 8 <0x1>; + in_links = <0 &afbc1_block>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &hdr1_block>; + }; + scaler3_block: block@5 { + id = /bits/ 8 ; + index = /bits/ 8 <2>; + type = /bits/ 8 <2>; + block_name = "scaler3_block"; + num_in_links = /bits/ 8 <0x1>; + in_links = <0 &afbc2_block>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &hdr3_block>; + }; + hdr1_block: block@6 { + id = /bits/ 8 ; + index = /bits/ 8 <0>; + block_name = "hdr1_block"; + type = /bits/ 8 <4>; + num_in_links = /bits/ 8 <0x1>; + in_links = <0 &scaler1_block>; + num_out_links = /bits/ 8 <0x3>; + out_links = <0 &slice2ppc_block>, + <1 &osd_blend_block>, + <0 &vpp_postblend_block>; + }; + hdr3_block: block@7 { + id = /bits/ 8 ; + index = /bits/ 8 <2>; + block_name = "hdr3_block"; + type = /bits/ 8 <4>; + num_in_links = /bits/ 8 <0x1>; + in_links = <0 &scaler3_block>; + num_out_links = /bits/ 8 <0x3>; + out_links = <1 &slice2ppc_block>, + <3 &osd_blend_block>, + <0 &vpp_postblend_block>; + }; + slice2ppc_block: block@8 { + id = /bits/ 8 ; + index = /bits/ 8 <0>; + block_name = "slice2ppc_block"; + type = /bits/ 8 <8>; + num_in_links = /bits/ 8 <0x2>; + in_links = <1 &hdr1_block>, + <1 &hdr3_block>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &osd_blend_block>; + }; + osd_blend_block: block@9 { + id = /bits/ 8 ; + block_name = "osd_blend_block"; + type = /bits/ 8 <3>; + num_in_links = /bits/ 8 <0x3>; + in_links = <0 &slice2ppc_block>, + <0 &hdr1_block>, + <0 &hdr3_block>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &vpp_postblend_block>; + }; + vpp_postblend_block: block@10 { + id = /bits/ 8 ; + index = /bits/ 8 <0>; + block_name = "vpp_postblend_block"; + type = /bits/ 8 <6>; + num_in_links = /bits/ 8 <0x3>; + in_links = <0 &hdr1_block>, + <0 &hdr3_block>, + <0 &osd_blend_block>; + num_out_links = <0x0>; + }; + video1_block: block@11 { + id = /bits/ 8 ; + index = /bits/ 8 <0>; + type = /bits/ 8 <7>; + block_name = "video1_block"; + num_in_links = /bits/ 8 <0x0>; + num_out_links = /bits/ 8 <0x0>; + }; + video2_block: block@12 { + id = /bits/ 8 ; + index = /bits/ 8 <1>; + type = /bits/ 8 <7>; + block_name = "video2_block"; + num_in_links = /bits/ 8 <0x0>; + num_out_links = /bits/ 8 <0x0>; + }; + }; + }; + + vpu_hw_para: vpu_hw_para@0 { + osd_ver = /bits/ 8 ; + afbc_type = /bits/ 8 <0x2>; + has_deband = /bits/ 8 <0x1>; + has_lut = /bits/ 8 <0x1>; + has_rdma = /bits/ 8 <0x1>; + osd_fifo_len = /bits/ 8 <64>; + vpp_fifo_len = /bits/ 32 <0xfff>; + }; + }; +}; + +&amhdmitx { + ports { + port { + #address-cells = <1>; + #size-cells = <0>; + hdmitx_to_drm: endpoint@0 { + reg = <0>; + remote-endpoint = <&drm_to_hdmitx>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/t3x_pxp.dts b/arch/arm64/boot/dts/amlogic/t3x_pxp.dts new file mode 100644 index 000000000..24241ca3d --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/t3x_pxp.dts @@ -0,0 +1,2015 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "mesont3x.dtsi" +#include "partition_mbox_ab.dtsi" +#include "mesont3x_drm.dtsi" +#include + +/ { + model = "Amlogic"; + amlogic-dt-id = "t3x_pxp"; + compatible = "amlogic, t3x"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_B; + serial1 = &uart_A; + serial2 = &uart_C; + serial3 = &uart_D; + serial4 = &uart_E; + serial5 = &uart_F; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + spi3 = &spicc2; + tsensor0 = &a55_tsensor; + tsensor1 = &gpu_tsensor; + tsensor2 = &vpu_tsensor; + tsensor3 = &dos_tsensor; + tsensor4 = &nna_tsensor; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x00000000 0x00000000 0x00000000 0xE0000000 + 0x00000001 0x00000000 0x00000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + ramoops@0x08400000 { + compatible = "ramoops"; + reg = <0x0 0x08400000 0x0 0x00100000>; + record-size = <0x20000>; + console-size = <0x40000>; + ftrace-size = <0x80000>; + pmsg-size = <0x10000>; + bconsole-size = <0x10000>; + status = "disabled"; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + /*reusable;*/ + no-map; + alignment = <0x0 0x400000>; + reg = <0x0 0x05000000 0x0 0x400000>; + }; + + dsp_fw_reserved:linux,dsp_fw { + compatible = "shared-dma-pool"; + reusable; + //size = <0x0 0x1000000>; + size = <0x0 0x0>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x3f000000 0x0 0x1000000>; + }; + + vc9000e_reserved: linux,vc9000e { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x0>; + //size = <0x0 0x2000000>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x0 0x0 0xe0000000>; + linux,contiguous-region; + clear-map; + }; + + /*dsp_shm_reserved:linux,dsp_shm { */ + /* compatible = "dspshmem"; */ + /* reg = <0x0 0x40820000 0x0 0x80000>; */ + /* size = <0x80000>; */ + /*};*/ + + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x0>; + //size = <0x0 0x800000>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x3e800000 0x0 0x800000>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x0 0x0>; + //size = <0x0 0x70000000>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x0 0x0 0xe0000000>; + linux,contiguous-region; + clear-map; + }; + + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x0 0x0>; + //size = <0x0 0x400000>; + //size = <0x0 0x0>; + alignment = <0x0 0x400000>; + }; + + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0 0x0>; + }; + + camera_cma_reserved:linux,camera_cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x0>; + //size = <0x0 0xB000000>; + alignment = <0x0 0x400000>; + }; + + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x0>; + //size = <0x0 0x5000000>; + alignment = <0x0 0x400000>; + }; + + ion_fb_reserved:linux,ion-fb { + compatible = "shared-dma-pool"; + reusable; + /* 3840x2160x4x4 round up 4M align */ + size = <0x0 0x0>; + //size = <0x0 0x8400000>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x0 0x0 0xe0000000>; + }; + /* secure ion for gpu,advice size is 0x1c800000 */ + ion_secure_reserved:linux,ion-secure { + compatible = "amlogic, ion-secure-mem"; + no-map; + size = <0x0 0x0>; + alignment = <0x0 0x400000>; + }; + + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0 0x0>; + alignment = <0x0 0x100000>; + //no-map; + }; + + /* vdin0 CMA pool */ + /*vdin0_cma_reserved:linux,vdin0_cma {*/ + /* compatible = "shared-dma-pool";*/ + /* reusable;*/ + /* up to 1920x1080 yuv422 8bit and 5 buffers + * 1920x1080x2x5 = 20 M + */ + /* size = <0x0 0x01400000>;*/ + /* alignment = <0x0 0x400000>;*/ + /*};*/ + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* up to 1920x1080 yuv422 8bit and 5 buffers + * 1920x1080x2x5 = 20 M + */ + size = <0x0 0x0>; + //size = <0x0 0x01400000>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x0 0x0 0xe0000000>; + }; + + mfh_fw_reserved:linux,mfh_fw { + compatible = "amlogic, aml_mfh_reserve_mem"; + reusable; + size = <0x0 0x0>; + //size = <0x0 0x80000>; + alignment = <0x0 0x80000>; + alloc-ranges = <0x0 0x41000000 0x0 0x80000>; + }; + + pcie_dma_ops_mm:linux,pcie_dma_ops { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x0>; + //size = <0x0 0x5000000>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x0 0x0 0xe0000000>; + }; + }; + + smmu: aml_smmu { + compatible = "amlogic,smmu"; + status = "disabled"; + #iommu-cells = <1>; + memory-region = <&pcie_dma_ops_mm>; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "disabled"; + }; + + vc9000e_rev { + compatible = "vc9000e_rev"; + memory-region = <&vc9000e_reserved>; + dev_name = "vc9000e"; + status = "disabled"; + interrupts = ; + interrupt-names = "vc9000e_irq0", "vc9000e_irq1", "vc9000e_irq1"; + power-domains = <&pwrdm PDID_S5_VC9000E>; + //clock-names = "vers_sys_clk", "vers_core_clk", "vers_aclk"; + //clocks = <&clkc CLKID_SYS_CLK_VC9000E>, + // <&clkc CLKID_VC9000E_CORE>, + // <&clkc CLKID_VC9000E_AXI>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-sc2"; + status = "disabled"; + + /* clk path */ + /* 0:vid_pll vid2_clk */ + /* 1:gp0_pll vid2_clk */ + /* 2:vid_pll vid1_clk */ + /* 3:gp0_pll vid1_clk */ + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* tm2 */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + performance_revB_telecom = <0x1bf0 0x9 + 0x1b56 0x546 + 0x1b12 0x8080 + 0x1b05 0x9 + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + }; + + multi-di { + //status = "okay"; + /*************************************************** + * memory: default is 4 + * 0:use reserved; + * 1:use cma; + * 2:use cma as reserved + * 4:use codec mem + ***************************************************/ + //flag_cma = <4>;//t5d unsupport 4K,di 1CH need 42M + //memory-region = <&di_cma_reserved>; + /*************************************************** + * clock-range: + * default: <334 334> + ***************************************************/ + //clock-range = <334 334>; + /*************************************************** + * en_4k: t5d not support 4k + ***************************************************/ + en_4k = <0>; + keep_dec_vf = <2>; + po_fmt = <0>; + /*************************************************** + * post_nub: default is 11 (T7/T3/SC2/S4 new path) + * local 7*4075520 = 28 + * post 11*5222400 = 56 + ***************************************************/ + post_nub = <11>; + /*************************************************** + * 0:not support + * bit 0: for 4k + * bit 1: for 1080p + ***************************************************/ + alloc_sct = <0>; + /*************************************************** + * hf: default is 0 (T7/T3/SC2/S4 new path) + * 0:not enable; + * 1: enable + ***************************************************/ + //hf = <1>; + tb = <2>; + }; + + provisionkey { + compatible = "amlogic, provisionkey"; + status = "disabled"; + key-permit-default = "write"; + //new key not need add dts if started with KEY_PROVISION_ + KEY_PROVISION_XXX { }; + //test_my_added_keyname { }; + };//End provisionkey + + unifykey{ + compatible = "amlogic,unifykey"; + status = "disabled"; + unifykey-num = <19>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + unifykey-index-15= <&keysn_15>; + unifykey-index-16= <&keysn_16>; + unifykey-index-17= <&keysn_17>; + unifykey-index-18= <&keysn_18>; + unifykey-index-19= <&keysn_19>; + unifykey-index-20= <&keysn_20>; + unifykey-index-21= <&keysn_21>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "region_code"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_16:key_16{ + key-name = "netflix_mgkid"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_17:key_17{ + key-name = "attestationdevidbox";// attest dev id box + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_18:key_18{ + key-name = "oemkey"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_19:key_19{ + key-name = "lcd"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_20:key_20{ + key-name = "lcd_extern"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_21:key_21{ + key-name = "backlight"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + };//End unifykey + + pmic_osc: clock-pmic { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic_osc"; + }; + + hdmirx { + compatible = "amlogic, hdmirx_t7"; + #address-cells=<1>; + #size-cells=<1>; + /*memory-region = <&hdmirx_emp_cma_reserved>;*/ + status = "disabled"; + pinctrl-names = "hdmirx_pins"; + pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux + &hdmirx_c_mux>; + repeat = <0>; + //power-domains = <&pwrdm PDID_T7_HDMIRX>; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; +// clocks =<&clkc CLKID_HDMIRX_CFG>, +// <&clkc CLKID_HDMIRX_ACR>, +// <&clkc CLKID_HDMIRX_METER>, +// <&clkc CLKID_HDMIRX_2M>, +// <&clkc CLKID_HDMIRX_5M>, +// <&clkc CLKID_HDMIRX_HDCP>, +// <&xtal>, +// <&clkc CLKID_FCLK_DIV4>, +// <&clkc CLKID_FCLK_DIV5>; +// clock-names = "hdmirx_cfg_clk", +// "cts_hdmirx_acr_ref_clk", +// "cts_hdmirx_meter_clk", +// "cts_hdmirx_2m_clk", +// "cts_hdmirx_5m_clk", +// "cts_hdmirx_hdcp2x_eclk", +// "xtal", +// "fclk_div4", +// "fclk_div5"; + hdmirx_id = <0>; + en_4k_2_2k = <0>; + hpd_low_cec_off = <0>; + arc_port = <1>; + /* bit4: enable feature, bit3~0: port number */ + disable_port = <0x0>; + /* MAP_ADDR_MODULE_CBUS */ + /* MAP_ADDR_MODULE_HIU */ + /* MAP_ADDR_MODULE_HDMIRX_CAPB3 */ + /* MAP_ADDR_MODULE_SEC_AHB */ + /* MAP_ADDR_MODULE_SEC_AHB2 */ + /* MAP_ADDR_MODULE_APB4 */ + /* MAP_ADDR_MODULE_TOP */ + /* MAP_ADDR_MODULE_CLK_CTRL */ + reg = < 0x0 0x0 0x0 0x0 + 0x0 0xff63C000 0x0 0x2000 + 0x0 0xffe0d000 0x0 0x2000 + 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 + 0x0 0xfe398000 0x0 0x18000 + 0x0 0xfe000000 0x0 0x1fff>; + }; + + /* Audio Related start */ + auge_sound { + compatible = "amlogic, auge-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + /*avout mute gpio*/ + avout_mute-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_HIGH>; + spk_mute-gpios = <&gpio GPIOA_5 GPIO_ACTIVE_LOW>; + + interrupts = ; + interrupt-names = "audio_exception64"; + + status = "disabled"; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + /* master mode */ + bitclock-master = <&tdma>; + frame-master = <&tdma>; + /* slave mode */ + /* + * bitclock-master = <&tdmacodec>; + * frame-master = <&tdmacodec>; + */ + /* suffix-name, sync with android audio hal used for */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&tdma>; + dai-tdm-slot-tx-mask = + <1>; + dai-tdm-slot-rx-mask = + <1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + system-clock-frequency = <256000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + /* master mode */ + bitclock-master = <&tdmb>; + frame-master = <&tdmb>; + /* slave mode */ + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s2hdmi"; + cpu { + sound-dai = <&tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + /* + * dai-tdm-slot-tx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-rx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-num = <8>; + */ + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + /* master mode */ + bitclock-master = <&tdmc>; + frame-master = <&tdmc>; + /* slave mode */ + //bitclock-master = <&tdmccodec>; + //frame-master = <&tdmccodec>; + /* suffix-name, sync with android audio hal used for */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmccodec: codec { + sound-dai = <&amlogic_codec>; + }; + }; + aml-audio-card,dai-link@3 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + /* master mode */ + bitclock-master = <&tdmd>; + frame-master = <&tdmd>; + /* slave mode */ + /* suffix-name, sync with android audio hal used for */ + suffix-name = "alsaPORT-tdm-d"; + cpu { + sound-dai = <&tdmd>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmd_codec: codec { + sound-dai = <&amlogic_codec>; + }; + }; + aml-audio-card,dai-link@4 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm-builtinmic"; + cpu { + sound-dai = <&pdm>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal used for */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&spdifa>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + + /* spdif_b to hdmi, only playback */ + aml-audio-card,dai-link@6 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdifb"; + cpu { + sound-dai = <&spdifb>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + + aml-audio-card,dai-link@7 { + mclk-fs = <256>; + continuous-clock; + suffix-name = "alsaPORT-loopback"; + cpu { + sound-dai = <&loopbacka>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + + aml-audio-card,dai-link@8 { + mclk-fs = <256>; + suffix-name = "alsaPORT-earc"; + cpu { + sound-dai = <&earc>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + /* Audio Related end */ + + picdec { + compatible = "amlogic, picdec"; + status = "disabled"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "disabled"; + }; + + amdolby_vision { + compatible = "amlogic, dolby_vision_s5"; + dev_name = "aml_amdolby_vision_driver"; + status = "disabled"; + tv_mode = <0>;/*1:enable ;0:disable*/ + multi_core1 = <1>; + }; + + /* SMC */ + smartcard { + compatible = "amlogic,smartcard-sc2"; + dev_name = "smartcard"; + status = "disabled"; + + reg = <0x0 0xfe000000 0x0 0x480000>; + irq_trigger_type = "GPIO_IRQ_LOW"; + + reset_pin-gpios = <&gpio GPIOH_7 GPIO_ACTIVE_HIGH>; + detect_pin-gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; + enable_5v3v_pin-gpios = <&gpio GPIOT_11 GPIO_ACTIVE_HIGH>; + enable_pin-gpios = <&gpio GPIOT_12 GPIO_ACTIVE_HIGH>; + + interrupts = <0 174 1>; + interrupt-names = "smc0_irq"; + /* + *Smc clock source, if change this, + *you must adjust clk and divider in smartcard.c + */ + smc0_clock_source = <0>; + /*0: high voltage on detect pin indicates card in.*/ + smc0_det_invert = <0>; + smc0_5v3v_level = <0>; + /*Ordinarily,smartcard controller needs a enable pin.*/ + smc_need_enable_pin = "yes"; + reset_level = <0>; + smc0_enable_level = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_iso7816_pins>; +// clocks = <&clkc CLKID_SC_CLK_GATE>; +// clock-names = "smartcard"; + }; + + dvb-extern { + compatible = "amlogic, dvb-extern"; + dev_name = "dvb-extern"; + /*GPIOT-19 conflict with audio speaker */ + status = "disabled"; + + fe_num = <2>; + fe0_demod = "cxd2856"; + fe0_i2c_adap_id = <&i2c2>; + fe0_demod_i2c_addr = <0xD8>; + fe0_reset_value = <0>; + fe0_reset_gpio = <&gpio GPIOT_22 GPIO_ACTIVE_LOW>; + fe0_reset_dir = <0>; /* 0: out, 1: in. */ + //fe0_ant_poweron_value = <0>; + //fe0_ant_power_gpio = <&gpio GPIOT_18 GPIO_ACTIVE_HIGH>; + fe0_ts = <0>; + fe0_tuner0 = <0>; /* T/C */ + fe0_tuner1 = <1>; /* S */ + + fe1_demod = "cxd2856"; + fe1_i2c_adap_id = <&i2c2>; + fe1_demod_i2c_addr = <0xCA>; + fe1_reset_value = <0>; + fe1_reset_gpio = <&gpio GPIOT_22 GPIO_ACTIVE_LOW>; + fe1_reset_dir = <0>; /* 0: out, 1: in. */ + //fe1_ant_poweron_value = <0>; + //fe1_ant_power_gpio = <&gpio GPIOT_18 GPIO_ACTIVE_HIGH>; + fe1_ts = <1>; + fe1_tuner0 = <0>; /* T/C */ + fe1_tuner1 = <1>; /* S */ + + tuner_num = <2>; /* for extern demod use tuner */ + tuner0_name = "r836_tuner"; + tuner1_name = "av2018_tuner"; + }; + + dvb-demux { + compatible = "amlogic sc2, dvb-demux"; + dev_name = "dvb-demux"; + status = "disabled"; + + reg = <0x0 0xfe000000 0x0 0x480000>; + + dmxdev_num = <0x11>; + + tsn_from = "demod"; + + /*single demod setting */ + ts0_sid = <0x20>; + ts0 = "serial-4wire"; /* tsinA: serial-4wire, serial-3wire */ + ts0_control = <0x0>; + ts0_invert = <0>; + + ts1_sid = <0x21>; + ts1 = "serial-4wire"; + ts1_control = <0x0>; + ts1_invert = <0>; + + pinctrl-names = "s_ts0", "s_ts1"; + pinctrl-0 = <&dvb_s_ts0_pins>; + pinctrl-1 = <&dvb_s_ts1_pins>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "disabled"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "disabled"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "disabled"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + gpio_keypad{ + compatible = "amlogic, gpio_keypad"; + status = "disabled"; + scan_period = <20>; + key_num = <2>; + key_name = "bluetooth", "mute"; + key_code = <600 SW_MUTE_DEVICE>; + key_type = ; + key-gpios = <&gpio GPIOD_2 GPIO_ACTIVE_HIGH + &gpio GPIOA_7 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "disabled"; + key_name = "key_a", "key_b", "key_c"; + key_num = <3>; + io-channels = <&saradc 0>; + io-channel-names = "key-chan-0"; + key_chan = <0 0 0>; + key_code = <141 114 115>; + key_val = <900 511 0>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40>; + }; + + vddq_reg: fixedregulator@vddq { + compatible = "regulator-fixed"; + vin-supply = <&vbat>; + regulator-name = "VDDQ_1V1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + pinctrl-names = "default"; + gpio = <&gpio GPIOD_8 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ddr_reg: fixedregulator@vdd_ddr { + compatible = "regulator-fixed"; + vin-supply = <&vbat>; + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <823000>; + regulator-max-microvolt = <823000>; + pinctrl-names = "default"; + gpio = <&gpio GPIOD_8 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + vddao3v3_p_reg: fixedregulator@vddao3v3_p { + vin-supply = <&vbat>; + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3.3V_P"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vddao1v8_reg: fixedregulator@vddao1v8 { + compatible = "regulator-fixed"; + vin-supply = <&vddao3v3_p_reg>; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vddao3v3_reg: fixedregulator@vddao3v3 { + vin-supply = <&vddao3v3_p_reg>; + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc3v3_reg: fixedregulator@vcc3v3 { + vin-supply = <&vddao3v3_reg>; + compatible = "regulator-fixed"; + regulator-name = "VCC3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + gpio = <&gpio GPIOD_10 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + vcc1v8_reg: fixedregulator@vcc1v8 { + vin-supply = <&vcc3v3_reg>; + compatible = "regulator-fixed"; + regulator-name = "VCC1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + emmc1v8_reg: fixedregulator@emmc1v8 { + vin-supply = <&vcc3v3_reg>; + compatible = "regulator-fixed"; + regulator-name = "EMMC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + sdcard_3v3: sdcard-3v3 { + compatible = "regulator-fixed"; + regulator-name = "SD_3V3"; + vin-supply = <&vcc3v3_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + // GPIOH_7(Down) Output L= Enable SD_3V3 + gpio = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; + // (GPIOH_7 |sdcard-3v3) out lo ACTIVE LOW + enable-active-low; //3.3V , high: 0V + regulator-boot-on; + regulator-always-on; + }; + + vddio_c: sdcard-1v8_3v3 { + compatible = "regulator-gpio"; + regulator-name = "VDDIO_C"; + vin-supply = <&vcc3v3_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + // GPIOH_8(DOWN) H: 1.8V, L: 3.3V + gpio = <&gpio GPIOH_8 GPIO_ACTIVE_HIGH>; + // (GPIOH_8 |VDDIO_C) out lo : 3300mV, 3.3V + gpios-states = <0>; + + /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ + states = <1800000 1 + 3300000 0>; + }; +}; + +&audiobus { + tdma:tdm@0 { + compatible = "amlogic, tm2-revb-snd-tdma"; + #sound-dai-cells = <0>; + + dai-tdm-lane-slot-mask-in = <1 0>; + dai-tdm-lane-slot-mask-out = <0 1>; + dai-tdm-clk-sel = <0>; + //clocks = <&clkaudio CLKID_AUDIO_MCLK_A + // &clkc CLKID_HIFI_PLL + // &clkc CLKID_HIFI1_PLL>; + //clock-names = "mclk", "clk_srcpll", "clk_src_cd"; + + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdm_a_pins + &tdm_d0_pins + &tdm_d1_pins + &tdma_clk_pins>; + /* suspend disable clk */ + suspend-clk-off = <1>; + status = "disabled"; + + }; + + tdmb: tdm@1 { + compatible = "amlogic, tm2-revb-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 1 1 1>; + dai-tdm-lane-slot-mask-out = <1 1 1 1>; + dai-tdm-clk-sel = <1>; + //clocks = <&clkaudio CLKID_AUDIO_MCLK_B + // &clkc CLKID_HIFI_PLL + // &clkc CLKID_HIFI1_PLL>; + //clock-names = "mclk", "clk_srcpll", "clk_src_cd"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = ; + i2s2hdmi = <1>; + /* suspend disable clk */ + suspend-clk-off = <1>; + status = "disabled"; + }; + + tdmc: tdm@2 { + compatible = "amlogic, tm2-revb-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 1 1 1>; + dai-tdm-lane-slot-mask-out = <1 1 1 1>; + dai-tdm-clk-sel = <2>; + //clocks = <&clkaudio CLKID_AUDIO_MCLK_C + // &clkc CLKID_HIFI_PLL + // &clkc CLKID_HIFI1_PLL>; + //clock-names = "mclk", "clk_srcpll", "clk_src_cd"; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + + /*enable default mclk(12.288M), before extern codec start*/ + start_clk_enable = <1>; + + /*tdm clk tuning enable*/ + clk_tuning_enable = <1>; + /* suspend disable clk */ + suspend-clk-off = <1>; + status = "disabled"; + }; + + tdmd:tdm@3 { + compatible = "amlogic, p1-snd-tdmd"; + #sound-dai-cells = <0>; + + dai-tdm-lane-slot-mask-in = <1 0 0 0>; + dai-tdm-lane-slot-mask-out = <1 1 1 1>; + dai-tdm-clk-sel = <3>; + + //clocks = <&clkaudio CLKID_AUDIO_GATE_TDMIND + // &clkaudio CLKID_AUDIO_GATE_TDMOUTD + // &clkaudio CLKID_AUDIO_MCLK_D + // &clkaudio CLKID_AUDIO_MCLK_PAD3 + // &clkc CLKID_HIFI_PLL + // &clkc CLKID_HIFI1_PLL>; + //clock-names = "gate_in", "gate_out", "mclk", + // "mclk_pad", "clk_srcpll", "clk_src_cd"; + /* suspend disable clk */ + suspend-clk-off = <1>; + start_clk_enable = <1>; + status = "disabled"; + }; + + pdm:pdm { + compatible = "amlogic, tm2-revb-snd-pdm"; + #sound-dai-cells = <0>; + + //clocks = <&clkaudio CLKID_AUDIO_GATE_PDM + // &clkc CLKID_FCLK_DIV3 + // &clkc CLKID_HIFI1_PLL + // &clkaudio CLKID_AUDIO_PDMIN0 + // &clkaudio CLKID_AUDIO_PDMIN1>; + //clock-names = "gate", + // "sysclk_srcpll", + // "dclk_srcpll", + // "pdm_dclk", + // "pdm_sysclk"; + + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; + + train_sample_count = <0xb>; + + status = "disabled"; + }; + + spdifa:spdif@0 { + compatible = "amlogic, tm2-revb-snd-spdif-a"; + #sound-dai-cells = <0>; + + //clocks = <&clkc CLKID_HIFI_PLL + // &clkc CLKID_HIFI1_PLL + // &clkc CLKID_FCLK_DIV4 + // &clkaudio CLKID_AUDIO_GATE_SPDIFIN + // &clkaudio CLKID_AUDIO_GATE_SPDIFOUT_A + // &clkaudio CLKID_AUDIO_SPDIFIN + // &clkaudio CLKID_AUDIO_SPDIFOUT_A>; + //clock-names = "sysclk", "clk_src_cd", "fixed_clk", "gate_spdifin", + // "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins", "spdif_pins_mute"; + pinctrl-0 = <&spdifout>; + pinctrl-1 = <&spdifout_a_mute>; + /*spdif clk tuning enable*/ + clk_tuning_enable = <1>; + /* suspend disable clk */ + suspend-clk-off = <1>; + status = "disabled"; + }; + + spdifb:spdif@1 { + compatible = "amlogic, tm2-revb-snd-spdif-b"; + #sound-dai-cells = <0>; + //clocks = <&clkc CLKID_HIFI_PLL /*CLKID_HIFI_PLL*/ + // &clkc CLKID_HIFI1_PLL + // &clkaudio CLKID_AUDIO_GATE_SPDIFOUT_B + // &clkaudio CLKID_AUDIO_SPDIFOUT_B>; + //clock-names = "sysclk", "clk_src_cd", + // "gate_spdifout", "clk_spdifout"; + /* suspend disable clk */ + suspend-clk-off = <1>; + status = "disabled"; + }; + + extn:extn { + compatible = "amlogic, t7-snd-extn"; + #sound-dai-cells = <0>; + + interrupts = + ; + interrupt-names = "irq_frhdmirx"; + + status = "disabled"; + }; + + aed:effect { + compatible = "amlogic, snd-effect-v3"; + #sound-dai-cells = <0>; + + //clocks = <&clkaudio CLKID_AUDIO_GATE_EQDRC + // &clkc CLKID_FCLK_DIV5 + // &clkaudio CLKID_AUDIO_EQDRC>; + //clock-names = "gate", "srcpll", "eqdrc"; + + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <2>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + + status = "disabled"; + }; + + asrca:resample@0 { + compatible = "amlogic, t5-resample-a"; + //clocks = <&clkc CLKID_HIFI_PLL + // &clkaudio CLKID_AUDIO_MCLK_B + // &clkaudio CLKID_AUDIO_RESAMPLE_A>; + //clock-names = "resample_pll", "resample_src", "resample_clk"; + + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * FRATV, 5 + * TDMIN_LB, 6 + * LOOPBACK_A, 7 + * FRHDMIRX, 8 + * LOOPBACK_B, 9 + * SPDIFIN_LB, 10 + * EARC_RX, 11 + */ + resample_module = <6>; + /* suspend disable clk */ + suspend-clk-off = <1>; + status = "disabled"; + }; + + asrcb:resample@1 { + compatible = "amlogic, t5-resample-b"; + //clocks = <&clkc CLKID_HIFI_PLL + // &clkaudio CLKID_AUDIO_MCLK_F + // &clkaudio CLKID_AUDIO_RESAMPLE_B>; + //clock-names = "resample_pll", "resample_src", "resample_clk"; + + /*this resample is only used for loopback_A.*/ + capture_sample_rate = <16000>; + /* suspend disable clk */ + suspend-clk-off = <1>; + status = "disabled"; + }; + + vad:vad { + compatible = "amlogic, snd-vad"; + #sound-dai-cells = <0>; + + clocks = <&clkaudio CLKID_AUDIO_GATE_TOVAD + &clkc CLKID_FCLK_DIV5 + &clkaudio CLKID_AUDIO_VAD>; + clock-names = "gate", "pll", "clk"; + + interrupts = ; + interrupt-names = "irq_wakeup", "irq_frame_sync"; + + /* + * Data src sel: + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + * 5: loopback_b; + * 6: tdmin_lb; + * 7: loopback_a; + */ + src = <4>; + + /* + * deal with hot word in user space or kernel space + * 0: in user space + * 1: in kernel space + */ + level = <1>; + + status = "disabled"; + }; + + loopbacka:loopback@0 { + compatible = "amlogic, p1-loopbacka"; + #sound-dai-cells = <0>; + + //clocks = <&clkaudio CLKID_AUDIO_GATE_PDM + // &clkc CLKID_FCLK_DIV3 + // &clkc CLKID_HIFI_PLL + // &clkaudio CLKID_AUDIO_PDMIN0 + // &clkaudio CLKID_AUDIO_PDMIN1 + // &clkc CLKID_HIFI_PLL + // &clkaudio CLKID_AUDIO_MCLK_A>; + //clock-names = "pdm_gate", + // "pdm_sysclk_srcpll", + // "pdm_dclk_srcpll", + // "pdm_dclk", + // "pdm_sysclk", + // "tdminlb_mpll", + // "tdminlb_mclk"; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <4>; + datain_chmask = <0xf>; + /* config which data pin for loopback */ + datain-lane-mask-in = <1 0 1 0>; + + /* calc mclk for datalb */ + mclk-fs = <256>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_TDMINA_DIN*, refer to core pinmux + * 4: PAD_TDMINB_DIN*, refer to core pinmux + * 5: PAD_TDMINC_DIN*, refer to core pinmux + * 6: PAD_TDMINA_D*, oe, refer to core pinmux + * 7: PAD_TDMINB_D*, oe, refer to core pinmux + */ + /* if tdmin_lb >= 3, use external loopback */ + datalb_src = <1>; + datalb_chnum = <2>; + datalb_chmask = <0x3>; + /* config which data pin as loopback */ + datalb-lane-mask-in = <1 0 0 0>; + /* suspend disable clk */ + suspend-clk-off = <1>; + status = "disabled"; + }; + + loopbackb:loopback@1 { + compatible = "amlogic, p1-loopbackb"; + #sound-dai-cells = <0>; + + //clocks = <&clkaudio CLKID_AUDIO_GATE_PDM + // &clkc CLKID_FCLK_DIV3 + // &clkc CLKID_HIFI_PLL + // &clkaudio CLKID_AUDIO_PDMIN0 + // &clkaudio CLKID_AUDIO_PDMIN1 + // &clkc CLKID_HIFI_PLL + // &clkaudio CLKID_AUDIO_MCLK_A>; + //clock-names = "pdm_gate", + // "pdm_sysclk_srcpll", + // "pdm_dclk_srcpll", + // "pdm_dclk", + // "pdm_sysclk", + // "tdminlb_mpll", + // "tdminlb_mclk"; + + /* calc mclk for datain_lb */ + mclk-fs = <256>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + /* for s5 atv ok google */ + datain_chnum = <0>; + datain_chmask = <0>; + /* config which data pin for loopback */ + datain-lane-mask-in = <0 0 0 0>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_TDMINA_DIN*, refer to core pinmux + * 4: PAD_TDMINB_DIN*, refer to core pinmux + * 5: PAD_TDMINC_DIN*, refer to core pinmux + * 6: PAD_TDMINA_D*, oe, refer to core pinmux + * 7: PAD_TDMINB_D*, oe, refer to core pinmux + */ + /* if tdmin_lb >= 3, use external loopback */ + datalb_src = <1>; + datalb_chnum = <2>; + datalb_chmask = <0x3>; + /* config which data pin as loopback */ + datalb-lane-mask-in = <1 0 0 0>; + /* suspend disable clk */ + suspend-clk-off = <1>; + status = "disabled"; + }; +}; /* end of audiobus */ + +&earc { + suspend-clk-off = <1>; + status = "disabled"; +}; + +&crg21_otg { + status = "disabled"; + controller-type = <1>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&crg20 { + compatible = "amlogic, crg-host-drd"; + status = "disabled"; +}; + +&crg31 { + compatible = "amlogic, crg-host-drd"; + status = "disabled"; +}; + +&crg30_drd { + compatible = "amlogic, crg-drd"; + status = "disabled"; +}; + +&usb2_m31_0_phy { + status = "disabled"; +}; + +&usb3_m31_0_phy { + status = "disabled"; + portnum = <1>; +}; + +&usb2_m31_1_phy { + status = "disabled"; +}; + +&usb3_m31_1_phy { + status = "disabled"; + portnum = <0>; +}; + +&crg_phy_20 { + status = "disabled"; + portnum = <1>; +}; + +&crg3_phy_20 { + status = "disabled"; + portnum = <0>; +}; + +&crg_udc_2 { + status = "disabled"; + controller-type = <4>; +}; + +&pcie1 { + reset-gpio = <&gpio GPIOX_5 GPIO_ACTIVE_HIGH>; + iommu-map = <0x100 &smmu 0x5 0x10>; + status = "disabled"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; +}; + +&i2c1 { + status = "disabled"; + pinctrl-names="default"; + pinctrl-0=<&i2c1_pins1>; + + aw9523: aw9523_led@5b { + compatible = "amlogic,aw9523b_led"; + reg = <0x5b>; + status = "okay"; + reset-gpio = <&gpio GPIOA_4 GPIO_ACTIVE_HIGH>; + platform = <4>; + + led1 { + default_colors = <0 0 0>; + r_io_number = <0>; + g_io_number = <10>; + b_io_number = <5>; + }; + + led2 { + default_colors = <0 0 0>; + r_io_number = <1>; + g_io_number = <11>; + b_io_number = <6>; + }; + + led3 { + default_colors = <0 0 0>; + r_io_number = <2>; + g_io_number = <12>; + b_io_number = <7>; + }; + + led4 { + default_colors = <0 0 0>; + r_io_number = <3>; + g_io_number = <13>; + b_io_number = <8>; + }; + led9 { + default_colors = <0 0 0>; + r_io_number = <4>; + g_io_number = <14>; + b_io_number = <9>; + }; + }; +}; + +&i2c5 { + status = "disable"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins2>; +}; + +&csiphy2 { + port { + csiphy2_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 1>; + //remote-endpoint = <&ov9285_2_ep>; + }; + }; +}; + +&isp2 { + memory-region = <&camera_cma_reserved>; +}; + +&csiphy3 { + port { + csiphy3_ep: endpoint { + clock-lanes = <1>; + data-lanes = <3 4>; + //remote-endpoint = <&ov9285_3_ep>; + }; + }; +}; + +&isp3 { + memory-region = <&camera_cma_reserved>; +}; + +&i2c5 { + status = "disable"; + pinctrl-names = "default";//, "sleep" + pinctrl-0 = <&i2c5_pins1>; + //pinctrl-1 = <&i2c2_sleep_pins2>; + clock-frequency = <100000>; /* default 100k */ +}; + +&i2c2 { + status = "disabled"; + pinctrl-names="default"; + pinctrl-0=<&i2c2_pins2>; + clock-frequency = <300000>; +}; + +/* SDIO */ +/* ref board pcie wifi */ +&sd_emmc_a { + status = "disabled"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <200000000>; + + non-removable; + disable-wp; + + //vmmc-supply = <&sdcard_3v3>; + //vqmmc-supply = <&vddio_c>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "disabled"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_clk_gate_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sdcard_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sdcard_pins &ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins + &ao_to_sd_uart_pins>; + pinctrl-7 = <&sdcard_pins &ao_uart_pins>; + pinctrl-8 = <&sd_to_ao_uart_clr_pins + &ao_to_sd_uart_pins>; + pinctrl-names = "sd_default", + "clk-gate", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "sd_to_ao_jtag_pins", + "ao_to_sd_jtag_pins"; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <200000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + //dat1-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&sdcard_3v3>; + vqmmc-supply = <&vddio_c>; +}; + +&sd_emmc_c { + status = "disabled"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; +// mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + //mmc-hs400-enhanced-strobe; + max-frequency = <200000000>; + non-removable; + disable-wp; + +// mmc-pwrseq = <&emmc_pwrseq>; +// vmmc-supply = <&sdcard_3v3>; +// vqmmc-supply = <&vddio_c>; +}; + +&saradc { + status = "disabled"; +}; + +ðmac { + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + status = "disabled"; + phy-mode = "rgmii"; + phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; +}; + +&uart_A { + status = "okay"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_pins>; + pinctrl-names = "default"; +}; + +&spifc { + status = "disabled"; + spi-nor@0 { + status = "disabled"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_t>; + cs-gpios = <&gpio GPIOT_4 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins>; + cs-gpios = <&gpio GPIOH_6 0>; +}; + +&spicc2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc2_pins_x>; + cs-gpios = <&gpio GPIOX_2 0>; +}; + +&fb { + status = "disabled"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000>; + logo_addr = "0x3e800000"; + mem_alloc = <0>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&drm_vpu { + status = "disabled"; + logo_addr = "0x3e800000"; +}; + +&amhdmitx { + status = "disabled"; + pxp_mode = <1>; /* run on pxp */ +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + /*memory-region = <&vdin0_cma_reserved>;*/ + status = "disabled"; + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + * onebuffer: + * worst case:(4096*2160*3 + 2M(afbce issue)) = 27.5M + * dw:960x540x3 = 1.5M + * total size:(27.5+1.5)x buffernumber + */ + cma_size = <300>; + frame_buff_num = <10>; +}; + +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "disabled"; +}; + +&periphs_pinctrl { + pdmin: pdmin { + mux { /* GPIOA_3, GPIOA_2 */ + groups = "pdm_din0_a"; + function = "pdm"; + }; + mux1 { + groups = "pdm_dclk_a"; + function = "pdm"; + drive-strength-microamp = <3000>; + }; + }; + tdm_a_pins: tdm_a_pin { + mux { /* GPIOX_11, GPIOX_10, GPIOX_8, GPIOX_9 */ + groups = "tdm_sclk0", + "tdm_fs0", + "tdm_d0", + "tdm_d1"; + function = "tdm"; + }; + }; + tdm_b_pins: tdm_b_pin { + mux { /* GPIOA_7, GPIOA_8, GPIOA_1 */ + groups = "tdm_sclk2_a", + "tdm_fs2_a", + "tdm_d5_a"; + function = "tdm"; + }; + }; + + spdifout: spdifout { + mux { /* GPIOH_4 */ + groups = "spdif_out_h"; + function = "spdif_out"; + }; + }; + + spdifout_a_mute: spdifout_a_mute { + mux { /* GPIOH_4 */ + groups = "GPIOH_4"; + function = "gpio_periphs"; + output-low; + }; + }; + + spdifin: spdifin { + mux { /* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + spdifin_a_mute: spdifin_a_mute { + mux { /* GPIOH_5 */ + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-low; + }; + }; + tdm_c_pins: tdm_c_pin { + mux { /* GPIOK_9, GPIOK_10, GPIOK_11, GPIOK_12 */ + groups = "tdm_sclk2", + "tdm_fs2", + "tdm_d4", + "tdm_d5"; + function = "tdm"; + }; + }; + tdm_d_pins: tdm_d_pin { + mux { /* GPIOT_18, GPIOT_19, GPIOT_20 */ + groups = "tdm_sclk1_t", + "tdm_fs1_t", + "tdm_d2_t"; + function = "tdm"; + }; + }; + dvb_s_ts0_pins: dvb_s_ts0_pins { + tsin_a { + groups = "tsin_a_sop", + "tsin_a_valid", + "tsin_a_clk", + "tsin_a_din0"; + function = "tsin_a"; + }; + }; + + dvb_s_ts1_pins: dvb_s_ts1_pins { + tsin_b { + groups = "tsin_b_sop", + "tsin_b_valid", + "tsin_b_clk", + "tsin_b_din0"; + function = "tsin_b"; + }; + }; +}; + +&pinctrl_audio { + tdm_d0_pins: tdm_d0_pin { + mux { + groups = "tdm_d0"; + function = "tdmouta_lane1"; + }; + }; + tdm_d1_pins: tdm_d1_pin { + mux { + groups = "tdm_d1"; + function = "tdmina_lane0"; + }; + }; + tdm_d5_a_pins: tdm_d5_a_pin { + mux { + groups = "tdm_d5"; + function = "tdmoutb_lane0"; + }; + }; + tdm_d2_t_pins: tdm_d2_t_pin { + mux { + groups = "tdm_d2_t"; + function = "tdmind_lane0"; + }; + }; + tdm_d4_pins: tdm_d4_pin { + mux { + groups = "tdm_d4"; + function = "tdmoutc_lane0"; + }; + }; + + tdm_d5_pins: tdm_d5_pin { + mux { + groups = "tdm_d5"; + function = "tdminc_lane0"; + }; + }; + tdm_d6_pins: tdm_d6_pin { + mux { + groups = "tdm_d6"; + function = "tdmoutd_lane1"; + }; + }; + + tdm_d7_pins: tdm_d7_pin { + mux { + groups = "tdm_d7"; + function = "tdmoutd_lane0"; + }; + }; + tdma_clk_pins: tdma_clk_pin { + mux { + groups = "tdm_sclk0", "tdm_lrclk0"; + function = "tdm_clk_outa"; + }; + }; + tdmb_clk_pins: tdmb_clk_pin { + mux { + groups = "tdm_sclk2", "tdm_lrclk2"; + function = "tdm_clk_outb"; + }; + }; + + tdmd_clk_pins: tdmd_clk_pin { + mux { + groups = "tdm_sclk1", "tdm_lrclk1"; + //function = "tdm_clk_in"; + function = "tdm_clk_outd"; + }; + }; +}; + +&amlvecm { + status = "disabled"; + gamma_en = <0>;/*1:enable ;0:disable*/ + wb_en = <0>;/*1:enable ;0:disable*/ + cm_en = <0>;/*1:enable ;0:disable*/ + wb_sel = <0>;/*1:mtx ;0:gainoff*/ + vlock_en = <0>;/*1:enable;0:disable*/ + vlock_mode = <0x8>; + /*vlock work mode: + *bit0:auto ENC + *bit1:auto PLL + *bit2:manual PLL + *bit3:manual ENC + *bit4:manual soft ENC + *bit5:manual MIX PLL ENC + */ + vlock_pll_m_limit = <1>; + vlock_line_limit = <2>; +}; + +&aml_wifi{ + status = "disabled"; + interrupt-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + power_on-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; +}; + +&aml_bt { + status = "disabled"; + reset-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + /*hostwake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;*/ +}; + +&pwm_ab { + pinctrl-0 = <&pwm_a_pins1>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&pwm_cd { + status = "disabled"; +}; + +&pwm_ef { + pinctrl-0 = <&pwm_f_pins>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&irblaster { + status = "disabled"; +}; + +&uart_B { + status = "okay"; +}; + +&vddcpua { + status = "okay"; +}; + +&vddcpub { + status = "okay"; +}; + +&vddnpu { + status = "okay"; +}; diff --git a/include/dt-bindings/clock/amlogic,t3x-audio-clk.h b/include/dt-bindings/clock/amlogic,t3x-audio-clk.h new file mode 100644 index 000000000..8decb1361 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,t3x-audio-clk.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __S5_AUDIO_CLK_H__ +#define __S5_AUDIO_CLK_H__ + +/* + * CLKID audio index values + */ + +#define CLKID_AUDIO_GATE_DDR_ARB 0 +#define CLKID_AUDIO_GATE_PDM 1 +#define CLKID_AUDIO_GATE_TDMINA 2 +#define CLKID_AUDIO_GATE_TDMINB 3 +#define CLKID_AUDIO_GATE_TDMINC 4 +#define CLKID_AUDIO_GATE_TDMINLB 5 +#define CLKID_AUDIO_GATE_TDMOUTA 6 +#define CLKID_AUDIO_GATE_TDMOUTB 7 +#define CLKID_AUDIO_GATE_TDMOUTC 8 +#define CLKID_AUDIO_GATE_FRDDRA 9 +#define CLKID_AUDIO_GATE_FRDDRB 10 +#define CLKID_AUDIO_GATE_FRDDRC 11 +#define CLKID_AUDIO_GATE_TODDRA 12 +#define CLKID_AUDIO_GATE_TODDRB 13 +#define CLKID_AUDIO_GATE_TODDRC 14 +#define CLKID_AUDIO_GATE_LOOPBACKA 15 +#define CLKID_AUDIO_GATE_SPDIFIN 16 +#define CLKID_AUDIO_GATE_SPDIFOUT_A 17 +#define CLKID_AUDIO_GATE_RESAMPLEA 18 +#define CLKID_AUDIO_GATE_RESERVED0 19 +#define CLKID_AUDIO_GATE_RESERVED1 20 +#define CLKID_AUDIO_GATE_SPDIFOUT_B 21 +#define CLKID_AUDIO_GATE_EQDRC 22 +#define CLKID_AUDIO_GATE_RESERVED2 23 +#define CLKID_AUDIO_GATE_RESERVED3 24 +#define CLKID_AUDIO_GATE_RESERVED4 25 +#define CLKID_AUDIO_GATE_RESAMPLEB 26 +#define CLKID_AUDIO_GATE_TOVAD 27 +#define CLKID_AUDIO_GATE_AUDIOLOCKER 28 +#define CLKID_AUDIO_GATE_SPDIFIN_LB 29 +#define CLKID_AUDIO_GATE_FRATV 30 +#define CLKID_AUDIO_GATE_FRHDMIRX 31 + +/* Gate En1 */ +#define CLKID_AUDIO_GATE_FRDDRD 32 +#define CLKID_AUDIO_GATE_TODDRD 33 +#define CLKID_AUDIO_GATE_LOOPBACKB 34 +#define CLKID_AUDIO_GATE_FRDDRE 35 +#define CLKID_AUDIO_GATE_EARCRX 36 +#define CLKID_AUDIO_GATE_TDMIND 37 +#define CLKID_AUDIO_GATE_TDMOUTD 38 +#define CLKID_AUDIO_GATE_PCPD_A 39 +#define CLKID_AUDIO_GATE_PCPD_B 40 + +#define CLKID_AUDIO_GATE_MAX 41 + +#define MCLK_BASE CLKID_AUDIO_GATE_MAX +#define CLKID_AUDIO_MCLK_A (MCLK_BASE + 0) +#define CLKID_AUDIO_MCLK_B (MCLK_BASE + 1) +#define CLKID_AUDIO_MCLK_C (MCLK_BASE + 2) +#define CLKID_AUDIO_MCLK_D (MCLK_BASE + 3) +#define CLKID_AUDIO_MCLK_E (MCLK_BASE + 4) +#define CLKID_AUDIO_MCLK_F (MCLK_BASE + 5) + +#define CLKID_AUDIO_SPDIFIN (MCLK_BASE + 6) +#define CLKID_AUDIO_SPDIFOUT_A (MCLK_BASE + 7) +#define CLKID_AUDIO_RESAMPLE_A (MCLK_BASE + 8) +#define CLKID_AUDIO_LOCKER_OUT (MCLK_BASE + 9) +#define CLKID_AUDIO_LOCKER_IN (MCLK_BASE + 10) +#define CLKID_AUDIO_PDMIN0 (MCLK_BASE + 11) +#define CLKID_AUDIO_PDMIN1 (MCLK_BASE + 12) +#define CLKID_AUDIO_SPDIFOUT_B (MCLK_BASE + 13) +#define CLKID_AUDIO_RESAMPLE_B (MCLK_BASE + 14) +#define CLKID_AUDIO_SPDIFIN_LB (MCLK_BASE + 15) +#define CLKID_AUDIO_EQDRC (MCLK_BASE + 16) +#define CLKID_AUDIO_VAD (MCLK_BASE + 17) +#define CLKID_EARCTX_CMDC (MCLK_BASE + 18) +#define CLKID_EARCTX_DMAC (MCLK_BASE + 19) +#define CLKID_EARCRX_CMDC (MCLK_BASE + 20) +#define CLKID_EARCRX_DMAC (MCLK_BASE + 21) + +#define CLKID_AUDIO_MCLK_PAD0 (MCLK_BASE + 22) +#define CLKID_AUDIO_MCLK_PAD1 (MCLK_BASE + 23) +#define CLKID_AUDIO_MCLK_PAD2 (MCLK_BASE + 24) +#define CLKID_AUDIO_MCLK_PAD3 (MCLK_BASE + 25) + +#define CLKID_AUDIO_PDMBIN0 (MCLK_BASE + 26) +#define CLKID_AUDIO_PDMBIN1 (MCLK_BASE + 27) +#define NUM_AUDIO_CLKS (MCLK_BASE + 28) +#endif /* __S5_AUDIO_CLK_H__ */ diff --git a/include/dt-bindings/clock/t3x-clkc.h b/include/dt-bindings/clock/t3x-clkc.h new file mode 100644 index 000000000..d45d4a26a --- /dev/null +++ b/include/dt-bindings/clock/t3x-clkc.h @@ -0,0 +1,408 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __S5_CLKC_H +#define __S5_CLKC_H + +/* + * CLKID index values + */ +#define CLKID_SYS_PLL_DCO 0 +#define CLKID_SYS_PLL 1 +#define CLKID_SYS1_PLL_DCO 2 +#define CLKID_SYS1_PLL 3 +#define CLKID_FIXED_PLL_DCO 4 +#define CLKID_FIXED_PLL 5 +#define CLKID_FCLK_DIV2_DIV 6 +#define CLKID_FCLK_DIV2 7 +#define CLKID_FCLK_DIV3_DIV 8 +#define CLKID_FCLK_DIV3 9 +#define CLKID_FCLK_DIV4_DIV 10 +#define CLKID_FCLK_DIV4 11 +#define CLKID_FCLK_DIV5_DIV 12 +#define CLKID_FCLK_DIV5 13 +#define CLKID_FCLK_DIV7_DIV 14 +#define CLKID_FCLK_DIV7 15 +#define CLKID_FCLK_DIV2P5_DIV 16 +#define CLKID_FCLK_DIV2P5 17 +#define CLKID_FCLK_CLK50M_DIV 18 +#define CLKID_FCLK_CLK50M 19 +#define CLKID_GP0_PLL_DCO 20 +#define CLKID_GP0_PLL 21 +#define CLKID_GP1_PLL_DCO 22 +#define CLKID_GP1_PLL 23 +#define CLKID_CPU_DYN_CLK 24 +#define CLKID_CPU_CLK 25 +#define CLKID_HIFI_PLL_DCO 26 +#define CLKID_HIFI_PLL 27 +#define CLKID_PCIE_PLL_DCO 28 +#define CLKID_PCIE_PLL_DCO_DIV2 29 +#define CLKID_PCIE_PLL_OD 30 +#define CLKID_PCIE_PLL 31 +#define CLKID_PCIE_BGP 32 +#define CLKID_PCIE_HCSL_OUT 33 +#define CLKID_PCIE_HCSL_PAD 34 +#define CLKID_PCIE_HCSL_IN_PAD 35 +#define CLKID_PCIE_CLK_IN 36 +#define CLKID_PCIE1_PLL_DCO 37 +#define CLKID_PCIE1_PLL_DCO_DIV2 38 +#define CLKID_PCIE1_PLL_OD 39 +#define CLKID_PCIE1_PLL 40 +#define CLKID_PCIE1_BGP 41 +#define CLKID_PCIE1_HCSL_OUT 42 +#define CLKID_PCIE1_HCSL_PAD 43 +#define CLKID_PCIE1_HCSL_IN_PAD 44 +#define CLKID_PCIE1_CLK_IN 45 +#define CLKID_SYS2_PLL_DCO 46 +#define CLKID_SYS2_PLL 47 +#define CLKID_A76_DYN_CLK 48 +#define CLKID_A76_CLK 49 +#define CLKID_DSU_DYN_CLK 50 +#define CLKID_DSU_CLK 51 +#define CLKID_DSU_FINAL_CLK 52 +#define CLKID_GP2_PLL_DCO 53 +#define CLKID_GP2_PLL 54 +#define CLKID_NNA_PLL_DCO 55 +#define CLKID_NNA_PLL 56 +#define CLKID_NNA_PLL_AUDIO 57 +#define CLKID_HIFI1_PLL_DCO 58 +#define CLKID_HIFI1_PLL 59 +#define CLKID_FDLE_PLL_DCO 60 +#define CLKID_FDLE_PLL_OD 61 +#define CLKID_FDLE_PLL_OD1 62 +#define CLKID_FDLE_PLL_TMDS 63 +#define CLKID_FDLE_PLL_PIXEL 64 +#define CLKID_CPU4_CLK 65 + +#define CLKID_BASE 66 +#define CLKID_RTC_32K_CLKIN (CLKID_BASE + 0) +#define CLKID_RTC_32K_DIV (CLKID_BASE + 1) +#define CLKID_RTC_32K_XATL (CLKID_BASE + 2) +#define CLKID_RTC_32K_SEL (CLKID_BASE + 3) +#define CLKID_RTC_CLK (CLKID_BASE + 4) +#define CLKID_SYS_CLK_1_SEL (CLKID_BASE + 5) +#define CLKID_SYS_CLK_1_DIV (CLKID_BASE + 6) +#define CLKID_SYS_CLK_1 (CLKID_BASE + 7) +#define CLKID_SYS_CLK_0_SEL (CLKID_BASE + 8) +#define CLKID_SYS_CLK_0_DIV (CLKID_BASE + 9) +#define CLKID_SYS_CLK_0 (CLKID_BASE + 10) +#define CLKID_SYS_CLK (CLKID_BASE + 11) +#define CLKID_CECA_32K_CLKIN (CLKID_BASE + 12) +#define CLKID_CECA_32K_DIV (CLKID_BASE + 13) +#define CLKID_CECA_32K_MUX_PRE (CLKID_BASE + 14) +#define CLKID_CECA_32K_MUX (CLKID_BASE + 15) +#define CLKID_CECA_32K_CLKOUT (CLKID_BASE + 16) +#define CLKID_CECB_32K_CLKIN (CLKID_BASE + 17) +#define CLKID_CECB_32K_DIV (CLKID_BASE + 18) +#define CLKID_CECB_32K_MUX_PRE (CLKID_BASE + 19) +#define CLKID_CECB_32K_MUX (CLKID_BASE + 20) +#define CLKID_CECB_32K_CLKOUT (CLKID_BASE + 21) +#define CLKID_AXICLK_1_SEL (CLKID_BASE + 22) +#define CLKID_AXICLK_1_DIV (CLKID_BASE + 23) +#define CLKID_AXICLK_1 (CLKID_BASE + 24) +#define CLKID_AXICLK_0_SEL (CLKID_BASE + 25) +#define CLKID_AXICLK_0_DIV (CLKID_BASE + 26) +#define CLKID_AXICLK_0 (CLKID_BASE + 27) +#define CLKID_AXICLK (CLKID_BASE + 28) +#define CLKID_24M_CLK_GATE (CLKID_BASE + 29) +#define CLKID_24M_DIV2 (CLKID_BASE + 30) +#define CLKID_12M_CLK (CLKID_BASE + 31) +#define CLKID_25M_CLK_DIV (CLKID_BASE + 32) +#define CLKID_25M_CLK (CLKID_BASE + 33) + +#define VIDEO_BASE (CLKID_BASE + 34) +#define CLKID_VCLK_SEL (VIDEO_BASE + 0) +#define CLKID_VCLK2_SEL (VIDEO_BASE + 1) +#define CLKID_VCLK_INPUT (VIDEO_BASE + 2) +#define CLKID_VCLK2_INPUT (VIDEO_BASE + 3) +#define CLKID_VCLK_DIV (VIDEO_BASE + 4) +#define CLKID_VCLK2_DIV (VIDEO_BASE + 5) +#define CLKID_VCLK (VIDEO_BASE + 6) +#define CLKID_VCLK2 (VIDEO_BASE + 7) +#define CLKID_VCLK_DIV1 (VIDEO_BASE + 8) +#define CLKID_VCLK_DIV2_EN (VIDEO_BASE + 9) +#define CLKID_VCLK_DIV4_EN (VIDEO_BASE + 10) +#define CLKID_VCLK_DIV6_EN (VIDEO_BASE + 11) +#define CLKID_VCLK_DIV12_EN (VIDEO_BASE + 12) +#define CLKID_VCLK2_DIV1 (VIDEO_BASE + 13) +#define CLKID_VCLK2_DIV2_EN (VIDEO_BASE + 14) +#define CLKID_VCLK2_DIV4_EN (VIDEO_BASE + 15) +#define CLKID_VCLK2_DIV6_EN (VIDEO_BASE + 16) +#define CLKID_VCLK2_DIV12_EN (VIDEO_BASE + 17) +#define CLKID_VCLK_DIV2 (VIDEO_BASE + 18) +#define CLKID_VCLK_DIV4 (VIDEO_BASE + 19) +#define CLKID_VCLK_DIV6 (VIDEO_BASE + 20) +#define CLKID_VCLK_DIV12 (VIDEO_BASE + 21) +#define CLKID_VCLK2_DIV2 (VIDEO_BASE + 22) +#define CLKID_VCLK2_DIV4 (VIDEO_BASE + 23) +#define CLKID_VCLK2_DIV6 (VIDEO_BASE + 24) +#define CLKID_VCLK2_DIV12 (VIDEO_BASE + 25) +#define CLKID_CTS_ENCI_SEL (VIDEO_BASE + 26) +#define CLKID_CTS_ENCT_SEL (VIDEO_BASE + 28) +#define CLKID_CTS_ENCP_SEL (VIDEO_BASE + 29) +#define CLKID_CTS_ENCL_SEL (VIDEO_BASE + 30) +#define CLKID_CTS_VDAC_SEL (VIDEO_BASE + 31) +#define CLKID_CTS_ENCI (VIDEO_BASE + 32) +#define CLKID_CTS_ENCT (VIDEO_BASE + 33) +#define CLKID_CTS_ENCP (VIDEO_BASE + 34) +#define CLKID_CTS_ENCL (VIDEO_BASE + 35) +#define CLKID_CTS_VDAC (VIDEO_BASE + 36) + +#define PERI_BASE (VIDEO_BASE + 37) +#define CLKID_SD_EMMC_C_CLK_SEL (PERI_BASE + 0) +#define CLKID_SD_EMMC_C_CLK_DIV (PERI_BASE + 1) +#define CLKID_SD_EMMC_C_CLK (PERI_BASE + 2) +#define CLKID_SD_EMMC_A_CLK_SEL (PERI_BASE + 3) +#define CLKID_SD_EMMC_A_CLK_DIV (PERI_BASE + 4) +#define CLKID_SD_EMMC_A_CLK (PERI_BASE + 5) +#define CLKID_SD_EMMC_B_CLK_SEL (PERI_BASE + 6) +#define CLKID_SD_EMMC_B_CLK_DIV (PERI_BASE + 7) +#define CLKID_SD_EMMC_B_CLK (PERI_BASE + 8) +#define CLKID_SPICC0_SEL (PERI_BASE + 9) +#define CLKID_SPICC0_DIV (PERI_BASE + 10) +#define CLKID_SPICC0 (PERI_BASE + 11) +#define CLKID_SPICC1_SEL (PERI_BASE + 12) +#define CLKID_SPICC1_DIV (PERI_BASE + 13) +#define CLKID_SPICC1 (PERI_BASE + 14) +#define CLKID_SPICC2_SEL (PERI_BASE + 15) +#define CLKID_SPICC2_DIV (PERI_BASE + 16) +#define CLKID_SPICC2 (PERI_BASE + 17) +#define CLKID_PWM_A_SEL (PERI_BASE + 27) +#define CLKID_PWM_A_DIV (PERI_BASE + 28) +#define CLKID_PWM_A (PERI_BASE + 29) +#define CLKID_PWM_B_SEL (PERI_BASE + 30) +#define CLKID_PWM_B_DIV (PERI_BASE + 31) +#define CLKID_PWM_B (PERI_BASE + 32) +#define CLKID_PWM_C_SEL (PERI_BASE + 33) +#define CLKID_PWM_C_DIV (PERI_BASE + 34) +#define CLKID_PWM_C (PERI_BASE + 35) +#define CLKID_PWM_D_SEL (PERI_BASE + 36) +#define CLKID_PWM_D_DIV (PERI_BASE + 37) +#define CLKID_PWM_D (PERI_BASE + 38) +#define CLKID_PWM_E_SEL (PERI_BASE + 39) +#define CLKID_PWM_E_DIV (PERI_BASE + 40) +#define CLKID_PWM_E (PERI_BASE + 41) +#define CLKID_PWM_F_SEL (PERI_BASE + 42) +#define CLKID_PWM_F_DIV (PERI_BASE + 43) +#define CLKID_PWM_F (PERI_BASE + 44) +#define CLKID_PWM_G_SEL (PERI_BASE + 45) +#define CLKID_PWM_G_DIV (PERI_BASE + 46) +#define CLKID_PWM_G (PERI_BASE + 47) +#define CLKID_PWM_H_SEL (PERI_BASE + 48) +#define CLKID_PWM_H_DIV (PERI_BASE + 49) +#define CLKID_PWM_H (PERI_BASE + 50) +#define CLKID_PWM_I_SEL (PERI_BASE + 51) +#define CLKID_PWM_I_DIV (PERI_BASE + 52) +#define CLKID_PWM_I (PERI_BASE + 53) +#define CLKID_PWM_J_SEL (PERI_BASE + 54) +#define CLKID_PWM_J_DIV (PERI_BASE + 55) +#define CLKID_PWM_J (PERI_BASE + 56) +#define CLKID_SARADC_SEL (PERI_BASE + 57) +#define CLKID_SARADC_DIV (PERI_BASE + 58) +#define CLKID_SARADC (PERI_BASE + 59) +#define CLKID_GEN_SEL (PERI_BASE + 60) +#define CLKID_GEN_DIV (PERI_BASE + 61) +#define CLKID_GEN (PERI_BASE + 62) +#define CLKID_ETH_RMII_SEL (PERI_BASE + 63) +#define CLKID_ETH_RMII_DIV (PERI_BASE + 64) +#define CLKID_ETH_RMII (PERI_BASE + 65) +#define CLKID_ETH_DIV8 (PERI_BASE + 66) +#define CLKID_ETH_125M (PERI_BASE + 67) +#define CLKID_TS_CLK_DIV (PERI_BASE + 68) +#define CLKID_TS_CLK (PERI_BASE + 69) +#define CLKID_USB_250M_SEL (PERI_BASE + 70) +#define CLKID_USB_250M_DIV (PERI_BASE + 71) +#define CLKID_USB_250M (PERI_BASE + 72) +#define CLKID_PCIE_400M_SEL (PERI_BASE + 73) +#define CLKID_PCIE_400M_DIV (PERI_BASE + 74) +#define CLKID_PCIE_400M (PERI_BASE + 75) +#define CLKID_PCIE_CLK_SEL (PERI_BASE + 76) +#define CLKID_PCIE_CLK_DIV (PERI_BASE + 77) +#define CLKID_PCIE_CLK (PERI_BASE + 78) +#define CLKID_PCIE_TL_CLK_SEL (PERI_BASE + 79) +#define CLKID_PCIE_TL_CLK_DIV (PERI_BASE + 80) +#define CLKID_PCIE_TL_CLK (PERI_BASE + 81) +#define CLKID_CDAC_SEL (PERI_BASE + 82) +#define CLKID_CDAC_DIV (PERI_BASE + 83) +#define CLKID_CDAC (PERI_BASE + 84) +#define CLKID_SC_SEL (PERI_BASE + 85) +#define CLKID_SC_DIV (PERI_BASE + 86) +#define CLKID_SC (PERI_BASE + 87) + +#define MEDIA_BASE (PERI_BASE + 88) +#define CLKID_VAPB_0_SEL (MEDIA_BASE + 1) +#define CLKID_VAPB_0_DIV (MEDIA_BASE + 2) +#define CLKID_VAPB_0 (MEDIA_BASE + 3) +#define CLKID_GE2D_SEL (MEDIA_BASE + 4) +#define CLKID_GE2D_DIV (MEDIA_BASE + 5) +#define CLKID_GE2D (MEDIA_BASE + 6) +#define CLKID_NNA_0_SEL (MEDIA_BASE + 7) +#define CLKID_NNA_0_DIV (MEDIA_BASE + 8) +#define CLKID_NNA_0 (MEDIA_BASE + 9) +#define CLKID_NNA_1_SEL (MEDIA_BASE + 10) +#define CLKID_NNA_1_DIV (MEDIA_BASE + 11) +#define CLKID_NNA_1 (MEDIA_BASE + 12) +#define CLKID_NNA_SEL (MEDIA_BASE + 13) +#define CLKID_NNA (MEDIA_BASE + 14) +#define CLKID_VPU0_SEL (MEDIA_BASE + 15) +#define CLKID_VPU0_DIV (MEDIA_BASE + 16) +#define CLKID_VPU0 (MEDIA_BASE + 17) +#define CLKID_VPU1_SEL (MEDIA_BASE + 18) +#define CLKID_VPU1_DIV (MEDIA_BASE + 19) +#define CLKID_VPU1 (MEDIA_BASE + 20) +#define CLKID_VPU_SEL (MEDIA_BASE + 21) +#define CLKID_VPU (MEDIA_BASE + 22) +#define CLKID_VPU_CLKB_TMP_SEL (MEDIA_BASE + 23) +#define CLKID_VPU_CLKB_TMP_DIV (MEDIA_BASE + 24) +#define CLKID_VPU_CLKB_TMP (MEDIA_BASE + 25) +#define CLKID_VPU_CLKB_DIV (MEDIA_BASE + 26) +#define CLKID_VPU_CLKB (MEDIA_BASE + 27) +#define CLKID_VIN_MEAS_SEL (MEDIA_BASE + 28) +#define CLKID_VIN_MEAS_DIV (MEDIA_BASE + 29) +#define CLKID_VIN_MEAS (MEDIA_BASE + 30) +#define CLKID_VID_LOCK_SEL (MEDIA_BASE + 31) +#define CLKID_VID_LOCK_DIV (MEDIA_BASE + 32) +#define CLKID_VID_LOCK (MEDIA_BASE + 33) +#define CLKID_CMPR_SEL (MEDIA_BASE + 34) +#define CLKID_CMPR_DIV (MEDIA_BASE + 35) +#define CLKID_CMPR (MEDIA_BASE + 36) +#define CLKID_MALI0_SEL (MEDIA_BASE + 37) +#define CLKID_MALI0_DIV (MEDIA_BASE + 38) +#define CLKID_MALI0 (MEDIA_BASE + 39) +#define CLKID_MALI1_SEL (MEDIA_BASE + 40) +#define CLKID_MALI1_DIV (MEDIA_BASE + 41) +#define CLKID_MALI1 (MEDIA_BASE + 42) +#define CLKID_MALI_SEL (MEDIA_BASE + 43) +#define CLKID_MALI (MEDIA_BASE + 44) +#define CLKID_VDEC0_SEL (MEDIA_BASE + 45) +#define CLKID_VDEC0_DIV (MEDIA_BASE + 46) +#define CLKID_VDEC0 (MEDIA_BASE + 47) +#define CLKID_VDEC1_SEL (MEDIA_BASE + 48) +#define CLKID_VDEC1_DIV (MEDIA_BASE + 49) +#define CLKID_VDEC1 (MEDIA_BASE + 50) +#define CLKID_VDEC_SEL (MEDIA_BASE + 51) +#define CLKID_VDEC (MEDIA_BASE + 52) +#define CLKID_HCODEC0_SEL (MEDIA_BASE + 53) +#define CLKID_HCODEC0_DIV (MEDIA_BASE + 54) +#define CLKID_HCODEC0 (MEDIA_BASE + 55) +#define CLKID_HCODEC1_SEL (MEDIA_BASE + 56) +#define CLKID_HCODEC1_DIV (MEDIA_BASE + 57) +#define CLKID_HCODEC1 (MEDIA_BASE + 58) +#define CLKID_HCODEC_SEL (MEDIA_BASE + 59) +#define CLKID_HCODEC (MEDIA_BASE + 60) +#define CLKID_HEVC0_SEL (MEDIA_BASE + 61) +#define CLKID_HEVC0_DIV (MEDIA_BASE + 62) +#define CLKID_HEVC0 (MEDIA_BASE + 63) +#define CLKID_HEVC1_SEL (MEDIA_BASE + 64) +#define CLKID_HEVC1_DIV (MEDIA_BASE + 65) +#define CLKID_HEVC1 (MEDIA_BASE + 66) +#define CLKID_HEVC_SEL (MEDIA_BASE + 67) +#define CLKID_HEVC (MEDIA_BASE + 68) +#define CLKID_VC9000E_AXI_SEL (MEDIA_BASE + 69) +#define CLKID_VC9000E_AXI_DIV (MEDIA_BASE + 70) +#define CLKID_VC9000E_AXI (MEDIA_BASE + 71) +#define CLKID_VC9000E_CORE_SEL (MEDIA_BASE + 72) +#define CLKID_VC9000E_CORE_DIV (MEDIA_BASE + 73) +#define CLKID_VC9000E_CORE (MEDIA_BASE + 74) +#define CLKID_HDMITX_SYS_SEL (MEDIA_BASE + 75) +#define CLKID_HDMITX_SYS_DIV (MEDIA_BASE + 76) +#define CLKID_HDMITX_SYS (MEDIA_BASE + 77) +#define CLKID_HDMITX_PRIF_SEL (MEDIA_BASE + 78) +#define CLKID_HDMITX_PRIF_DIV (MEDIA_BASE + 79) +#define CLKID_HDMITX_PRIF (MEDIA_BASE + 80) +#define CLKID_HDMITX_200M_SEL (MEDIA_BASE + 81) +#define CLKID_HDMITX_200M_DIV (MEDIA_BASE + 82) +#define CLKID_HDMITX_200M (MEDIA_BASE + 83) +#define CLKID_HDMITX_AUD_SEL (MEDIA_BASE + 84) +#define CLKID_HDMITX_AUD_DIV (MEDIA_BASE + 85) +#define CLKID_HDMITX_AUD (MEDIA_BASE + 86) +#define CLKID_ENC_HDMI_TX_PNX_SEL (MEDIA_BASE + 87) +#define CLKID_ENC_HDMI_TX_PNX (MEDIA_BASE + 88) +#define CLKID_ENC_HDMI_TX_FE_SEL (MEDIA_BASE + 89) +#define CLKID_ENC_HDMI_TX_FE (MEDIA_BASE + 90) +#define CLKID_ENC_HDMI_TX_PIXEL_SEL (MEDIA_BASE + 91) +#define CLKID_ENC_HDMI_TX_PIXEL (MEDIA_BASE + 92) +#define CLKID_HDMI_TX_PNX_SEL (MEDIA_BASE + 93) +#define CLKID_HDMI_TX_FE_SEL (MEDIA_BASE + 94) +#define CLKID_HDMI_TX_PIXEL_SEL (MEDIA_BASE + 95) +#define CLKID_HDMI_TX_PNX_DIV (MEDIA_BASE + 96) +#define CLKID_HDMI_TX_FE_DIV (MEDIA_BASE + 97) +#define CLKID_HDMI_TX_PIXEL_DIV (MEDIA_BASE + 98) +#define CLKID_HDMI_TX_PNX (MEDIA_BASE + 99) +#define CLKID_HDMI_TX_FE (MEDIA_BASE + 100) +#define CLKID_HDMI_TX_PIXEL (MEDIA_BASE + 101) +#define CLKID_HTX_TMDS_SEL (MEDIA_BASE + 102) +#define CLKID_HTX_TMDS_DIV (MEDIA_BASE + 103) +#define CLKID_HTX_TMDS (MEDIA_BASE + 104) + +#define SYS_BASE (MEDIA_BASE + 105) +#define CLKID_SYS_CLK_DDR (SYS_BASE + 0) +#define CLKID_SYS_CLK_ETHPHY (SYS_BASE + 1) +#define CLKID_SYS_CLK_GPU (SYS_BASE + 2) +#define CLKID_SYS_CLK_VC9000E (SYS_BASE + 3) +#define CLKID_SYS_CLK_AOCPU (SYS_BASE + 4) +#define CLKID_SYS_CLK_AUCPU (SYS_BASE + 5) +#define CLKID_SYS_CLK_DEWARPC (SYS_BASE + 6) +#define CLKID_SYS_CLK_DEWARPB (SYS_BASE + 7) +#define CLKID_SYS_CLK_DEWARPA (SYS_BASE + 8) +#define CLKID_SYS_CLK_AMPIPE_NAND (SYS_BASE + 9) +#define CLKID_SYS_CLK_AMPIPE_ETH (SYS_BASE + 10) +#define CLKID_SYS_CLK_AM2AXI0 (SYS_BASE + 11) +#define CLKID_SYS_CLK_IR_CTRL (SYS_BASE + 12) +#define CLKID_SYS_CLK_SD_EMMC_B (SYS_BASE + 13) +#define CLKID_SYS_CLK_SD_EMMC_A (SYS_BASE + 14) +#define CLKID_SYS_CLK_SD_EMMC_C (SYS_BASE + 15) +#define CLKID_SYS_CLK_SPIFC (SYS_BASE + 16) +#define CLKID_SYS_CLK_MSR_CLK (SYS_BASE + 17) +#define CLKID_SYS_CLK_AUDIO (SYS_BASE + 18) +#define CLKID_SYS_CLK_ETH (SYS_BASE + 19) +#define CLKID_SYS_CLK_UART_A (SYS_BASE + 20) +#define CLKID_SYS_CLK_UART_B (SYS_BASE + 21) +#define CLKID_SYS_CLK_UART_C (SYS_BASE + 22) +#define CLKID_SYS_CLK_UART_D (SYS_BASE + 23) +#define CLKID_SYS_CLK_UART_E (SYS_BASE + 24) +#define CLKID_SYS_CLK_UART_F (SYS_BASE + 25) +#define CLKID_SYS_CLK_DOS (SYS_BASE + 26) +#define CLKID_SYS_CLK_SPICC2 (SYS_BASE + 27) +#define CLKID_SYS_CLK_ACODEC (SYS_BASE + 28) +#define CLKID_SYS_CLK_TS_A55 (SYS_BASE + 29) +#define CLKID_SYS_CLK_SMART_CARD (SYS_BASE + 30) +#define CLKID_SYS_CLK_G2D (SYS_BASE + 31) +#define CLKID_SYS_CLK_SPICC0 (SYS_BASE + 32) +#define CLKID_SYS_CLK_SPICC1 (SYS_BASE + 33) +#define CLKID_SYS_CLK_PCIE (SYS_BASE + 34) +#define CLKID_SYS_CLK_PCIEPHY (SYS_BASE + 35) +#define CLKID_SYS_CLK_USB (SYS_BASE + 36) +#define CLKID_SYS_CLK_PCIE_PHY0 (SYS_BASE + 37) +#define CLKID_SYS_CLK_PCIE_PHY1 (SYS_BASE + 38) +#define CLKID_SYS_CLK_PCIE_PHY2 (SYS_BASE + 39) +#define CLKID_SYS_CLK_I2C_M_A (SYS_BASE + 40) +#define CLKID_SYS_CLK_I2C_M_B (SYS_BASE + 41) +#define CLKID_SYS_CLK_I2C_M_C (SYS_BASE + 42) +#define CLKID_SYS_CLK_I2C_M_D (SYS_BASE + 43) +#define CLKID_SYS_CLK_I2C_M_E (SYS_BASE + 44) +#define CLKID_SYS_CLK_I2C_M_F (SYS_BASE + 45) +#define CLKID_SYS_CLK_TS_GPU (SYS_BASE + 46) +#define CLKID_SYS_CLK_I2C_S_A (SYS_BASE + 47) +#define CLKID_SYS_CLK_CMPR (SYS_BASE + 48) +#define CLKID_SYS_CLK_MMC_PCLK (SYS_BASE + 49) +#define CLKID_SYS_CLK_HDMITX_PCLK (SYS_BASE + 50) +#define CLKID_SYS_CLK_HDMI20_AES_CLK (SYS_BASE + 51) +#define CLKID_SYS_CLK_PCLK_SYS_CPU_APB (SYS_BASE + 52) +#define CLKID_SYS_CLK_CEC (SYS_BASE + 53) +#define CLKID_SYS_CLK_VPU_INTR (SYS_BASE + 54) +#define CLKID_SYS_CLK_SAR_ADC (SYS_BASE + 55) +#define CLKID_SYS_CLK_GIC (SYS_BASE + 56) +#define CLKID_SYS_CLK_TS_NNA (SYS_BASE + 57) +#define CLKID_SYS_CLK_PWM_AB (SYS_BASE + 58) +#define CLKID_SYS_CLK_PWM_CD (SYS_BASE + 59) +#define CLKID_SYS_CLK_PWM_EF (SYS_BASE + 60) +#define CLKID_SYS_CLK_PWM_GH (SYS_BASE + 61) +#define CLKID_SYS_CLK_PWM_IJ (SYS_BASE + 62) +#define CLKID_SYS_CLK_TS_VPU (SYS_BASE + 63) +#define CLKID_SYS_CLK_TS_DOS (SYS_BASE + 64) +#define NR_CLKS (SYS_BASE + 65) + +#endif /* __S5_CLKC_H */ diff --git a/include/dt-bindings/display/meson-drm-ids.h b/include/dt-bindings/display/meson-drm-ids.h index 25c5af26e..b89aa7603 100644 --- a/include/dt-bindings/display/meson-drm-ids.h +++ b/include/dt-bindings/display/meson-drm-ids.h @@ -62,6 +62,9 @@ #define VPP_POSTBLEND_OUT_PORT 18 #define VIDEO1_PORT 19 #define VIDEO2_PORT 20 +#define VPP2_BLOCK 21 +#define HDR3_BLOCK 22 +#define SLICE2PPC_BLOCK 23 /* * vpu block type diff --git a/include/dt-bindings/gpio/meson-t3x-gpio.h b/include/dt-bindings/gpio/meson-t3x-gpio.h new file mode 100644 index 000000000..5630c3640 --- /dev/null +++ b/include/dt-bindings/gpio/meson-t3x-gpio.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_MESON_S5_GPIO_H +#define _DT_BINDINGS_MESON_S5_GPIO_H + +#define GPIOD_0 0 +#define GPIOD_1 1 +#define GPIOD_2 2 +#define GPIOD_3 3 +#define GPIOD_4 4 +#define GPIOD_5 5 +#define GPIOD_6 6 +#define GPIOD_7 7 +#define GPIOD_8 8 +#define GPIOD_9 9 +#define GPIOD_10 10 +#define GPIOD_11 11 + +#define GPIOE_0 12 +#define GPIOE_1 13 +#define GPIOE_2 14 +#define GPIOE_3 15 +#define GPIOE_4 16 + +#define GPIOC_0 17 +#define GPIOC_1 18 +#define GPIOC_2 19 +#define GPIOC_3 20 +#define GPIOC_4 21 +#define GPIOC_5 22 +#define GPIOC_6 23 +#define GPIOC_7 24 + +#define GPIOX_0 25 +#define GPIOX_1 26 +#define GPIOX_2 27 +#define GPIOX_3 28 +#define GPIOX_4 29 +#define GPIOX_5 30 +#define GPIOX_6 31 +#define GPIOX_7 32 +#define GPIOX_8 33 +#define GPIOX_9 34 +#define GPIOX_10 35 +#define GPIOX_11 36 +#define GPIOX_12 37 +#define GPIOX_13 38 +#define GPIOX_14 39 +#define GPIOX_15 40 +#define GPIOX_16 41 +#define GPIOX_17 42 +#define GPIOX_18 43 +#define GPIOX_19 44 + +#define GPIOH_0 45 +#define GPIOH_1 46 +#define GPIOH_2 47 +#define GPIOH_3 48 +#define GPIOH_4 49 +#define GPIOH_5 50 +#define GPIOH_6 51 +#define GPIOH_7 52 +#define GPIOH_8 53 + +#define GPIOZ_0 54 +#define GPIOZ_1 55 +#define GPIOZ_2 56 +#define GPIOZ_3 57 +#define GPIOZ_4 58 +#define GPIOZ_5 59 +#define GPIOZ_6 60 +#define GPIOZ_7 61 +#define GPIOZ_8 62 +#define GPIOZ_9 63 +#define GPIOZ_10 64 +#define GPIOZ_11 65 +#define GPIOZ_12 66 +#define GPIOZ_13 67 +#define GPIOZ_14 68 +#define GPIOZ_15 69 + +#define GPIOT_0 70 +#define GPIOT_1 71 +#define GPIOT_2 72 +#define GPIOT_3 73 +#define GPIOT_4 74 +#define GPIOT_5 75 +#define GPIOT_6 76 +#define GPIOT_7 77 +#define GPIOT_8 78 +#define GPIOT_9 79 +#define GPIOT_10 80 +#define GPIOT_11 81 +#define GPIOT_12 82 +#define GPIOT_13 83 +#define GPIOT_14 84 +#define GPIOT_15 85 +#define GPIOT_16 86 +#define GPIOT_17 87 +#define GPIOT_18 88 +#define GPIOT_19 89 +#define GPIOT_20 90 +#define GPIOT_21 91 +#define GPIOT_22 92 +#define GPIOT_23 93 +#define GPIOT_24 94 + +#define GPIOA_0 95 +#define GPIOA_1 96 +#define GPIOA_2 97 +#define GPIOA_3 98 +#define GPIOA_4 99 +#define GPIOA_5 100 +#define GPIOA_6 101 +#define GPIOA_7 102 +#define GPIOA_8 103 +#define GPIOA_9 104 +#define GPIOA_10 105 +#define GPIO_TEST_N 106 + +#define GPIOB_0 0 +#define GPIOB_1 1 +#define GPIOB_2 2 +#define GPIOB_3 3 +#define GPIOB_4 4 +#define GPIOB_5 5 +#define GPIOB_6 6 +#define GPIOB_7 7 +#define GPIOB_8 8 +#define GPIOB_9 9 +#define GPIOB_10 10 +#define GPIOB_11 11 +#define GPIOB_12 12 + +#endif /* _DT_BINDINGS_MESON_S5_GPIO_H */ diff --git a/include/dt-bindings/power/t3x-pd.h b/include/dt-bindings/power/t3x-pd.h new file mode 100644 index 000000000..4fdb4453a --- /dev/null +++ b/include/dt-bindings/power/t3x-pd.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#define PDID_S5_MALI_0 0 +#define PDID_S5_MALI_1 1 +#define PDID_S5_MALI_2 2 +#define PDID_S5_MALI_TOP 3 +#define PDID_S5_DOS_TOP_WRAP 4 +#define PDID_S5_DOS_VDEC 5 +#define PDID_S5_DOS_HCODEC 6 +#define PDID_S5_DOS_HEVC_TOP 7 +#define PDID_S5_DOS_HEVC_CORE1 8 +#define PDID_S5_USB2 9 +#define PDID_S5_PCIE0 10 +#define PDID_S5_GE2D 11 +#define PDID_S5_VC9000E 12 +#define PDID_S5_VICP 13 +#define PDID_S5_VGE_TOP 14 +#define PDID_S5_VI_CLK1 15 +#define PDID_S5_VI_CLK2 16 +#define PDID_S5_VPU_HDMI 17 +#define PDID_S5_ETH 18 +#define PDID_S5_PCIE1 19 +#define PDID_S5_VPU_DOLBY 20 +#define PDID_S5_USB30 21 +#define PDID_S5_USB31 22 +#define PDID_S5_SDCARD 23 +#define PDID_S5_SDIO 24 +#define PDID_S5_NAND_EMMC 25 +#define PDID_S5_NNA_4T 26 +#define PDID_S5_DMC00 27 +#define PDID_S5_DMC01 28 +#define PDID_S5_NOC_DMC_TOP 29 +#define PDID_S5_DMC10 30 +#define PDID_S5_DMC11 31 +#define PDID_S5_DDRPHY0 32 +#define PDID_S5_DDRPHY1 33 diff --git a/include/dt-bindings/reset/amlogic,meson-t3x-reset.h b/include/dt-bindings/reset/amlogic,meson-t3x-reset.h new file mode 100644 index 000000000..33ed6f6fb --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-t3x-reset.h @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_S5_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_S5_RESET_H + +/* RESET0 */ +/* 0 */ +#define RESET_U3X1_M31_UTMI 1 +#define RESET_U3X0_M31_UTMI 2 +#define RESET_U2DRDX0 3 +/* 4 */ +#define RESET_U3DRDX1 5 +#define RESET_U3DRDX0 6 +/* 7 */ +#define RESET_U2PHY20 8 +#define RESET_U3X1_PCIE_PHY 9 +#define RESET_U3X0_PCIE_PHY 10 +#define RESET_APB_DECODE_DMC 11 +/* 12-15 */ +#define RESET_BRG_SYS_APB_DEC 16 +#define RESET_BRG_VCBUS_DEC 17 +#define RESET_HDMITX_CAPB3 18 +#define RESET_HDMITX 19 +/* 20 */ +#define RESET_GE2D 21 +/* 22 */ +#define RESET_HTXDPHY 23 +#define RESET_HDMI20_AES 24 +/* 25-28 */ +#define RESET_DSC_ENC_CAPB3 29 +#define RESET_DSC_ENC 30 +/* 31 */ + +/* RESET1 */ +#define RESET_AUDIO 32 +#define RESET_DOS 33 +#define RESET_DOS_CAPB3 34 +#define RESET_DDR_APB 35 +#define RESET_DDR 36 +/* 37 */ +#define RESET_U3X1_PCIE_APB 38 +#define RESET_U3X0_PCIE_APB 39 +#define RESET_I_DEBUGB 40 +#define RESET_I_DEBUGA 41 +/* 42-43 */ +#define RESET_PCIE_GEN2_L1 44 +#define RESET_PCIE_B_APB 45 +#define RESET_PCIE_A_APB 46 +#define RESET_ADLA 47 +#define RESET_ETH 48 +/* 49 */ +#define RESET_PCIE_GEN2_L0 50 +/* 51 */ +#define RESET_U3COMBX1 52 +#define RESET_U3COMBX0 53 +#define RESET_U2COMBX0 54 +#define RESET_NNA_NIC_4T 55 +/* 56-58 */ +#define RESET_NNA_NIC_1T 59 +#define RESET_NNA_NIC_MAIN 60 +#define RESET_NNA_NIC_GPV 61 +#define RESET_NNA_NIC_ALL 62 +#define RESET_ACODEC 63 + +/* RESET2 */ +#define RESET_IR_CTRL 64 +#define RESET_TS_A55 65 +/* 66-67 */ +#define RESET_SPICC_2 68 +/* 69-71 */ +#define RESET_SMART_CARD 72 +#define RESET_SPICC_0 73 +#define RESET_SPICC_1 74 +/* 75-79 */ +#define RESET_MSR_CLK 80 +#define RESET_SPIFC 81 +#define RESET_SAR_ADC 82 +/* 83-88 */ +#define RESET_CEC 89 +#define RESET_AFIFO 90 +#define RESET_WATCHDOG 91 +#define RESET_VID_PLL0_DIV 92 +/* 93 */ +#define RESET_TMDS20_DIV 94 +/* 95 */ + +/* RESET3 */ +/* 96-99 */ +#define RESET_PCIE_B_7 100 +#define RESET_PCIE_B_6 101 +#define RESET_PCIE_B_5 102 +#define RESET_PCIE_B_4 103 +#define RESET_PCIE_B_3 104 +#define RESET_PCIE_B_2 105 +#define RESET_PCIE_B_1 106 +#define RESET_PCIE_B_0 107 +#define RESET_PCIE_A_7 108 +#define RESET_PCIE_A_6 109 +#define RESET_PCIE_A_5 110 +#define RESET_PCIE_A_4 111 +#define RESET_PCIE_A_3 112 +#define RESET_PCIE_A_2 113 +#define RESET_PCIE_A_1 114 +#define RESET_PCIE_A_0 115 +#define RESET_VDI6 116 +#define RESET_VID_LOCK 117 +#define RESET_VENC2 118 +#define RESET_VENC1 119 +#define RESET_VENC0 120 +#define RESET_VDAC 121 +#define RESET_RDMA 122 +#define RESET_VIU 123 +#define RESET_VENC 124 +/* 125-126 */ +#define RESET_A55_ACE 127 + +/* RESET4 */ +#define RESET_PWM_AB 128 +#define RESET_PWM_CD 129 +#define RESET_PWM_EF 130 +#define RESET_PWM_GH 131 +#define RESET_PWM_IJ 132 +#define RESET_VID_CMPR 133 +#define RESET_VC9000E_ARESET 134 +#define RESET_VC9000E_CORE 135 +/* 136 */ +#define RESET_VC9000E_APB 137 +#define RESET_UART_A 138 +#define RESET_UART_B 139 +#define RESET_UART_C 140 +#define RESET_UART_D 141 +#define RESET_UART_E 142 +#define RESET_UART_F 143 +#define RESET_I2C_S_A 144 +#define RESET_I2C_M_A 145 +#define RESET_I2C_M_B 146 +#define RESET_I2C_M_C 147 +#define RESET_I2C_M_D 148 +#define RESET_I2C_M_E 149 +#define RESET_I2C_M_F 150 +/* 151 */ +#define RESET_UART_G 152 +#define RESET_SD_EMMC_A 153 +#define RESET_SD_EMMC_B 154 +#define RESET_SD_EMMC_C 155 +#define RESET_TS_GPU 156 +#define RESET_TS_NNA 157 +#define RESET_TS_VPU 158 +#define RESET_TS_DOS 159 + +/* RESET5 */ +/* 160-177 */ +#define RESET_BRG_NICSYS_NPU 178 +#define RESET_BRG_NICSYS_EMMCC 179 +#define RESET_BRG_NICSYS_EMMCB 180 +#define RESET_BRG_NICSYS_EMMCA 181 +/* 182 */ +#define RESET_BRG_NICSYS_PCIE 183 +#define RESET_BRG_NICSYS_SYSCPU 184 +#define RESET_BRG_NICSYS_SYS 185 +/* 186-188 */ +#define RESET_BRG_NICSYS_VAPB 189 +#define RESET_BRG_NICSYS_MAIN 190 +#define RESET_BRG_NICSYS_ALL 191 + +/* RESET6 */ +#define RESET_BRG_AHB_PIPE_NICDOS 192 +#define RESET_BRG_AHB_PIPE_NICNNA 193 +#define RESET_BRG_AHB_PIPE_NICVPU 194 +#define RESET_BRG_AHB_PIPE_NICVGE 195 +/* 196 */ +#define RESET_BRG_AHB_PIPE_NICSYS 197 +#define RESET_BRG_VDEC_DMC_PIPEL 198 +#define RESET_BRG_HEVCF_DMC_PIPEL 199 +/* 200 */ +#define RESET_BRG_AXI_PIPE_NNATODDR 201 +/* 202 */ +#define RESET_BRG_AXI_PIPE_NNATOSYS 203 +#define RESET_BRG_AXI_PIPE_NICVPU 204 +#define RESET_BRG_AXI_PIPE_NICDOS 205 +#define RESET_BRG_AXI_PIPE_NICVGE 206 +#define RESET_BRG_AXI_PIPE_EMMCC 207 +#define RESET_BRG_APB_PIPE_NNA 208 +#define RESET_BRG_APB_PIPE_FDLETOP 209 +#define RESET_BRG_APB_PIPE_NOCDMC 210 +#define RESET_BRG_APB_PIPE_DDR0 211 +#define RESET_BRG_APB_PIPE_DDR1 212 +#define RESET_BRG_APB_PIPE_GE2D 213 +#define RESET_BRG_APB_PIPE_VPU 214 +/* 215-217 */ +#define RESET_BRG_AMPIPE_NAND 218 +#define RESET_BRG_AMPIPE_ETH 219 +/* 220 */ +#define RESET_BRG_AM2AXI0 221 +/* 222-223 */ + +/* RESET7 */ +/* 224-234 */ +#define RESET_BRG_NICVGE_SYS 235 +#define RESET_BRG_NICVGE_VC9000E 236 +#define RESET_BRG_NICVGE_VID_CMPR 237 +#define RESET_BRG_NICVGE_GE2D 238 +/* 239-241 */ +#define RESET_BRG_NICVGE_MAIN 242 +#define RESET_BRG_NICVGE_ALL 243 +/* 244 */ +#define RESET_BRG_NICDOS_SYS 245 +#define RESET_BRG_NICDOS_VDEC 246 +#define RESET_BRG_NICDOS_HEVC 247 +#define RESET_BRG_NICDOS_HCODEC 248 +#define RESET_BRG_NICDOS_MAIN 249 +#define RESET_BRG_NICDOS_ALL 250 +/* 251-252 */ +#define RESET_BRG_NICVPU_SYS 253 +#define RESET_BRG_NICVPU_MAIN 254 +#define RESET_BRG_NICVPU_ALL 255 + +#endif