diff --git a/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h b/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h
index afcc79fa8..ea0c1d615 100644
--- a/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h
+++ b/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h
@@ -111,7 +111,8 @@
 /* 2023.9.14 add support for 240p */
 /* 2023 09.28 add trim flow for txhd2 */
 /* 2023.10.8 t3x some compatibility problem */
-#define RX_VER1 "ver.2023/10/8"
+/* 2023.10.10 fix t3x frl audio problem */
+#define RX_VER1 "ver.2023/10/10"
 
 /* 50ms timer for hdmirx main loop (HDMI_STATE_CHECK_FREQ is 20) */
 
@@ -723,6 +724,7 @@ struct clk_msr {
 	u32 p_clk;
 	u32 tclk;
 	u32 t_clk_pre;
+	u32 fpll_clk;
 };
 
 struct emp_info_s {
diff --git a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c
index 586ed94ae..24753d4b0 100644
--- a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c
+++ b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c
@@ -1764,9 +1764,15 @@ void rx_get_aud_info(struct aud_info_s *audio_info, u8 port)
 		audio_info->n = hdmirx_rd_dwc(DWC_PDEC_ACR_N);
 	}
 	if (audio_info->cts != 0) {
-		audio_info->arc =
-			(rx[rx_info.main_port].clk.tmds_clk / audio_info->cts) *
-			audio_info->n / 128;
+		if (rx[port].var.frl_rate == 0) {
+			audio_info->arc =
+				(rx[rx_info.main_port].clk.tmds_clk / audio_info->cts) *
+				audio_info->n / 128;
+		} else {
+			audio_info->arc =
+				(rx[rx_info.main_port].clk.fpll_clk / audio_info->cts) *
+				audio_info->n / 128;
+		}
 	} else {
 		audio_info->arc = 0;
 	}
@@ -5491,6 +5497,7 @@ void rx_clkmsr_handler(struct work_struct *work)
 				rx[E_PORT2].clk.aud_pll = aud_pll;
 				rx[E_PORT2].clk.p_clk = p_clk;
 				rx[E_PORT2].clk.tclk = meson_clk_measure(49);
+				rx[E_PORT2].clk.fpll_clk = meson_clk_measure(9);
 			}
 				//Port-D
 			if (rx[E_PORT3].cur_5v_sts) {
@@ -5502,6 +5509,7 @@ void rx_clkmsr_handler(struct work_struct *work)
 				rx[E_PORT3].clk.aud_pll = aud_pll;
 				rx[E_PORT3].clk.p_clk = p_clk;
 				rx[E_PORT3].clk.tclk = meson_clk_measure(50);
+				rx[E_PORT3].clk.fpll_clk = meson_clk_measure(11);
 			}
 		}
 		break;
diff --git a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.c b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.c
index 60536f631..b5b94b9a0 100644
--- a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.c
+++ b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.c
@@ -3935,6 +3935,7 @@ void aml_phy_switch_port_t3x(u8 port)
 		hdmirx_wr_top_common(HDMIRX_TOP_SW_RESET_COMMON, 0);
 		break;
 	case 3:
+		data32 = 0;
 		data32 |= (2 << (8 + rx_info.main_port * 2));
 		data32 |= (1 << (rx_info.main_port + 4));
 		hdmirx_wr_top_common(HDMIRX_TOP_FSW_CNTL, data32);
@@ -5384,7 +5385,7 @@ void audio_setting_for_aud21(int frl_rate, u8 port)
 		wr_reg_clk_ctl(T3X_CLKCTRL_AUD21_PLL_CTRL1, 0x8);
 		//aud div
 		hdmirx_wr_bits_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_PI,
-		MSK(2, 12), 0, port);
+		MSK(2, 12), 0x1, port);
 		//Na
 		hdmirx_wr_bits_clk_ctl(T3X_CLKCTRL_AUD21_PLL_CTRL0,
 		_BIT(13), 0);
@@ -5394,12 +5395,25 @@ void audio_setting_for_aud21(int frl_rate, u8 port)
 		//ctsa
 		hdmirx_wr_bits_clk_ctl(T3X_CLKCTRL_AUD21_PLL_CTRL1,
 		_BIT(9), 1);
-	} else if (rx[port].var.frl_rate == FRL_RATE_6G_3LANES ||
-		rx[port].var.frl_rate == FRL_RATE_6G_4LANES) {
+	} else if (rx[port].var.frl_rate == FRL_RATE_6G_3LANES) {
 		wr_reg_clk_ctl(T3X_CLKCTRL_AUD21_PLL_CTRL1, 0x8);
 		//aud div
 		hdmirx_wr_bits_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_PI,
-		MSK(2, 12), 0x1, port);
+		MSK(2, 12), 0x2, port);
+		//Na
+		hdmirx_wr_bits_clk_ctl(T3X_CLKCTRL_AUD21_PLL_CTRL0,
+		_BIT(13), 0);
+		//ctsa
+		hdmirx_wr_bits_clk_ctl(T3X_CLKCTRL_AUD21_PLL_CTRL2,
+		_BIT(19), 1);
+		//ctsa
+		hdmirx_wr_bits_clk_ctl(T3X_CLKCTRL_AUD21_PLL_CTRL1,
+		_BIT(9), 0);
+	} else if (rx[port].var.frl_rate == FRL_RATE_6G_4LANES) {
+		wr_reg_clk_ctl(T3X_CLKCTRL_AUD21_PLL_CTRL1, 0x8);
+		//aud div
+		hdmirx_wr_bits_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_PI,
+		MSK(2, 12), 0x2, port);
 		//Na
 		hdmirx_wr_bits_clk_ctl(T3X_CLKCTRL_AUD21_PLL_CTRL0,
 		_BIT(13), 0);
@@ -5427,7 +5441,7 @@ void audio_setting_for_aud21(int frl_rate, u8 port)
 		wr_reg_clk_ctl(T3X_CLKCTRL_AUD21_PLL_CTRL1, 0x8);
 		//aud div
 		hdmirx_wr_bits_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_PI,
-		MSK(2, 12), 0x2, port);
+		MSK(2, 12), 0x3, port);
 		//Na
 		hdmirx_wr_bits_clk_ctl(T3X_CLKCTRL_AUD21_PLL_CTRL0,
 		_BIT(13), 1);
diff --git a/drivers/media/vin/tvin/vdin/vdin_ctl_t3x.c b/drivers/media/vin/tvin/vdin/vdin_ctl_t3x.c
index 309880aa4..d9e50403e 100644
--- a/drivers/media/vin/tvin/vdin/vdin_ctl_t3x.c
+++ b/drivers/media/vin/tvin/vdin/vdin_ctl_t3x.c
@@ -697,6 +697,10 @@ void vdin_set_top_t3x(struct vdin_dev_s *devp, enum tvin_port_e port,
 		wr_bits(0, VPU_VDIN_HDMI0_CTRL1, 1, 4, 2); /* reg_hskip_mode */
 	if (devp->v_skip_en)
 		wr_bits(0, VPU_VDIN_HDMI0_CTRL1, 1, 7, 1); /* reg_vskip_en */
+	if (input_cfmt == TVIN_YUV420)
+		wr_bits(0, VPU_VDIN_HDMI0_CTRL1, 1, 30, 1);
+	else
+		wr_bits(0, VPU_VDIN_HDMI0_CTRL1, 0, 30, 1);
 }
 
 /*this function will set the bellow parameters of devp: