From 30a8d00a32b792843758686c8c169d7b46de3a11 Mon Sep 17 00:00:00 2001
From: Gaowei Zhao <gaowei.zhao@amlogic.com>
Date: Mon, 30 Oct 2023 17:30:51 +0800
Subject: [PATCH] hdmirx: disable DDR write when suspend [1/1]

PD#SWPL-144124

Problem:
access DDR when suspend, cause resume fail

Solution:
disable EMP hw

Verify:
TXHD2

Change-Id: I0a8d25bd6f0c7c501d5fc507dd7ab8ddafdf3815
Signed-off-by: Gaowei Zhao <gaowei.zhao@amlogic.com>
---
 drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.c |  2 ++
 drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h |  3 +-
 drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c  | 31 +++++++++++++++------
 drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.h  |  1 +
 4 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.c b/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.c
index dab5269de..293025789 100644
--- a/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.c
+++ b/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.c
@@ -4139,6 +4139,7 @@ static int hdmirx_suspend(struct platform_device *pdev, pm_message_t state)
 	 */
 	rx_set_suspend_edid_clk(true);
 	rx_dig_clk_en(0);
+	rx_emp_hw_enable(false);
 	rx_pr("hdmirx: suspend success\n");
 	return 0;
 }
@@ -4149,6 +4150,7 @@ static int hdmirx_resume(struct platform_device *pdev)
 
 	hdevp = platform_get_drvdata(pdev);
 	add_timer(&hdevp->timer);
+	rx_emp_hw_enable(true);
 	rx_dig_clk_en(1);
 //#ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND
 	/* if early suspend not called, need to pw up phy here */
diff --git a/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h b/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h
index 107f4c32d..7010bef55 100644
--- a/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h
+++ b/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h
@@ -140,7 +140,8 @@
 /* 2023.08.28 fix t3x sound issue */
 /* 2023 09 27 reduce phy power */
 /* optimize afifo configuration */
-#define RX_VER2 "ver.2023/10/19"
+/* 2023.11.03 disable DDR access when suspend */
+#define RX_VER2 "ver.2023/11/03"
 
 #define PFIFO_SIZE 160
 #define HDCP14_KEY_SIZE 368
diff --git a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c
index 81911d730..5b0a00c49 100644
--- a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c
+++ b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c
@@ -5306,14 +5306,12 @@ void hdmirx_config_video(u8 port)
 		else//use auto de-repeat
 			hdmirx_wr_bits_top(TOP_VID_CNTL, _BIT(7), 0, port);
 	}
-	if (rx_info.chip_id >= CHIP_ID_T3X) {
-		if (vpcore1_select) {
-			rx[port].emp_vid_idx = 1;
-			rx[port].emp_info = &rx_info.emp_buff_b;
-		} else {
-			rx[port].emp_vid_idx = 0;
-			rx[port].emp_info = &rx_info.emp_buff_a;
-		}
+	if (rx_info.chip_id >= CHIP_ID_T3X && port == rx_info.main_port) {
+		rx[port].emp_vid_idx = 1;
+		rx[port].emp_info = &rx_info.emp_buff_b;
+	} else {
+		rx[port].emp_vid_idx = 0;
+		rx[port].emp_info = &rx_info.emp_buff_a;
 	}
 	rx_sw_reset_t7(2, port);
 	//frl_debug
@@ -6469,6 +6467,23 @@ void aml_eq_eye_monitor(u8 port)
 		aml_eq_eye_monitor_txhd2(0);
 }
 
+/* resume-enable:true, suspend-enable:false */
+void rx_emp_hw_enable(bool enable)
+{
+	u32 data;
+
+	data = hdmirx_rd_top_common(TOP_EMP_CNTL_1);
+	if (enable) {
+		if (rx_info.chip_id == CHIP_ID_T3X)
+			hdmirx_wr_top_common(TOP_EMP1_CNTL_1, data | _BIT(0));
+		hdmirx_wr_top_common(TOP_EMP_CNTL_1, data | _BIT(0));
+	} else {
+		if (rx_info.chip_id == CHIP_ID_T3X)
+			hdmirx_wr_top_common(TOP_EMP1_CNTL_1, data & ~(_BIT(0)));
+		hdmirx_wr_top_common(TOP_EMP_CNTL_1, data & ~(_BIT(0)));
+	}
+}
+
 void rx_emp_to_ddr_init(u8 port)
 {
 	u32 data32;
diff --git a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.h b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.h
index f437a2249..472d35ae7 100644
--- a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.h
+++ b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.h
@@ -3475,5 +3475,6 @@ void hdmirx_wr_bits_top_common_1(u32 addr, u32 mask, u32 value);
 void cor_init(u8 port);
 void vdin_set_black_pattern(bool mute);
 void rx_set_term_value(unsigned char port, bool value);
+void rx_emp_hw_enable(bool enable);
 
 #endif