diff --git a/drivers/memory_debug/ddr_tool/ddr_band_op_t7.c b/drivers/memory_debug/ddr_tool/ddr_band_op_t7.c
index 0c6395d67..c7cf646b2 100644
--- a/drivers/memory_debug/ddr_tool/ddr_band_op_t7.c
+++ b/drivers/memory_debug/ddr_tool/ddr_band_op_t7.c
@@ -203,11 +203,7 @@ static unsigned long t7_get_dmc_freq_quick(struct ddr_bandwidth *db)
 	od1 = (((val >> 19) & 0x1)) == 1 ? 2 : 1;
 	freq = DEFAULT_XTAL_FREQ / 1000;	/* avoid overflow */
 	if (n) {
-		if (db->cpu_type == DMC_TYPE_P1)
-			freq = ((((freq * m) / n) >> od1) / od_div) * 1000 / 2;
-		else
-
-			freq = ((((freq * m) / n) >> od1) / od_div) * 1000;
+		freq = ((((freq * m) / n) >> od1) / od_div) * 1000;
 	}
 
 	return freq;
diff --git a/drivers/memory_debug/ddr_tool/ddr_bandwidth.c b/drivers/memory_debug/ddr_tool/ddr_bandwidth.c
index 3efe15a29..b79544e89 100644
--- a/drivers/memory_debug/ddr_tool/ddr_bandwidth.c
+++ b/drivers/memory_debug/ddr_tool/ddr_bandwidth.c
@@ -181,7 +181,14 @@ static void cal_ddr_usage(struct ddr_bandwidth *db, struct ddr_grant *dg)
 			}
 
 		} else {
-			mbw = (u64)freq * db->bytes_per_cycle * db->dmc_number;
+			/* ddr data bus width = dmc bus width * dmc number.
+			 * After s4 soc, not register to distinguish ddr data bus width,
+			 * default ereryone dmc bus width is 32, but p1 and s5 is 16.
+			 */
+			if (db->cpu_type == DMC_TYPE_P1 || db->cpu_type == DMC_TYPE_S5)
+				mbw = (u64)freq * db->bytes_per_cycle * db->dmc_number / 2;
+			else
+				mbw = (u64)freq * db->bytes_per_cycle * db->dmc_number;
 		}
 		if (!mbw) {
 			pr_emerg("warning: theoretic max bandwidth is zer0\n");