diff --git a/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h b/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h index 0b8c9f1c0..ca976a812 100644 --- a/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h +++ b/drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h @@ -463,7 +463,6 @@ struct rx_aml_phy { int cdr_fr_en_auto; int hyper_gain_en; int eye_height_min; - bool phy_power_off_en; int buf_gain; }; diff --git a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c index 935531093..9acfd753f 100644 --- a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c +++ b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c @@ -6607,6 +6607,11 @@ void rx_phy_power_on(u32 onoff) } } +bool rx_is_phy_power_off(u8 port) +{ + return rx_is_power_off_t3x(port); +} + void aml_phy_iq_skew_monitor(void) { if (rx_info.phy_ver == PHY_VER_T5) diff --git a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.h b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.h index e6e4664e1..a990ce6c6 100644 --- a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.h +++ b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.h @@ -3492,5 +3492,6 @@ void vdin_set_black_pattern(bool mute); void rx_set_term_value(unsigned char port, bool value); void rx_emp_hw_enable(bool enable); bool rx_is_need_edid_reset(u8 port); +bool rx_is_phy_power_off(u8 port); #endif diff --git a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.c b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.c index ab3a6b7f2..3fb3bacaf 100644 --- a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.c +++ b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.c @@ -3787,107 +3787,66 @@ void rx_set_term_value_t3x(unsigned char port, bool value) } } -void aml_phy_power_off_t3x_port0(void) +void aml_phy_power_off_t3x_20(u8 port) { - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PLL_CTRL0, 0x0, E_PORT0); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PLL_CTRL1, 0x0, E_PORT0); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHA_AFE, 0x0, E_PORT0); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHA_DFE, 0x0, E_PORT0); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHD_CDR, 0x0, E_PORT0); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHD_EQ, 0x0, E_PORT0); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHA_MISC1, 0x0, E_PORT0); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHA_MISC2, 0x0, E_PORT0); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHD_STAT, 0x0, E_PORT0); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PLL_CTRL0, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PLL_CTRL1, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHA_AFE, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHA_DFE, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHD_CDR, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHD_EQ, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHA_MISC1, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHA_MISC2, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHD_STAT, 0x0, port); //hdmirx_wr_amlphy_t3x(T3X_HDMIRX_EARCTX_CNTL0, 0x0, E_PORT0); //hdmirx_wr_amlphy_t3x(T3X_HDMIRX_EARCTX_CNTL1, 0x0, E_PORT0); //hdmirx_wr_amlphy_t3x(T3X_HDMIRX_ARC_CNTL, 0x0, E_PORT0); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX_PHY_PROD_TEST0, 0x0, E_PORT0); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX_PHY_PROD_TEST1, 0x0, E_PORT0); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX_PHY_PROD_TEST0, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX_PHY_PROD_TEST1, 0x0, port); } -void aml_phy_power_off_t3x_port1(void) -{ - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PLL_CTRL0, 0x0, E_PORT1); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PLL_CTRL1, 0x0, E_PORT1); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHA_AFE, 0x0, E_PORT1); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHA_DFE, 0x0, E_PORT1); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHD_CDR, 0x0, E_PORT1); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHD_EQ, 0x0, E_PORT1); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHA_MISC1, 0x0, E_PORT1); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHA_MISC2, 0x0, E_PORT1); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX20PHY_DCHD_STAT, 0x0, E_PORT1); - //hdmirx_wr_amlphy_t3x(T3X_HDMIRX_EARCTX_CNTL0, 0x0, E_PORT1); - //hdmirx_wr_amlphy_t3x(T3X_HDMIRX_EARCTX_CNTL1, 0x0, E_PORT1); - //hdmirx_wr_amlphy_t3x(T3X_HDMIRX_ARC_CNTL, 0x0, E_PORT1); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX_PHY_PROD_TEST0, 0x0, E_PORT1); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX_PHY_PROD_TEST1, 0x0, E_PORT1); -} - -void aml_phy_power_off_t3x_port2(void) +void aml_phy_power_off_t3x_21(u8 port) { /* power off phy and pll */ - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL0, 0x0, E_PORT2); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL1, 0x0, E_PORT2); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL2, 0x0, E_PORT2); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL3, 0x0, E_PORT2); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL4, 0x0, E_PORT2); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_MISC0, 0x0, E_PORT2); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_MISC1, 0x0, E_PORT2); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_MISC2, 0x0, E_PORT2); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_AFE, 0x0, E_PORT2); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_DFE, 0x0, E_PORT2); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_PI, 0x0, E_PORT2); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_CTRL, 0x0, E_PORT2); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHD_CDR, 0x0, E_PORT2); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHD_EQ, 0x0, E_PORT2); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL0, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL1, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL2, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL3, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL4, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_MISC0, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_MISC1, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_MISC2, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_AFE, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_DFE, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_PI, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_CTRL, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHD_CDR, 0x0, port); + hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHD_EQ, 0x0, port); /* poweroff port C FPLL */ - wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL0_CTRL0, 0x0); - wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL0_CTRL1, 0x0); - wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL0_CTRL2, 0x0); - wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL0_CTRL3, 0x0); -} + if (port == E_PORT2) { + wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL0_CTRL0, 0x0); + wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL0_CTRL1, 0x0); + wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL0_CTRL2, 0x0); + wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL0_CTRL3, 0x0); + } -void aml_phy_power_off_t3x_port3(void) -{ - /* power off phy and pll */ - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL0, 0x0, E_PORT3); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL1, 0x0, E_PORT3); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL2, 0x0, E_PORT3); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL3, 0x0, E_PORT3); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PLL_CTRL4, 0x0, E_PORT3); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_MISC0, 0x0, E_PORT3); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_MISC1, 0x0, E_PORT3); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_MISC2, 0x0, E_PORT3); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_AFE, 0x0, E_PORT3); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_DFE, 0x0, E_PORT3); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_PI, 0x0, E_PORT3); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHA_CTRL, 0x0, E_PORT3); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHD_CDR, 0x0, E_PORT3); - hdmirx_wr_amlphy_t3x(T3X_HDMIRX21PHY_DCHD_EQ, 0x0, E_PORT3); - /* poweroff port D FPLL */ - wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL1_CTRL0, 0x0); - wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL1_CTRL1, 0x0); - wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL1_CTRL2, 0x0); - wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL1_CTRL3, 0x0); + if (port == E_PORT3) { + wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL1_CTRL0, 0x0); + wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL1_CTRL1, 0x0); + wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL1_CTRL2, 0x0); + wr_reg_clk_ctl(T3X_CLKCTRL_HDMI_PLL1_CTRL3, 0x0); + } } void aml_phy_power_off_t3x(u8 port) { - if (!rx_info.aml_phy.phy_power_off_en) - return; - if (port == E_PORT0) { - aml_phy_power_off_t3x_port0(); - } else if (port == E_PORT1) { - aml_phy_power_off_t3x_port1(); - } else if (port == E_PORT2) { - aml_phy_power_off_t3x_port2(); - } else if (port == E_PORT3) { - aml_phy_power_off_t3x_port3(); + if (port <= E_PORT1) { + aml_phy_power_off_t3x_20(port); + } else if (port <= E_PORT3) { + aml_phy_power_off_t3x_21(port); } else { - aml_phy_power_off_t3x_port0(); - aml_phy_power_off_t3x_port1(); - aml_phy_power_off_t3x_port2(); - aml_phy_power_off_t3x_port3(); + aml_phy_power_off_t3x_20(port); + aml_phy_power_off_t3x_21(port); } } @@ -6112,3 +6071,10 @@ bool is_fsm_ready_t3x(void) hdmi_cec_en != 0xff && is_valid_edid_data(edid_cur); } +bool rx_is_power_off_t3x(u8 port) +{ + if (port <= E_PORT1) + return hdmirx_rd_cor(T3X_HDMIRX20PHY_DCHA_MISC1, port) == 0; + else + return hdmirx_rd_amlphy_t3x(T3X_HDMIRX21PHY_MISC0, port) == 0; +} diff --git a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.h b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.h index fefec6dc1..264a81eec 100644 --- a/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.h +++ b/drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.h @@ -270,10 +270,8 @@ bool s_tmds_transmission_detected(u8 port); bool hdmirx_flt_update_cleared_wait(u32 addr, u8 port); void hdmirx_vga_gain_tuning(u8 port); void rx_set_term_value_t3x(unsigned char port, bool value); -void aml_phy_power_off_t3x_port0(void); -void aml_phy_power_off_t3x_port1(void); -void aml_phy_power_off_t3x_port2(void); -void aml_phy_power_off_t3x_port3(void); +void aml_phy_power_off_t3x_20(u8 port); +void aml_phy_power_off_t3x_21(u8 port); void rx_cor_reset_t3x(u8 port); void cor_debug_t3x(u8 port); void clr_frl_fifo_status(u8 port); @@ -286,6 +284,8 @@ bool rx_get_valid_m_sts(u8 port); void rx_i2c_dbg_monitor(void); void rx_i2c_monitor(u8 sel, u8 smp_mod, u8 trig_mod, u8 dump_mod); void rx_i2c_dump(void); +bool rx_is_power_off_t3x(u8 port); + //void reset_pcs(void); /*function declare end*/ diff --git a/drivers/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c b/drivers/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c index bcfad6a6a..db436d4e2 100644 --- a/drivers/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c +++ b/drivers/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c @@ -309,7 +309,6 @@ void hdmirx_phy_var_init(void) rx_info.aml_phy.eye_height = 5; rx_info.aml_phy.hyper_gain_en = 0; rx_info.aml_phy.eye_height_min = 8; - rx_info.aml_phy.phy_power_off_en = 0; // for t3x 2.1 phy if (rx_info.phy_ver == PHY_VER_T3X && !rx_info.aml_phy.phy_debug_en) { rx_info.aml_phy_21.phy_bwth = 1; @@ -4064,7 +4063,6 @@ void rx_get_global_variable(const char *buf) pr_var(rx_info.aml_phy.tap1_byp, i++); pr_var(rx_info.aml_phy.eq_byp, i++); pr_var(rx_info.aml_phy.long_cable, i++); - pr_var(rx_info.aml_phy.phy_power_off_en, i++); pr_var(rx_info.aml_phy.osc_mode, i++); pr_var(rx_info.aml_phy.pll_div, i++); pr_var(rx_info.aml_phy.eq_fix_val, i++); @@ -4606,9 +4604,6 @@ int rx_set_global_variable(const char *buf, int size) if (set_pr_var(tmpbuf, var_to_str(rx_info.aml_phy.phy_debug_en), &rx_info.aml_phy.phy_debug_en, value)) return pr_var(rx_info.aml_phy.phy_debug_en, index); - if (set_pr_var(tmpbuf, var_to_str(rx_info.aml_phy.phy_power_off_en), - &rx_info.aml_phy.phy_power_off_en, value)) - return pr_var(rx_info.aml_phy.phy_power_off_en, index); if (set_pr_var(tmpbuf, var_to_str(rx_info.aml_phy.enhance_dfe_en_old), &rx_info.aml_phy.enhance_dfe_en_old, value)) return pr_var(rx_info.aml_phy.enhance_dfe_en_old, index); @@ -5037,22 +5032,19 @@ void rx_5v_monitor(void) else tmp_5v = rx_get_hdmi5v_sts(); - if (rx_info.chip_id == CHIP_ID_T3X) { - if (tmp_5v == 0 && pwr_sts == 0) { - aml_phy_power_off_t3x(E_PORT0); - aml_phy_power_off_t3x(E_PORT1); - aml_phy_power_off_t3x(E_PORT2); - aml_phy_power_off_t3x(E_PORT3); - } - for (i = 0; i < rx_info.port_num; i++) { - if (((tmp_5v >> i) & 1) == 0) - aml_phy_power_off_t3x(i); - } - } - if (tmp_5v != pwr_sts) check_cnt++; + for (i = 0; i < rx_info.port_num; i++) { + if (rx_info.chip_id == CHIP_ID_T3X) { + if (rx[i].cur_5v_sts == 0) { + if (rx_get_hpd_sts(i) == 1) + rx_set_cur_hpd(0, 5, i); + if (!rx_is_phy_power_off(i)) + aml_phy_power_off_t3x(i); + } + } + } if (check_cnt >= pow5v_max_cnt) { check_cnt = 0; pwr_sts = tmp_5v; @@ -5067,8 +5059,8 @@ void rx_5v_monitor(void) if (rx_info.chip_id == CHIP_ID_T3X) { if (rx[i].cur_5v_sts == 0) { set_fsm_state(FSM_5V_LOST, i); - rx_set_cur_hpd(0, 5, i); - aml_phy_power_off_t3x(i); + //rx_set_cur_hpd(0, 5, i); + //aml_phy_power_off_t3x(i); //rx_cor_reset_t3x(i); rx[i].tx_type = DEV_UNKNOWN; rx_clr_edid_type(i); @@ -8716,7 +8708,7 @@ void rx_hpd_monitor(void) if (rx_info.main_port_open) port_hpd_rst_flag &= ~(1 << rx_info.main_port); - if (port_hpd_rst_flag & 1) { + if ((port_hpd_rst_flag & 1) && rx[E_PORT0].cur_5v_sts) { if (hpd_wait_cnt0++ > hpd_wait_max) { rx_set_port_hpd(0, 1); hpd_wait_cnt0 = 0; @@ -8725,7 +8717,7 @@ void rx_hpd_monitor(void) } else { hpd_wait_cnt0 = 0; } - if (port_hpd_rst_flag & 2) { + if ((port_hpd_rst_flag & 2) && rx[E_PORT1].cur_5v_sts) { if (hpd_wait_cnt1++ > hpd_wait_max) { rx_set_port_hpd(1, 1); hpd_wait_cnt1 = 0; @@ -8734,7 +8726,7 @@ void rx_hpd_monitor(void) } else { hpd_wait_cnt1 = 0; } - if (port_hpd_rst_flag & 4) { + if ((port_hpd_rst_flag & 4) && rx[E_PORT2].cur_5v_sts) { if (hpd_wait_cnt2++ > hpd_wait_max) { rx_set_port_hpd(2, 1); hpd_wait_cnt2 = 0; @@ -8743,7 +8735,7 @@ void rx_hpd_monitor(void) } else { hpd_wait_cnt2 = 0; } - if (port_hpd_rst_flag & 8) { + if ((port_hpd_rst_flag & 8) && rx[E_PORT3].cur_5v_sts) { if (hpd_wait_cnt3++ > hpd_wait_max) { rx_set_port_hpd(3, 1); hpd_wait_cnt3 = 0;