diff --git a/arch/arm/boot/dts/amlogic/mesont5m.dtsi b/arch/arm/boot/dts/amlogic/mesont5m.dtsi index 59f5f1746..5f60782ff 100644 --- a/arch/arm/boot/dts/amlogic/mesont5m.dtsi +++ b/arch/arm/boot/dts/amlogic/mesont5m.dtsi @@ -1270,7 +1270,7 @@ status = "okay"; reg = <0xfe000000 0x100 /* clk */ 0xfe00c000 0x70 /* pwrctrl */ - 0xff800000 0xa000>; /* vcbus */ + 0xff800000 0xf000>; /* vcbus */ clocks = <&clkc CLKID_VAPB_0>, <&clkc CLKID_VAPB_1>, <&clkc CLKID_VAPB>, diff --git a/arch/arm64/boot/dts/amlogic/mesont5m.dtsi b/arch/arm64/boot/dts/amlogic/mesont5m.dtsi index fd1ab1009..a304319fa 100644 --- a/arch/arm64/boot/dts/amlogic/mesont5m.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesont5m.dtsi @@ -1279,7 +1279,7 @@ status = "okay"; reg = <0x0 0xfe000000 0x0 0x100 /* clk */ 0x0 0xfe00c000 0x0 0x70 /* pwrctrl */ - 0x0 0xff800000 0x0 0xa000>; /* vcbus */ + 0x0 0xff800000 0x0 0xf000>; /* vcbus */ clocks = <&clkc CLKID_VAPB_0>, <&clkc CLKID_VAPB_1>, <&clkc CLKID_VAPB>, diff --git a/drivers/media/common/vpu/vpu.c b/drivers/media/common/vpu/vpu.c index c7e7bfbb1..8e583fd77 100644 --- a/drivers/media/common/vpu/vpu.c +++ b/drivers/media/common/vpu/vpu.c @@ -3106,7 +3106,8 @@ static int vpu_probe(struct platform_device *pdev) vpu_conf.data->chip_type == VPU_CHIP_S7 || vpu_conf.data->chip_type == VPU_CHIP_S7D || vpu_conf.data->chip_type == VPU_CHIP_TXHD2 || - vpu_conf.data->chip_type == VPU_CHIP_T6D) + vpu_conf.data->chip_type == VPU_CHIP_T6D || + vpu_conf.data->chip_type == VPU_CHIP_T5M) ret = init_arb_urgent_table(); if (ret) vpu_power_init(); diff --git a/drivers/media/common/vpu/vpu_arb.c b/drivers/media/common/vpu/vpu_arb.c index 4deaf47c9..fb33ecafd 100644 --- a/drivers/media/common/vpu/vpu_arb.c +++ b/drivers/media/common/vpu/vpu_arb.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include "vpu_reg.h" #include "vpu.h" @@ -59,6 +60,54 @@ static struct vpu_arb_table_s vpu_rdarb_vpu0_2_level1_t7[] = { {} }; +static struct vpu_arb_table_s vpu_rdarb_vpu0_2_level1_t5m_rev_a[] = { + /* vpu module, reg, bit, len, bind_port, name */ + {VPU_ARB_OSD1, VPP_RDARB_MODE, 20, 1, VPU_ARB_VPP_ARB1, "osd1", + /*slv_reg, bit, len*/ + VPP_RDARB_REQEN_SLV, 0, 2}, + {VPU_ARB_OSD2, VPP_RDARB_MODE, 21, 1, VPU_ARB_VPP_ARB1, "osd2", + VPP_RDARB_REQEN_SLV, 2, 2}, + {VPU_ARB_VD1, VPP_RDARB_MODE, 22, 1, VPU_ARB_VPP_ARB0, "vd1", + VPP_RDARB_REQEN_SLV, 4, 2}, + {VPU_ARB_VD2, VPP_RDARB_MODE, 23, 1, VPU_ARB_VPP_ARB0, "vd2", + VPP_RDARB_REQEN_SLV, 6, 2}, + {VPU_ARB_OSD3, VPP_RDARB_MODE, 24, 1, VPU_ARB_VPP_ARB1, "osd3", + VPP_RDARB_REQEN_SLV, 8, 2}, + {VPU_ARB_OSD4, VPP_RDARB_MODE, 25, 1, VPU_ARB_VPP_ARB1, "osd4", + VPP_RDARB_REQEN_SLV, 10, 2}, + {VPU_ARB_AMDOLBY0, VPP_RDARB_MODE, 26, 1, VPU_ARB_VPP_ARB0, "amdolby0", + VPP_RDARB_REQEN_SLV, 12, 2}, + {VPU_ARB_MALI_AFBCD, VPP_RDARB_MODE, 27, 1, VPU_ARB_VPP_ARB1, "mali_afbc", + VPP_RDARB_REQEN_SLV, 14, 2}, + {VPU_ARB_VD3, VPP_RDARB_MODE, 28, 1, VPU_ARB_VPP_ARB0, "vd3", + VPP_RDARB_REQEN_SLV, 16, 2}, + {} +}; + +static struct vpu_arb_table_s vpu_rdarb_vpu0_2_level1_t5m_rev_b[] = { + /* vpu module, reg, bit, len, bind_port, name */ + {VPU_ARB_OSD1, VPP_RDARB_MODE, 20, 1, VPU_ARB_VPP_ARB0, "osd1", + /*slv_reg, bit, len*/ + VPP_RDARB_REQEN_SLV, 0, 2}, + {VPU_ARB_OSD2, VPP_RDARB_MODE, 21, 1, VPU_ARB_VPP_ARB0, "osd2", + VPP_RDARB_REQEN_SLV, 2, 2}, + {VPU_ARB_VD1, VPP_RDARB_MODE, 22, 1, VPU_ARB_VPP_ARB0, "vd1", + VPP_RDARB_REQEN_SLV, 4, 2}, + {VPU_ARB_VD2, VPP_RDARB_MODE, 23, 1, VPU_ARB_VPP_ARB0, "vd2", + VPP_RDARB_REQEN_SLV, 6, 2}, + {VPU_ARB_OSD3, VPP_RDARB_MODE, 24, 1, VPU_ARB_VPP_ARB0, "osd3", + VPP_RDARB_REQEN_SLV, 8, 2}, + {VPU_ARB_OSD4, VPP_RDARB_MODE, 25, 1, VPU_ARB_VPP_ARB0, "osd4", + VPP_RDARB_REQEN_SLV, 10, 2}, + {VPU_ARB_AMDOLBY0, VPP_RDARB_MODE, 26, 1, VPU_ARB_VPP_ARB0, "amdolby0", + VPP_RDARB_REQEN_SLV, 12, 2}, + {VPU_ARB_MALI_AFBCD, VPP_RDARB_MODE, 27, 1, VPU_ARB_VPP_ARB0, "mali_afbc", + VPP_RDARB_REQEN_SLV, 14, 2}, + {VPU_ARB_VD3, VPP_RDARB_MODE, 28, 1, VPU_ARB_VPP_ARB0, "vd3", + VPP_RDARB_REQEN_SLV, 16, 2}, + {} +}; + static struct vpu_arb_table_s vpu_rdarb_vpu0_2_level1_txhd2[] = { /* vpu module, reg, bit, len, bind_port, name */ {VPU_ARB_OSD1, VPP_RDARB_MODE, 20, 1, VPU_ARB_VPP_ARB0, "osd1", @@ -97,6 +146,58 @@ static struct vpu_arb_table_s vpu_rdarb_vpu0_2_level2_t7[] = { {} }; +static struct vpu_arb_table_s vpu_rdarb_vpu0_2_level2_t5m_rev_a[] = { + /* vpu module, reg, bit, len, bind_port, name */ + {VPU_ARB_VPP_ARB0, VPU_RDARB_MODE_L2C1, 16, 1, VPU_READ0, "vpp_arb0", + /*slv_reg, bit, len*/ + VPP_RDARB_REQEN_SLV_L2C1, 0, 2}, + {VPU_ARB_VPP_ARB1, VPU_RDARB_MODE_L2C1, 17, 1, VPU_READ2, "vpp_arb1", + VPP_RDARB_REQEN_SLV_L2C1, 2, 2}, + {VPU_ARB_RDMA_READ, VPU_RDARB_MODE_L2C1, 18, 1, VPU_READ0, "rdma_read", + VPP_RDARB_REQEN_SLV_L2C1, 4, 2}, + {VPU_ARB_VIU2, VPU_RDARB_MODE_L2C1, 19, 1, VPU_READ0, "viu2", + VPP_RDARB_REQEN_SLV_L2C1, 6, 2}, + {VPU_ARB_TCON_P1, VPU_RDARB_MODE_L2C1, 20, 1, VPU_READ0, "tcon_p1", + VPP_RDARB_REQEN_SLV_L2C1, 8, 2}, + {VPU_ARB_TVFE_READ, VPU_RDARB_MODE_L2C1, 21, 1, VPU_READ0, "tvfe_read", + VPP_RDARB_REQEN_SLV_L2C1, 10, 2}, + {VPU_ARB_TCON_P2, VPU_RDARB_MODE_L2C1, 22, 1, VPU_READ0, "tcon_p2", + VPP_RDARB_REQEN_SLV_L2C1, 12, 2}, + {VPU_ARB_LDIM_RD, VPU_RDARB_MODE_L2C1, 23, 1, VPU_READ0, "ldim_rd", + VPP_RDARB_REQEN_SLV_L2C1, 14, 2}, + {VPU_ARB_VDIN_AFBCE_RD, VPU_RDARB_MODE_L2C1, 24, 1, VPU_READ0, "vdin_afbce_rd", + VPP_RDARB_REQEN_SLV_L2C1, 16, 2}, + {VPU_ARB_VPU_DMA, VPU_RDARB_MODE_L2C1, 25, 1, VPU_READ0, "vpu_dma", + VPP_RDARB_REQEN_SLV_L2C1, 18, 2}, + {} +}; + +static struct vpu_arb_table_s vpu_rdarb_vpu0_2_level2_t5m_rev_b[] = { + /* vpu module, reg, bit, len, bind_port, name */ + {VPU_ARB_VPP_ARB0, VPU_RDARB_MODE_L2C1, 16, 1, VPU_READ0, "vpp_arb0", + /*slv_reg, bit, len*/ + VPP_RDARB_REQEN_SLV_L2C1, 0, 2}, + {VPU_ARB_VPP_ARB1, VPU_RDARB_MODE_L2C1, 17, 1, VPU_READ0, "vpp_arb1", + VPP_RDARB_REQEN_SLV_L2C1, 2, 2}, + {VPU_ARB_RDMA_READ, VPU_RDARB_MODE_L2C1, 18, 1, VPU_READ0, "rdma_read", + VPP_RDARB_REQEN_SLV_L2C1, 4, 2}, + {VPU_ARB_VIU2, VPU_RDARB_MODE_L2C1, 19, 1, VPU_READ0, "viu2", + VPP_RDARB_REQEN_SLV_L2C1, 6, 2}, + {VPU_ARB_TCON_P1, VPU_RDARB_MODE_L2C1, 20, 1, VPU_READ0, "tcon_p1", + VPP_RDARB_REQEN_SLV_L2C1, 8, 2}, + {VPU_ARB_TVFE_READ, VPU_RDARB_MODE_L2C1, 21, 1, VPU_READ0, "tvfe_read", + VPP_RDARB_REQEN_SLV_L2C1, 10, 2}, + {VPU_ARB_TCON_P2, VPU_RDARB_MODE_L2C1, 22, 1, VPU_READ0, "tcon_p2", + VPP_RDARB_REQEN_SLV_L2C1, 12, 2}, + {VPU_ARB_LDIM_RD, VPU_RDARB_MODE_L2C1, 23, 1, VPU_READ0, "ldim_rd", + VPP_RDARB_REQEN_SLV_L2C1, 14, 2}, + {VPU_ARB_VDIN_AFBCE_RD, VPU_RDARB_MODE_L2C1, 24, 1, VPU_READ0, "vdin_afbce_rd", + VPP_RDARB_REQEN_SLV_L2C1, 16, 2}, + {VPU_ARB_VPU_DMA, VPU_RDARB_MODE_L2C1, 25, 1, VPU_READ0, "vpu_dma", + VPP_RDARB_REQEN_SLV_L2C1, 18, 2}, + {} +}; + static struct vpu_arb_table_s vpu_rdarb_vpu0_2_level2_txhd2[] = { /* vpu module, reg, bit, len, bind_port, name */ {VPU_ARB_VPP_ARB0, VPU_RDARB_MODE_L2C1, 16, 1, VPU_READ0, "vpp_arb0", @@ -1508,9 +1609,24 @@ int init_arb_urgent_table(void) { int i; if (vpu_conf.data->chip_type == VPU_CHIP_T7 || - vpu_conf.data->chip_type == VPU_CHIP_S6) { - vpu_rdarb_vpu0_2_level1_tables = vpu_rdarb_vpu0_2_level1_t7; - vpu_rdarb_vpu0_2_level2_tables = vpu_rdarb_vpu0_2_level2_t7; + vpu_conf.data->chip_type == VPU_CHIP_S6 || + vpu_conf.data->chip_type == VPU_CHIP_T5M) { + if (vpu_conf.data->chip_type == VPU_CHIP_T5M) { + /* + * T5M revA osd to dmc1 + * T5M revB osd to dmc0 + */ + if (is_meson_rev_a()) { + vpu_rdarb_vpu0_2_level1_tables = vpu_rdarb_vpu0_2_level1_t5m_rev_a; + vpu_rdarb_vpu0_2_level2_tables = vpu_rdarb_vpu0_2_level2_t5m_rev_a; + } else { + vpu_rdarb_vpu0_2_level1_tables = vpu_rdarb_vpu0_2_level1_t5m_rev_b; + vpu_rdarb_vpu0_2_level2_tables = vpu_rdarb_vpu0_2_level2_t5m_rev_b; + } + } else { + vpu_rdarb_vpu0_2_level1_tables = vpu_rdarb_vpu0_2_level1_t7; + vpu_rdarb_vpu0_2_level2_tables = vpu_rdarb_vpu0_2_level2_t7; + } vpu_rdarb_vpu1_tables = vpu_rdarb_vpu1_t7; vpu_wrarb_vpu0_tables = vpu_wrarb_vpu0_t7; vpu_wrarb_vpu1_tables = vpu_wrarb_vpu1_t7; diff --git a/drivers/media/osd/osd_hw.c b/drivers/media/osd/osd_hw.c index 30dddee8f..ea6ea488c 100644 --- a/drivers/media/osd/osd_hw.c +++ b/drivers/media/osd/osd_hw.c @@ -15164,7 +15164,9 @@ static void osd_hw_init(u32 logo_loaded) osd_hw.osd_meson_dev.cpu_id != __MESON_CPU_MAJOR_ID_S7D && osd_hw.osd_meson_dev.cpu_id != - __MESON_CPU_MAJOR_ID_S6) + __MESON_CPU_MAJOR_ID_S6 && + osd_hw.osd_meson_dev.cpu_id != + __MESON_CPU_MAJOR_ID_T5M) osd_set_two_ports(true); if (osd_dev_hw.prevsync_support) { u32 vpp0_pre_go_field = 0;