diff --git a/drivers/media/enhancement/amdolby_vision/amdv.c b/drivers/media/enhancement/amdolby_vision/amdv.c index 9f0f2a647..5097cceee 100644 --- a/drivers/media/enhancement/amdolby_vision/amdv.c +++ b/drivers/media/enhancement/amdolby_vision/amdv.c @@ -1487,14 +1487,14 @@ bool is_hdr10_src_primary_changed(void) static bool is_match_amdv_attr(void) { - struct hdmitx_dev *hdev = get_hdmitx_device(); + const struct vinfo_s *vinfo = get_current_vinfo(); if ((dolby_vision_ll_policy == DOLBY_VISION_LL_DISABLE && - hdev->para->cs == HDMI_COLORSPACE_YUV444 && - hdev->para->cd == COLORDEPTH_24B) || + vinfo->cs == HDMI_COLORSPACE_YUV444 && + vinfo->cd == COLORDEPTH_24B) || (dolby_vision_ll_policy == DOLBY_VISION_LL_YUV422 && - hdev->para->cs == HDMI_COLORSPACE_YUV422 && - hdev->para->cd == COLORDEPTH_36B)) + vinfo->cs == HDMI_COLORSPACE_YUV422 && + vinfo->cd == COLORDEPTH_36B)) return true; else return false; diff --git a/drivers/media/vout/hdmitx/hdmi_common/hdmi_parameters.c b/drivers/media/vout/hdmitx/hdmi_common/hdmi_parameters.c index e5b59d281..3881c0fd1 100644 --- a/drivers/media/vout/hdmitx/hdmi_common/hdmi_parameters.c +++ b/drivers/media/vout/hdmitx/hdmi_common/hdmi_parameters.c @@ -3151,7 +3151,7 @@ static struct hdmi_format_para *all_fmt_paras[] = { NULL, }; -struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic) +const struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic) { int i; @@ -3315,7 +3315,7 @@ static void hdmi_parse_attr(struct hdmi_format_para *para, char const *name) * or 3840x2160p60hz, 2160p60hz * or 3840x2160p60hz420, 2160p60hz420 (Y420 mode) */ -struct hdmi_format_para *hdmi_get_fmt_name(char const *name, char const *attr) +const struct hdmi_format_para *hdmi_get_fmt_name(char const *name, char const *attr) { int i; char *lname; @@ -3353,6 +3353,7 @@ struct hdmi_format_para *hdmi_get_fmt_name(char const *name, char const *attr) hdmi_parse_attr(para, name); hdmi_parse_attr(para, attr); } + if (strstr(name, "420")) para->cs = HDMI_COLORSPACE_YUV420; diff --git a/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c b/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c index 613d133e5..271716eac 100644 --- a/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c +++ b/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c @@ -2520,7 +2520,7 @@ bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev, if (para->cs != HDMI_COLORSPACE_RGB) return 0; for (i = 0; vesa_t[i] && i < VESA_MAX_TIMING; i++) { - struct hdmi_format_para *param = NULL; + const struct hdmi_format_para *param = NULL; param = hdmi_get_fmt_paras(vesa_t[i]); if (param) { @@ -2688,7 +2688,7 @@ enum hdmi_vic hdmitx_edid_get_VIC(struct hdmitx_dev *hdev, struct rx_cap *prxcap = &hdev->tx_comm.rxcap; int j; enum hdmi_vic vic = hdmitx_edid_vic_tab_map_vic(disp_mode); - struct hdmi_format_para *para = NULL; + const struct hdmi_format_para *para = NULL; enum hdmi_vic *vesa_t = &hdev->tx_comm.rxcap.vesa_timing[0]; enum hdmi_vic vesa_vic; diff --git a/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c b/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c index 4361cc2e9..ef9fa5ecf 100644 --- a/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c +++ b/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c @@ -98,6 +98,7 @@ static void clear_rx_vinfo(struct hdmitx_dev *hdev); static void edidinfo_attach_to_vinfo(struct hdmitx_dev *hdev); static void edidinfo_detach_to_vinfo(struct hdmitx_dev *hdev); static void update_current_para(struct hdmitx_dev *hdev); +static void update_current_para_from_mode(struct hdmitx_dev *hdev, const char *name); static bool is_cur_tmds_div40(struct hdmitx_dev *hdev); static void hdmitx_resend_div40(struct hdmitx_dev *hdev); static unsigned int hdmitx_get_frame_duration(void); @@ -403,16 +404,6 @@ static void hdmitx_early_suspend(struct early_suspend *h) mutex_unlock(&hdmimode_mutex); } -static int hdmitx_is_hdmi_vmode(char *mode_name) -{ - enum hdmi_vic vic = hdmitx_edid_vic_tab_map_vic(mode_name); - - if (vic == HDMI_UNKNOWN) - return 0; - - return 1; -} - static void hdmitx_late_resume(struct early_suspend *h) { const struct vinfo_s *info = hdmitx_get_current_vinfo(NULL); @@ -421,9 +412,6 @@ static void hdmitx_late_resume(struct early_suspend *h) mutex_lock(&hdmimode_mutex); - if (info && (hdmitx_is_hdmi_vmode(info->name) == 1)) - hdev->tx_hw.cntlmisc(&hdev->tx_hw, MISC_HPLL_FAKE, 0); - hdev->hpd_lock = 0; /* update status for hpd and switch/state */ hpd_state = !!(hdev->tx_hw.cntlmisc(&hdev->tx_hw, MISC_HPD_GPI_ST, 0)); @@ -466,6 +454,7 @@ static void hdmitx_late_resume(struct early_suspend *h) extcon_set_state(hdmitx_extcon_hdmi, EXTCON_DISP_HDMI, 1); } hdev->suspend_flag = false; + extcon_set_state_sync(hdmitx_extcon_hdmi, EXTCON_DISP_HDMI, hdev->tx_comm.hpd_state); hdmitx_set_uevent(HDMITX_HPD_EVENT, hdev->tx_comm.hpd_state); @@ -653,7 +642,7 @@ static void edidinfo_attach_to_vinfo(struct hdmitx_dev *hdev) mutex_lock(&getedid_mutex); hdrinfo_to_vinfo(&info->hdr_info, hdev); - if (hdev->para->cd == COLORDEPTH_24B) + if (hdev->tx_comm.fmt_para.cd == COLORDEPTH_24B) memset(&info->hdr_info, 0, sizeof(struct hdr_info)); rxlatency_to_vinfo(info, &hdev->tx_comm.rxcap); hdmitx_vdev.dv_info = &hdmitx_device.tx_comm.rxcap.dv_info; @@ -680,9 +669,9 @@ static int set_disp_mode_auto(void) struct vinfo_s *info = NULL; struct hdmitx_dev *hdev = &hdmitx_device; struct hdmitx_common *tx_comm = &hdev->tx_comm; - struct hdmi_format_para *para = NULL; unsigned char mode[32]; enum hdmi_vic vic = HDMI_UNKNOWN; + struct hdmi_format_para *para = &tx_comm->fmt_para; mutex_lock(&hdmimode_mutex); @@ -731,7 +720,9 @@ static int set_disp_mode_auto(void) hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONF_CLR_AVI_PACKET, 0); hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONF_CLR_VSDB_PACKET, 0); hdev->tx_hw.cntlmisc(&hdev->tx_hw, MISC_TMDS_PHY_OP, TMDS_PHY_DISABLE); - hdev->para = hdmi_get_fmt_name("invalid", tx_comm->fmt_attr); + + update_current_para_from_mode(hdev, "invalid"); + if (hdev->cedst_policy) cancel_delayed_work(&hdev->work_cedst); mutex_unlock(&hdmimode_mutex); @@ -764,9 +755,7 @@ static int set_disp_mode_auto(void) strcat(mode, "420"); } - para = hdmi_get_fmt_name(mode, tx_comm->fmt_attr); - hdev->para = para; - + update_current_para_from_mode(hdev, mode); if (!hdmitx_edid_check_valid_mode(hdev, para)) { pr_err("check failed vic: %d\n", para->vic); mutex_unlock(&hdmimode_mutex); @@ -774,6 +763,18 @@ static int set_disp_mode_auto(void) } vic = hdmitx_edid_get_VIC(hdev, mode, 1); + if (vic != HDMI_0_UNKNOWN && vic != para->vic) { + const struct hdmi_format_para *tmp = hdmi_get_fmt_paras(vic); + enum hdmi_color_depth cd = tx_comm->fmt_para.hdmitx_vinfo.cd; + enum hdmi_colorspace cs = tx_comm->fmt_para.hdmitx_vinfo.cs; + + pr_info("%s update (%d) to new vic (%d-%s)\n", + __func__, para->vic, vic, tmp->sname); + memcpy(para, tmp, sizeof(struct hdmi_format_para)); + para->cs = cs; + para->cd = cd; + } + if (strncmp(info->name, "2160p30hz", strlen("2160p30hz")) == 0) { vic = HDMI_4k2k_30; } else if (strncmp(info->name, "2160p25hz", @@ -1528,7 +1529,7 @@ static void hdmitx_set_drm_pkt(struct master_display_info_s *data) if (hdmitx_dv_en()) { update_current_para(hdev); hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONF_AVI_RGBYCC_INDIC, - hdev->para->cs); + hdev->tx_comm.fmt_para.cs); /* if using VSIF/DOVI, then only clear DV_VS10_SIG, else disable VSIF */ if (hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONF_CLR_DV_VS10_SIG, 0) == 0) hdev->hwop.setpacket(HDMI_PACKET_VEND, NULL, NULL); @@ -1572,24 +1573,26 @@ static void hdmitx_set_drm_pkt(struct master_display_info_s *data) /* currently output y444,8bit or rgb,8bit, if exit playing, * then switch back to 8bit mode */ - if (hdev->para->cs == HDMI_COLORSPACE_YUV444 && - hdev->para->cd == COLORDEPTH_24B) { + if (hdev->tx_comm.fmt_para.cs == HDMI_COLORSPACE_YUV444 && + hdev->tx_comm.fmt_para.cd == COLORDEPTH_24B) { /* hdev->hwop.cntlconfig(hdev, */ /* CONF_AVI_RGBYCC_INDIC, */ /* COLORSPACE_YUV444); */ hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONFIG_CSC, CSC_Y444_8BIT | CSC_UPDATE_AVI_CS); pr_info("%s: switch back to cs:%d, cd:%d\n", - __func__, hdev->para->cs, hdev->para->cd); - } else if (hdev->para->cs == HDMI_COLORSPACE_RGB && - hdev->para->cd == COLORDEPTH_24B) { + __func__, hdev->tx_comm.fmt_para.cs, + hdev->tx_comm.fmt_para.cd); + } else if (hdev->tx_comm.fmt_para.cs == HDMI_COLORSPACE_RGB && + hdev->tx_comm.fmt_para.cd == COLORDEPTH_24B) { /* hdev->hwop.cntlconfig(hdev, */ /* CONF_AVI_RGBYCC_INDIC, */ /* COLORSPACE_RGB444); */ hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONFIG_CSC, CSC_RGB_8BIT | CSC_UPDATE_AVI_CS); pr_info("%s: switch back to cs:%d, cd:%d\n", - __func__, hdev->para->cs, hdev->para->cd); + __func__, hdev->tx_comm.fmt_para.cs, + hdev->tx_comm.fmt_para.cd); } spin_unlock_irqrestore(&hdev->edid_spinlock, flags); return; @@ -1720,9 +1723,9 @@ static void hdmitx_set_drm_pkt(struct master_display_info_s *data) /* currently output y444,8bit or rgb,8bit, and EDID * support Y422, then switch to y422,12bit mode */ - if ((hdev->para->cs == HDMI_COLORSPACE_YUV444 || - hdev->para->cs == HDMI_COLORSPACE_RGB) && - hdev->para->cd == COLORDEPTH_24B && + if ((hdev->tx_comm.fmt_para.cs == HDMI_COLORSPACE_YUV444 || + hdev->tx_comm.fmt_para.cs == HDMI_COLORSPACE_RGB) && + hdev->tx_comm.fmt_para.cd == COLORDEPTH_24B && (hdev->tx_comm.rxcap.native_Mode & (1 << 4))) { /* hdev->hwop.cntlconfig(hdev,*/ /* CONF_AVI_RGBYCC_INDIC, */ @@ -1739,7 +1742,6 @@ static void update_current_para(struct hdmitx_dev *hdev) { struct vinfo_s *info = NULL; unsigned char mode[32]; - struct hdmitx_common *tx_comm = &hdev->tx_comm; info = hdmitx_get_current_vinfo(NULL); if (!info) @@ -1747,11 +1749,26 @@ static void update_current_para(struct hdmitx_dev *hdev) memset(mode, 0, sizeof(mode)); strncpy(mode, info->name, sizeof(mode) - 1); - if (strstr(tx_comm->fmt_attr, "420")) { + if (strstr(hdev->tx_comm.fmt_attr, "420")) { if (!strstr(mode, "420")) strncat(mode, "420", sizeof(mode) - strlen("420") - 1); } - hdev->para = hdmi_get_fmt_name(mode, tx_comm->fmt_attr); + + update_current_para_from_mode(hdev, mode); +} + +static void update_current_para_from_mode(struct hdmitx_dev *hdev, const char *name) +{ + struct hdmitx_common *tx_comm = &hdev->tx_comm; + const struct hdmi_format_para *para; + + para = hdmi_get_fmt_name(name, tx_comm->fmt_attr); + pr_info("get_fmt_para from %s -> %d,%s\n", name, para->vic, + para->sname ? para->sname : para->name); + + memcpy(&tx_comm->fmt_para, para, sizeof(struct hdmi_format_para)); + tx_comm->fmt_para.hdmitx_vinfo.cs = para->cs; + tx_comm->fmt_para.hdmitx_vinfo.cd = para->cd; } struct vsif_debug_save vsif_debug_info; @@ -1763,6 +1780,7 @@ static void hdmitx_set_vsif_pkt(enum eotf_type type, bool signal_sdr) { struct hdmitx_dev *hdev = &hdmitx_device; + struct hdmitx_common *tx_comm = &hdmitx_device.tx_comm; struct dv_vsif_para para = {0}; unsigned char VEN_HB[3] = {0x81, 0x01}; unsigned char VEN_DB1[24] = {0x00}; @@ -1926,7 +1944,7 @@ static void hdmitx_set_vsif_pkt(enum eotf_type type, pr_info("hdmitx: H14b VSIF, switching signal to SDR\n"); update_current_para(hdev); hdev->tx_hw.cntlconfig(&hdev->tx_hw, - CONF_AVI_RGBYCC_INDIC, hdev->para->cs); + CONF_AVI_RGBYCC_INDIC, tx_comm->fmt_para.cs); hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONF_AVI_Q01, RGB_RANGE_LIM); hdev->tx_hw.cntlconfig(&hdev->tx_hw, @@ -2066,10 +2084,10 @@ static void hdmitx_set_vsif_pkt(enum eotf_type type, pr_info("hdmitx: Dolby VSIF, switching signal to SDR\n"); update_current_para(hdev); pr_info("vic:%d, cd:%d, cs:%d, cr:%d\n", - hdev->para->vic, hdev->para->cd, - hdev->para->cs, hdev->para->cr); + tx_comm->fmt_para.timing.vic, tx_comm->fmt_para.cd, + tx_comm->fmt_para.cs, tx_comm->fmt_para.cr); hdev->tx_hw.cntlconfig(&hdev->tx_hw, - CONF_AVI_RGBYCC_INDIC, hdev->para->cs); + CONF_AVI_RGBYCC_INDIC, tx_comm->fmt_para.cs); hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONF_AVI_Q01, RGB_RANGE_DEFAULT); hdev->tx_hw.cntlconfig(&hdev->tx_hw, @@ -2468,44 +2486,43 @@ static ssize_t config_show(struct device *dev, pos += snprintf(buf + pos, PAGE_SIZE, "cur_video_param->VIC=%d\n", hdev->cur_video_param->VIC); - if (hdev->para) { - switch (hdev->para->cd) { - case COLORDEPTH_24B: - conf = "8bit"; - break; - case COLORDEPTH_30B: - conf = "10bit"; - break; - case COLORDEPTH_36B: - conf = "12bit"; - break; - case COLORDEPTH_48B: - conf = "16bit"; - break; - default: - conf = "reserved"; - } - pos += snprintf(buf + pos, PAGE_SIZE, "colordepth: %s\n", - conf); - switch (hdev->para->cs) { - case HDMI_COLORSPACE_RGB: - conf = "RGB"; - break; - case HDMI_COLORSPACE_YUV422: - conf = "422"; - break; - case HDMI_COLORSPACE_YUV444: - conf = "444"; - break; - case HDMI_COLORSPACE_YUV420: - conf = "420"; - break; - default: - conf = "reserved"; - } - pos += snprintf(buf + pos, PAGE_SIZE, "colorspace: %s\n", - conf); + + switch (hdev->tx_comm.fmt_para.cd) { + case COLORDEPTH_24B: + conf = "8bit"; + break; + case COLORDEPTH_30B: + conf = "10bit"; + break; + case COLORDEPTH_36B: + conf = "12bit"; + break; + case COLORDEPTH_48B: + conf = "16bit"; + break; + default: + conf = "reserved"; } + pos += snprintf(buf + pos, PAGE_SIZE, "colordepth: %s\n", + conf); + switch (hdev->tx_comm.fmt_para.cs) { + case HDMI_COLORSPACE_RGB: + conf = "RGB"; + break; + case HDMI_COLORSPACE_YUV422: + conf = "422"; + break; + case HDMI_COLORSPACE_YUV444: + conf = "444"; + break; + case HDMI_COLORSPACE_YUV420: + conf = "420"; + break; + default: + conf = "reserved"; + } + pos += snprintf(buf + pos, PAGE_SIZE, "colorspace: %s\n", + conf); switch (hdev->tx_aud_cfg) { case 0: @@ -2921,7 +2938,7 @@ static int is_4k50_fmt(char *mode) } /* check the resolution is over 1920x1080 or not */ -static bool is_over_1080p(struct hdmi_format_para *para) +static bool is_over_1080p(const struct hdmi_format_para *para) { if (!para) return 1; @@ -2933,7 +2950,7 @@ static bool is_over_1080p(struct hdmi_format_para *para) } /* check the fresh rate is over 60hz or not */ -static bool is_over_60hz(struct hdmi_format_para *para) +static bool is_over_60hz(const struct hdmi_format_para *para) { if (!para) return 1; @@ -2945,7 +2962,7 @@ static bool is_over_60hz(struct hdmi_format_para *para) } /* test current vic is over 150MHz or not */ -static bool is_over_pixel_150mhz(struct hdmi_format_para *para) +static bool is_over_pixel_150mhz(const struct hdmi_format_para *para) { if (!para) return 1; @@ -2958,7 +2975,7 @@ static bool is_over_pixel_150mhz(struct hdmi_format_para *para) bool validate_mode_refreshrate(enum hdmi_vic vic, u32 maxfreq) { - struct hdmi_format_para *para = hdmi_get_fmt_paras(vic); + const struct hdmi_format_para *para = hdmi_get_fmt_paras(vic); /* if the vic equals to HDMI_UNKNOWN or VESA, * then create it as over limited @@ -2977,7 +2994,7 @@ bool validate_mode_refreshrate(enum hdmi_vic vic, u32 maxfreq) bool is_vic_over_limited_1080p(enum hdmi_vic vic) { - struct hdmi_format_para *para = hdmi_get_fmt_paras(vic); + const struct hdmi_format_para *para = hdmi_get_fmt_paras(vic); /* if the vic equals to HDMI_UNKNOWN or VESA, * then create it as over limited @@ -3113,7 +3130,7 @@ static ssize_t vesa_cap_show(struct device *dev, char *buf) { int i; - struct hdmi_format_para *para = NULL; + const struct hdmi_format_para *para = NULL; enum hdmi_vic *vesa_t = &hdmitx_device.tx_comm.rxcap.vesa_timing[0]; int pos = 0; @@ -4905,8 +4922,8 @@ static ssize_t hdmitx_basic_config_show(struct device *dev, pos += snprintf(buf + pos, PAGE_SIZE, "cur_video_param->VIC=%d\n", hdev->cur_video_param->VIC); - if (hdev->para) { - switch (hdev->para->cd) { + if (hdev->tx_comm.fmt_para.timing.vic != HDMI_0_UNKNOWN) { + switch (hdev->tx_comm.fmt_para.cd) { case COLORDEPTH_24B: conf = "8bit"; break; @@ -4924,7 +4941,7 @@ static ssize_t hdmitx_basic_config_show(struct device *dev, } pos += snprintf(buf + pos, PAGE_SIZE, "colordepth: %s\n", conf); - switch (hdev->para->cs) { + switch (hdev->tx_comm.fmt_para.cs) { case HDMI_COLORSPACE_RGB: conf = "RGB"; break; @@ -5765,12 +5782,13 @@ static int hdmitx_vmode_is_supported(enum vmode_e mode, void *data) static int hdmitx_module_disable(enum vmode_e cur_vmod, void *data) { struct hdmitx_dev *hdev = &hdmitx_device; - struct hdmitx_common *tx_comm = &hdev->tx_comm; hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONF_CLR_AVI_PACKET, 0); hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONF_CLR_VSDB_PACKET, 0); hdev->tx_hw.cntlmisc(&hdev->tx_hw, MISC_TMDS_PHY_OP, TMDS_PHY_DISABLE); - hdev->para = hdmi_get_fmt_name("invalid", tx_comm->fmt_attr); + + update_current_para_from_mode(hdev, "invalid"); + hdmitx_validate_vmode("null", 0, NULL); if (hdev->cedst_policy) cancel_delayed_work(&hdev->work_cedst); @@ -6477,7 +6495,7 @@ int tv_audio_support(int type, struct rx_cap *prxcap) static bool is_cur_tmds_div40(struct hdmitx_dev *hdev) { struct hdmitx_common *tx_comm = &hdev->tx_comm; - struct hdmi_format_para *para1 = NULL; + const struct hdmi_format_para *para1 = NULL; struct hdmi_format_para *para2 = NULL; unsigned int act_clk = 0; @@ -6603,17 +6621,18 @@ static int get_dt_vend_init_data(struct device_node *np, static void hdmitx_fmt_attr(struct hdmitx_dev *hdev) { struct hdmitx_common *tx_comm = &hdev->tx_comm; + struct hdmi_format_para *para = &tx_comm->fmt_para; if (strlen(tx_comm->fmt_attr) >= 8) { pr_debug(SYS "fmt_attr %s\n", tx_comm->fmt_attr); return; } - if (hdev->para->cd == COLORDEPTH_RESERVED && - hdev->para->cs == HDMI_COLORSPACE_RESERVED6) { + if (para->cd == COLORDEPTH_RESERVED && + para->cs == HDMI_COLORSPACE_RESERVED6) { strcpy(tx_comm->fmt_attr, "default"); } else { memset(tx_comm->fmt_attr, 0, sizeof(tx_comm->fmt_attr)); - switch (hdev->para->cs) { + switch (para->cs) { case HDMI_COLORSPACE_RGB: memcpy(tx_comm->fmt_attr, "rgb,", 5); break; @@ -6629,7 +6648,7 @@ static void hdmitx_fmt_attr(struct hdmitx_dev *hdev) default: break; } - switch (hdev->para->cd) { + switch (para->cd) { case COLORDEPTH_24B: strcat(tx_comm->fmt_attr, "8bit"); break; @@ -6851,8 +6870,6 @@ static void hdmitx_hdr_state_init(struct hdmitx_dev *hdev) static int amhdmitx_device_init(struct hdmitx_dev *hdmi_dev, struct hdmitx_boot_param *params) { - struct hdmitx_common *tx_comm = &hdmi_dev->tx_comm; - if (!hdmi_dev) return 1; @@ -6863,8 +6880,8 @@ static int amhdmitx_device_init(struct hdmitx_dev *hdmi_dev, struct hdmitx_boot_ hdmitx_device.physical_addr = 0xffff; /* init para for NULL protection */ - hdmitx_device.para = hdmi_get_fmt_name("invalid", - tx_comm->fmt_attr); + update_current_para_from_mode(hdmi_dev, "invalid"); + hdmitx_device.hdmi_last_hdr_mode = 0; hdmitx_device.hdmi_current_hdr_mode = 0; /* hdr/vsif packet status init, no need to get actual status, @@ -7800,8 +7817,8 @@ bool drm_hdmitx_chk_mode_attr_sup(char *mode, char *attr) static int drm_hdmitx_get_timing_para(int vic, struct drm_hdmitx_timing_para *para) { - struct hdmi_format_para *hdmi_para; - struct hdmi_cea_timing *timing; + const struct hdmi_format_para *hdmi_para; + const struct hdmi_cea_timing *timing; hdmi_para = hdmi_get_fmt_paras(vic); if (hdmi_para->vic == HDMI_UNKNOWN) diff --git a/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_scdc.c b/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_scdc.c index 74e2057a3..d90d774e8 100644 --- a/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_scdc.c +++ b/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_scdc.c @@ -24,7 +24,7 @@ void scdc_config(struct hdmitx_dev *hdev) /* if change to > 3.4Gbps mode, or change from > 3.4Gbps * to < 3.4Gbps mode, need to forcely update clk ratio */ - if (hdev->para->tmds_clk_div40) + if (hdev->tx_comm.fmt_para.tmds_clk_div40) scdc_wr_sink(TMDS_CFG, 3); else if (hdev->tx_comm.rxcap.scdc_present || hdev->pre_tmds_clk_div40) diff --git a/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c b/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c index 5052bca8c..2d20f92d0 100644 --- a/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c +++ b/drivers/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c @@ -931,6 +931,7 @@ static int is_dvi_device(struct rx_cap *prxcap) int hdmitx_set_display(struct hdmitx_dev *hdev, enum hdmi_vic videocode) { + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; struct hdmitx_vidpara *param = NULL; enum hdmi_vic vic; int i, ret = -1; @@ -982,13 +983,13 @@ int hdmitx_set_display(struct hdmitx_dev *hdev, enum hdmi_vic videocode) } if (param->color == HDMI_COLORSPACE_RGB) { - hdev->para->cs = hdev->cur_video_param->color; + para->cs = hdev->cur_video_param->color; pr_info(VID "rx edid only support RGB format\n"); } if (videocode >= HDMITX_VESA_OFFSET) { - hdev->para->cs = HDMI_COLORSPACE_RGB; - hdev->para->cd = COLORDEPTH_24B; + para->cs = HDMI_COLORSPACE_RGB; + para->cd = COLORDEPTH_24B; pr_info("hdmitx: VESA only support RGB format\n"); } diff --git a/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c index 151111dcd..5693d9188 100644 --- a/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c +++ b/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c @@ -452,6 +452,8 @@ static void set_vmode_clk(struct hdmitx_dev *hdev) static void hdmi_hwp_init(struct hdmitx_dev *hdev) { + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; + hdmitx_set_sys_clk(hdev, 0xff); hdmitx_set_cts_hdcp22_clk(hdev); hdmitx_set_hdcp_pclk(hdev); @@ -484,55 +486,55 @@ static void hdmi_hwp_init(struct hdmitx_dev *hdev) /* Get uboot output color space from AVI */ switch (hdmitx_rd_reg(HDMITX_DWC_FC_AVICONF0) & 0x3) { case 1: - hdev->para->cs = HDMI_COLORSPACE_YUV422; + para->cs = HDMI_COLORSPACE_YUV422; break; case 2: - hdev->para->cs = HDMI_COLORSPACE_YUV444; + para->cs = HDMI_COLORSPACE_YUV444; break; case 3: - hdev->para->cs = HDMI_COLORSPACE_YUV420; + para->cs = HDMI_COLORSPACE_YUV420; break; default: - hdev->para->cs = HDMI_COLORSPACE_RGB; + para->cs = HDMI_COLORSPACE_RGB; break; } /* If color space is not 422, then get depth from VP_PR_CD */ - if (hdev->para->cs != HDMI_COLORSPACE_YUV422) { + if (para->cs != HDMI_COLORSPACE_YUV422) { switch ((hdmitx_rd_reg(HDMITX_DWC_VP_PR_CD) >> 4) & 0xf) { case 5: - hdev->para->cd = COLORDEPTH_30B; + para->cd = COLORDEPTH_30B; break; case 6: - hdev->para->cd = COLORDEPTH_36B; + para->cd = COLORDEPTH_36B; break; case 7: - hdev->para->cd = COLORDEPTH_48B; + para->cd = COLORDEPTH_48B; break; case 0: case 4: default: - hdev->para->cd = COLORDEPTH_24B; + para->cd = COLORDEPTH_24B; break; } } else { /* If colorspace is 422, then get depth from VP_REMAP */ switch (hdmitx_rd_reg(HDMITX_DWC_VP_REMAP) & 0x3) { case 1: - hdev->para->cd = COLORDEPTH_30B; + para->cd = COLORDEPTH_30B; break; case 2: - hdev->para->cd = COLORDEPTH_36B; + para->cd = COLORDEPTH_36B; break; case 0: default: - hdev->para->cd = COLORDEPTH_24B; + para->cd = COLORDEPTH_24B; break; } } } else { - hdev->para->cd = COLORDEPTH_RESERVED; - hdev->para->cs = HDMI_COLORSPACE_RESERVED6; + para->cd = COLORDEPTH_RESERVED; + para->cs = HDMI_COLORSPACE_RESERVED6; /* reset HDMITX APB & TX & PHY */ hdmitx_sys_reset(); if (hdev->data->chip_type < MESON_CPU_ID_G12A) { @@ -1378,8 +1380,8 @@ static void hdmi_tvenc_vesa_set(struct hdmitx_vidpara *param) unsigned long vs_adjust = 0; unsigned long vs_bline_evn = 0, vs_eline_evn = 0; unsigned long vso_begin_evn = 0; - struct hdmi_format_para *vpara = NULL; - struct hdmi_cea_timing *vtiming = NULL; + const struct hdmi_format_para *vpara = NULL; + const struct hdmi_cea_timing *vtiming = NULL; vpara = hdmi_get_fmt_paras(param->VIC); if (!vpara) { @@ -1502,8 +1504,8 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param) unsigned long vs_adjust = 0; unsigned long vs_bline_evn = 0, vs_eline_evn = 0; unsigned long vso_begin_evn = 0; - struct hdmi_format_para *hdmi_encp_para = NULL; - struct hdmi_cea_timing *hdmi_encp_timing = NULL; + const struct hdmi_format_para *hdmi_encp_para = NULL; + const struct hdmi_cea_timing *hdmi_encp_timing = NULL; if ((param->VIC & HDMITX_VESA_OFFSET) == HDMITX_VESA_OFFSET) { /* VESA modes setting */ @@ -1943,6 +1945,7 @@ static void set_phy_by_mode(unsigned int mode) static void hdmitx_set_phy(struct hdmitx_dev *hdev) { unsigned int phy_addr = 0; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; if (!hdev) return; @@ -1989,12 +1992,12 @@ do { \ case HDMI_3840x2160p60_16x9: case HDMI_4096x2160p50_256x135: case HDMI_4096x2160p60_256x135: - if (hdev->para->cs != HDMI_COLORSPACE_YUV420) + if (para->cs != HDMI_COLORSPACE_YUV420) set_phy_by_mode(HDMI_PHYPARA_6G); else - if (hdev->para->cd == COLORDEPTH_36B) + if (para->cd == COLORDEPTH_36B) set_phy_by_mode(HDMI_PHYPARA_4p5G); - else if (hdev->para->cd == COLORDEPTH_30B) + else if (para->cd == COLORDEPTH_30B) set_phy_by_mode(HDMI_PHYPARA_3p7G); else set_phy_by_mode(HDMI_PHYPARA_3G); @@ -2003,9 +2006,9 @@ do { \ case HDMI_3840x2160p60_16x9_Y420: case HDMI_4096x2160p50_256x135_Y420: case HDMI_4096x2160p60_256x135_Y420: - if (hdev->para->cd == COLORDEPTH_36B) + if (para->cd == COLORDEPTH_36B) set_phy_by_mode(HDMI_PHYPARA_4p5G); - else if (hdev->para->cd == COLORDEPTH_30B) + else if (para->cd == COLORDEPTH_30B) set_phy_by_mode(HDMI_PHYPARA_3p7G); else set_phy_by_mode(HDMI_PHYPARA_3G); @@ -2018,13 +2021,13 @@ do { \ case HDMI_4k2k_smpte_24: case HDMI_4096x2160p25_256x135: case HDMI_4096x2160p30_256x135: - if (hdev->para->cs == HDMI_COLORSPACE_YUV422 || - hdev->para->cd == COLORDEPTH_24B) + if (para->cs == HDMI_COLORSPACE_YUV422 || + para->cd == COLORDEPTH_24B) set_phy_by_mode(HDMI_PHYPARA_3G); else - if (hdev->para->cd == COLORDEPTH_36B) + if (para->cd == COLORDEPTH_36B) set_phy_by_mode(HDMI_PHYPARA_4p5G); - else if (hdev->para->cd == COLORDEPTH_30B) + else if (para->cd == COLORDEPTH_30B) set_phy_by_mode(HDMI_PHYPARA_3p7G); else set_phy_by_mode(HDMI_PHYPARA_3G); @@ -2061,16 +2064,18 @@ static void set_tmds_clk_div40(unsigned int div40) static void hdmitx_set_scdc(struct hdmitx_dev *hdev) { + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; + switch (hdev->cur_video_param->VIC) { case HDMI_3840x2160p50_16x9: case HDMI_3840x2160p60_16x9: case HDMI_4096x2160p50_256x135: case HDMI_4096x2160p60_256x135: - if (hdev->para->cs == HDMI_COLORSPACE_YUV420 && - hdev->para->cd == COLORDEPTH_24B) - hdev->para->tmds_clk_div40 = 0; + if (para->cs == HDMI_COLORSPACE_YUV420 && + para->cd == COLORDEPTH_24B) + para->tmds_clk_div40 = 0; else - hdev->para->tmds_clk_div40 = 1; + para->tmds_clk_div40 = 1; break; case HDMI_3840x2160p50_16x9_Y420: case HDMI_3840x2160p60_16x9_Y420: @@ -2078,10 +2083,10 @@ static void hdmitx_set_scdc(struct hdmitx_dev *hdev) case HDMI_4096x2160p60_256x135_Y420: case HDMI_3840x2160p50_64x27_Y420: case HDMI_3840x2160p60_64x27_Y420: - if (hdev->para->cd == COLORDEPTH_24B) - hdev->para->tmds_clk_div40 = 0; + if (para->cd == COLORDEPTH_24B) + para->tmds_clk_div40 = 0; else - hdev->para->tmds_clk_div40 = 1; + para->tmds_clk_div40 = 1; break; case HDMI_3840x2160p24_16x9: case HDMI_3840x2160p24_64x27: @@ -2092,28 +2097,29 @@ static void hdmitx_set_scdc(struct hdmitx_dev *hdev) case HDMI_3840x2160p30_16x9: case HDMI_3840x2160p30_64x27: case HDMI_4096x2160p30_256x135: - if (hdev->para->cs == HDMI_COLORSPACE_YUV422 || - hdev->para->cd == COLORDEPTH_24B) - hdev->para->tmds_clk_div40 = 0; + if (para->cs == HDMI_COLORSPACE_YUV422 || + para->cd == COLORDEPTH_24B) + para->tmds_clk_div40 = 0; else - hdev->para->tmds_clk_div40 = 1; + para->tmds_clk_div40 = 1; break; case HDMIV_2560x1600p60hz: - hdev->para->tmds_clk_div40 = 0; + para->tmds_clk_div40 = 0; break; default: - hdev->para->tmds_clk_div40 = 0; + para->tmds_clk_div40 = 0; break; } - set_tmds_clk_div40(hdev->para->tmds_clk_div40); + set_tmds_clk_div40(para->tmds_clk_div40); scdc_config(hdev); - hdev->pre_tmds_clk_div40 = hdev->para->tmds_clk_div40; - hdev->div40 = hdev->para->tmds_clk_div40; + hdev->pre_tmds_clk_div40 = para->tmds_clk_div40; + hdev->div40 = para->tmds_clk_div40; } void hdmitx_set_enc_hw(struct hdmitx_dev *hdev) { unsigned int data32 = 0; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; set_vmode_enc_hw(hdev); @@ -2160,7 +2166,7 @@ void hdmitx_set_enc_hw(struct hdmitx_dev *hdev) (0 << 4) | /* [4]dith_en: disable dithering */ (0 << 5) | (0 << 6)); /* [ 9: 6] hdmi_dith10_cntl. */ - if (hdev->para->cs == HDMI_COLORSPACE_YUV420) { + if (para->cs == HDMI_COLORSPACE_YUV420) { hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 2, 0, 2); hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 4, 4); hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 8, 1); @@ -2169,7 +2175,7 @@ void hdmitx_set_enc_hw(struct hdmitx_dev *hdev) hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 1); } - if (hdev->para->cs == HDMI_COLORSPACE_YUV422) { + if (para->cs == HDMI_COLORSPACE_YUV422) { hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 1, 0, 2); hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 4, 4); } @@ -2193,7 +2199,7 @@ void hdmitx_set_enc_hw(struct hdmitx_dev *hdev) break; } - switch (hdev->para->cd) { + switch (para->cd) { case COLORDEPTH_30B: case COLORDEPTH_36B: case COLORDEPTH_48B: @@ -2663,6 +2669,7 @@ static int set_aud_acr_pkt(struct hdmitx_dev *hdev, unsigned int aud_n_para; unsigned int char_rate; static unsigned int pre_aud_n_para; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; /* audio packetizer config */ hdmitx_wr_reg(HDMITX_DWC_AUD_INPUTCLKFS, audio_param->aud_src_if ? 4 : 0); @@ -2671,16 +2678,16 @@ static int set_aud_acr_pkt(struct hdmitx_dev *hdev, audio_param->type == CT_DTS_HD_MA) hdmitx_wr_reg(HDMITX_DWC_AUD_INPUTCLKFS, 2); - if (hdev->tx_comm.frac_rate_policy && hdev->para->timing.frac_freq) - char_rate = hdev->para->timing.frac_freq; + if (hdev->tx_comm.frac_rate_policy && para->timing.frac_freq) + char_rate = para->timing.frac_freq; else - char_rate = hdev->para->timing.pixel_freq; - if (hdev->para->cs == HDMI_COLORSPACE_YUV422) + char_rate = para->timing.pixel_freq; + if (para->cs == HDMI_COLORSPACE_YUV422) aud_n_para = hdmi_get_aud_n_paras(audio_param->sample_rate, COLORDEPTH_24B, char_rate); else aud_n_para = hdmi_get_aud_n_paras(audio_param->sample_rate, - hdev->para->cd, char_rate); + para->cd, char_rate); /* N must multiples 4 for DD+ */ switch (audio_param->type) { case CT_DD_P: @@ -3113,7 +3120,7 @@ static void mode420_half_horizontal_para(void) static void hdmitx_set_fake_vic(struct hdmitx_dev *hdev) { - hdev->para->cs = HDMI_COLORSPACE_YUV444; + hdev->tx_comm.fmt_para.cs = HDMI_COLORSPACE_YUV444; hdev->tx_comm.cur_VIC = HDMI_VIC_FAKE; set_vmode_clk(hdev); } @@ -3169,6 +3176,7 @@ static void hdmitx_debug(struct hdmitx_dev *hdev, const char *buf) struct extcon_dev *hdmitx_extcon_hdmi = get_hdmitx_extcon_hdmi(); struct extcon_dev *extcon_event_type; static enum hdmitx_event event_type = HDMITX_NONE_EVENT; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; while ((buf[i]) && (buf[i] != ',') && (buf[i] != ' ')) { tmpbuf[i] = buf[i]; @@ -3198,7 +3206,7 @@ static void hdmitx_debug(struct hdmitx_dev *hdev, const char *buf) hdev->bist_lock = 1; hdmitx_wr_reg(HDMITX_DWC_FC_VSDSIZE, 0x05); hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONF_AVI_RGBYCC_INDIC, - hdev->para->cs); + para->cs); if (hdev->data->chip_type < MESON_CPU_ID_SC2) hd_set_reg_bits(P_HHI_GCLK_OTHER, 1, 3, 1); hd_set_reg_bits(P_ENCP_VIDEO_MODE_ADV, 0, 3, 1); @@ -4451,7 +4459,7 @@ static void hdmitx_debug_bist(struct hdmitx_dev *hdev, unsigned int num) /*hdev->bist_lock = 1;*/ /*hdmitx_wr_reg(HDMITX_DWC_FC_VSDSIZE, 0x05); *hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONF_AVI_RGBYCC_INDIC, - * hdev->para->cs); + * hdev->tx_comm.fmt_para.cs); */ if (hdev->data->chip_type < MESON_CPU_ID_SC2) hd_set_reg_bits(P_HHI_GCLK_OTHER, 1, 3, 1); @@ -5223,7 +5231,7 @@ static void hdmitx_dith_ctrl(struct hdmitx_dev *hdev) { unsigned int hs_flag = 0; - switch (hdev->para->cd) { + switch (hdev->tx_comm.fmt_para.cd) { case COLORDEPTH_30B: case COLORDEPTH_36B: case COLORDEPTH_48B: @@ -5586,7 +5594,7 @@ static int hdmitx_cntl_config(struct hdmitx_hw_common *tx_hw, unsigned int cmd, hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, 6, 4, 3); } if (argv == CLR_AVI_BT2020) - hdmitx_set_avi_colorimetry(hdev->para); + hdmitx_set_avi_colorimetry(&hdev->tx_comm.fmt_para); break; case CONF_GET_AVI_BT2020: if (((hdmitx_rd_reg(HDMITX_DWC_FC_AVICONF1) & 0xC0) == 0xC0) && @@ -6165,7 +6173,7 @@ static void config_hdmi20_tx(enum hdmi_vic vic, unsigned char input_color_format, unsigned char output_color_format) { - struct hdmi_format_para *para = hdev->para; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; struct hdmi_cea_timing *t = ¶->timing; unsigned long data32; unsigned char vid_map; @@ -6469,7 +6477,7 @@ static void config_hdmi20_tx(enum hdmi_vic vic, data32 = t->v_sync & 0x3f; hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINWIDTH, data32); - if (hdev->para->cs == HDMI_COLORSPACE_YUV420) + if (para->cs == HDMI_COLORSPACE_YUV420) mode420_half_horizontal_para(); /* control period duration (typ 12 tmds periods) */ @@ -6989,27 +6997,14 @@ static void hdmitx_csc_config(unsigned char input_color_format, static void hdmitx_set_hw(struct hdmitx_dev *hdev) { - enum hdmi_vic vic = HDMI_UNKNOWN; - struct hdmi_format_para *para = NULL; + const struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; - if (!hdev->cur_video_param) { - pr_info("error at null vidpara!\n"); - return; - } + pr_info(HW " config hdmitx IP vic = %d cd:%d cs: %d\n", + para->vic, para->cd, para->cs); - vic = (enum hdmi_vic)hdev->cur_video_param->VIC; - para = hdmi_get_fmt_paras(vic); - if (!para) { - pr_info("error at %s[%d] vic = %d\n", __func__, __LINE__, vic); - return; - } - - pr_info(HW " config hdmitx IP vic = %d cd:%d cs: %d\n", vic, - hdev->para->cd, hdev->para->cs); - - config_hdmi20_tx(vic, hdev, - hdev->para->cd, - TX_INPUT_COLOR_FORMAT, - hdev->para->cs); + config_hdmi20_tx(para->vic, hdev, + para->cd, + TX_INPUT_COLOR_FORMAT, + para->cs); } diff --git a/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c b/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c index eb2f1d385..6750f579d 100644 --- a/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c +++ b/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c @@ -922,8 +922,8 @@ static void hdmitx_set_clk_(struct hdmitx_dev *hdev, int j = 0; struct hw_enc_clk_val_group *p_enc = NULL; enum hdmi_vic vic = hdev->tx_comm.cur_VIC; - enum hdmi_colorspace cs = hdev->para->cs; - enum hdmi_color_depth cd = hdev->para->cd; + enum hdmi_colorspace cs = hdev->tx_comm.fmt_para.cs; + enum hdmi_color_depth cd = hdev->tx_comm.fmt_para.cd; if (!test_clk) return; @@ -1010,7 +1010,7 @@ next: set_vid_clk_div(hdev, p_enc[j].vid_clk_div); set_hdmi_tx_pixel_div(hdev, p_enc[j].hdmi_tx_pixel_div); - if (hdev->para->hdmitx_vinfo.viu_mux == VIU_MUX_ENCI) { + if (hdev->tx_comm.fmt_para.hdmitx_vinfo.viu_mux == VIU_MUX_ENCI) { set_enci_div(hdev, p_enc[j].enci_div); hdmitx_enable_enci_clk(hdev); } else { @@ -1032,7 +1032,7 @@ static int likely_frac_rate_mode(char *m) static void hdmitx_check_frac_rate(struct hdmitx_dev *hdev) { enum hdmi_vic vic = hdev->tx_comm.cur_VIC; - struct hdmi_format_para *para = NULL; + const struct hdmi_format_para *para = NULL; frac_rate = hdev->tx_comm.frac_rate_policy; para = hdmi_get_fmt_paras(vic); @@ -1167,7 +1167,7 @@ void hdmitx_set_clk(struct hdmitx_dev *hdev) void hdmitx_disable_clk(struct hdmitx_dev *hdev) { /* cts_encp/enci_clk */ - if (hdev->para->hdmitx_vinfo.viu_mux == VIU_MUX_ENCI) + if (hdev->tx_comm.fmt_para.hdmitx_vinfo.viu_mux == VIU_MUX_ENCI) hdmitx_disable_enci_clk(hdev); else hdmitx_disable_encp_clk(hdev); diff --git a/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c b/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c index 2f0adad8b..538b3ec10 100644 --- a/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c +++ b/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c @@ -83,6 +83,7 @@ static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val) { int ret = 0; struct hdmitx_dev *hdev = get_hdmitx_device(); + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff)); hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2); @@ -90,11 +91,11 @@ static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val) hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); if (frac_val == 0x8148) { - if ((hdev->para->vic == HDMI_3840x2160p50_16x9 || - hdev->para->vic == HDMI_3840x2160p60_16x9 || - hdev->para->vic == HDMI_3840x2160p50_64x27 || - hdev->para->vic == HDMI_3840x2160p60_64x27) && - hdev->para->cs != HDMI_COLORSPACE_YUV420) { + if ((para->vic == HDMI_3840x2160p50_16x9 || + para->vic == HDMI_3840x2160p60_16x9 || + para->vic == HDMI_3840x2160p50_64x27 || + para->vic == HDMI_3840x2160p60_64x27) && + para->cs != HDMI_COLORSPACE_YUV420) { hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00); hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x11551293); } else { @@ -104,13 +105,13 @@ static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val) } else { if (hdev->data->chip_type == MESON_CPU_ID_SM1 && hdmitx_find_vendor_6g(hdev) && - (hdev->para->vic == HDMI_3840x2160p50_16x9 || - hdev->para->vic == HDMI_3840x2160p60_16x9 || - hdev->para->vic == HDMI_3840x2160p50_64x27 || - hdev->para->vic == HDMI_3840x2160p60_64x27 || - hdev->para->vic == HDMI_4096x2160p50_256x135 || - hdev->para->vic == HDMI_4096x2160p60_256x135) && - hdev->para->cs != HDMI_COLORSPACE_YUV420) { + (para->vic == HDMI_3840x2160p50_16x9 || + para->vic == HDMI_3840x2160p60_16x9 || + para->vic == HDMI_3840x2160p50_64x27 || + para->vic == HDMI_3840x2160p60_64x27 || + para->vic == HDMI_4096x2160p50_256x135 || + para->vic == HDMI_4096x2160p60_256x135) && + para->cs != HDMI_COLORSPACE_YUV420) { hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00); hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x11551293); } else { @@ -170,9 +171,11 @@ static bool set_hpll_hclk_v3(unsigned int m, unsigned int frac_val) static inline int is_dongle_mode(struct hdmitx_dev *hdev) { + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; + return hdev->dongle_mode && - (hdev->para->cs == HDMI_COLORSPACE_YUV422 || - hdev->para->cd == COLORDEPTH_24B) && + (para->cs == HDMI_COLORSPACE_YUV422 || + para->cd == COLORDEPTH_24B) && (hdev->tx_comm.cur_VIC == HDMI_1280x720p50_16x9 || hdev->tx_comm.cur_VIC == HDMI_1280x720p60_16x9 || hdev->tx_comm.cur_VIC == HDMI_1920x1080i60_16x9 || diff --git a/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_sc2.c b/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_sc2.c index bdd637a6e..47cd4181b 100644 --- a/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_sc2.c +++ b/drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_sc2.c @@ -41,6 +41,7 @@ static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val) { int ret = 0; struct hdmitx_dev *hdev = get_hdmitx_device(); + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | (m & 0xff)); hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x3, 28, 2); @@ -48,11 +49,11 @@ static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val) hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); if (frac_val == 0x8148) { - if ((hdev->para->vic == HDMI_3840x2160p50_16x9 || - hdev->para->vic == HDMI_3840x2160p60_16x9 || - hdev->para->vic == HDMI_3840x2160p50_64x27 || - hdev->para->vic == HDMI_3840x2160p60_64x27) && - hdev->para->cs != HDMI_COLORSPACE_YUV420) { + if ((para->vic == HDMI_3840x2160p50_16x9 || + para->vic == HDMI_3840x2160p60_16x9 || + para->vic == HDMI_3840x2160p50_64x27 || + para->vic == HDMI_3840x2160p60_64x27) && + para->cs != HDMI_COLORSPACE_YUV420) { hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00); hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x11551293); } else { @@ -61,13 +62,13 @@ static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val) } } else { if (hdmitx_find_vendor_6g(hdev) && - (hdev->para->vic == HDMI_3840x2160p50_16x9 || - hdev->para->vic == HDMI_3840x2160p60_16x9 || - hdev->para->vic == HDMI_3840x2160p50_64x27 || - hdev->para->vic == HDMI_3840x2160p60_64x27 || - hdev->para->vic == HDMI_4096x2160p50_256x135 || - hdev->para->vic == HDMI_4096x2160p60_256x135) && - hdev->para->cs != HDMI_COLORSPACE_YUV420) { + (para->vic == HDMI_3840x2160p50_16x9 || + para->vic == HDMI_3840x2160p60_16x9 || + para->vic == HDMI_3840x2160p50_64x27 || + para->vic == HDMI_3840x2160p60_64x27 || + para->vic == HDMI_4096x2160p50_256x135 || + para->vic == HDMI_4096x2160p60_256x135) && + para->cs != HDMI_COLORSPACE_YUV420) { hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00); hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x11551293); } else { diff --git a/drivers/media/vout/hdmitx21/hdmi_param.c b/drivers/media/vout/hdmitx21/hdmi_param.c index 8ca566bb4..96f25a8b9 100644 --- a/drivers/media/vout/hdmitx21/hdmi_param.c +++ b/drivers/media/vout/hdmitx21/hdmi_param.c @@ -315,21 +315,20 @@ static void recalc_vinfo_sync_duration(struct vinfo_s *info, u32 frac) * 3840x2160p60hz, etc * attr strings likes as '444,8bit' */ -struct hdmi_format_para *hdmitx21_get_fmtpara(const char *mode, - const char *attr) +int hdmitx21_get_fmtpara(const char *mode, const char *attr, struct hdmi_format_para *para) { struct hdmitx_dev *hdev = get_hdmitx21_device(); struct hdmitx_common *tx_comm = &hdev->tx_comm; +// struct hdmi_format_para *para = &tx_comm->fmt_para; + struct vinfo_s *tx_vinfo = ¶->hdmitx_vinfo; const struct hdmi_timing *timing; - struct vinfo_s *tx_vinfo = &hdev->para->hdmitx_vinfo; - struct hdmi_format_para *para = hdev->para; if (!mode || !attr) - return NULL; + return -EINVAL; timing = hdmitx21_gettiming_from_name(mode); if (!timing) - return NULL; + return -EINVAL; para->timing = *timing; _parse_hdmi_attr(attr, ¶->cs, ¶->cd, ¶->cr); @@ -369,8 +368,10 @@ struct hdmi_format_para *hdmitx21_get_fmtpara(const char *mode, if (strstr(timing->name, "1080i")) tx_vinfo->viu_mux = VIU_MUX_ENCP; tx_vinfo->viu_mux |= hdev->enc_idx << 4; + tx_vinfo->cd = para->cd; + tx_vinfo->cs = para->cs; - return hdev->para; + return 0; } /* For check all format parameters only */ diff --git a/drivers/media/vout/hdmitx21/hdmi_tx.h b/drivers/media/vout/hdmitx21/hdmi_tx.h index 0a0cd89c4..87bfd0505 100644 --- a/drivers/media/vout/hdmitx21/hdmi_tx.h +++ b/drivers/media/vout/hdmitx21/hdmi_tx.h @@ -73,7 +73,7 @@ u8 hdmi_ddc_status_check(void); u8 hdmi_ddc_busy_check(void); void hdmi_ddc_error_reset(void); -void hdmitx21_fmt_attr(struct hdmitx_dev *hdev); +void hdmitx21_rebuild_fmt_attr_str(struct hdmitx_dev *hdev, struct hdmi_format_para *para); int hdmitx21_hdcp_init(void); int hdmitx21_uboot_audio_en(void); diff --git a/drivers/media/vout/hdmitx21/hdmi_tx_infoframe.c b/drivers/media/vout/hdmitx21/hdmi_tx_infoframe.c index 9fe1a13d6..4a0030d21 100644 --- a/drivers/media/vout/hdmitx21/hdmi_tx_infoframe.c +++ b/drivers/media/vout/hdmitx21/hdmi_tx_infoframe.c @@ -160,7 +160,7 @@ void hdmi_avi_infoframe_config(enum avi_component_conf conf, u8 val) { struct hdmitx_dev *hdev = get_hdmitx21_device(); struct hdmi_avi_infoframe *info = &hdev->infoframes.avi.avi; - struct hdmi_format_para *para = hdev->para; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; switch (conf) { case CONF_AVI_CS: diff --git a/drivers/media/vout/hdmitx21/hdmi_tx_main.c b/drivers/media/vout/hdmitx21/hdmi_tx_main.c index 5001265bb..6dccf9636 100644 --- a/drivers/media/vout/hdmitx21/hdmi_tx_main.c +++ b/drivers/media/vout/hdmitx21/hdmi_tx_main.c @@ -611,6 +611,7 @@ static void rxlatency_to_vinfo(struct vinfo_s *info, struct rx_cap *rx) static void edidinfo_attach_to_vinfo(struct hdmitx_dev *hdev) { struct vinfo_s *info = NULL; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; /* get current vinfo */ info = hdmitx_get_current_vinfo(NULL); @@ -625,7 +626,7 @@ static void edidinfo_attach_to_vinfo(struct hdmitx_dev *hdev) mutex_lock(&getedid_mutex); hdrinfo_to_vinfo(&info->hdr_info, hdev); memcpy(&ext_dvinfo, &hdev->tx_comm.rxcap.dv_info, sizeof(ext_dvinfo)); - if (hdev->para && hdev->para->cd == COLORDEPTH_24B) + if (para->cd == COLORDEPTH_24B) memset(&info->hdr_info, 0, sizeof(struct hdr_info)); rxlatency_to_vinfo(info, &hdev->tx_comm.rxcap); hdmitx_vdev.dv_info = &hdev->tx_comm.rxcap.dv_info; @@ -756,7 +757,7 @@ static int set_disp_mode_auto(void) struct vinfo_s *info = NULL; struct hdmitx_dev *hdev = get_hdmitx21_device(); struct hdmitx_common *tx_comm = &hdev->tx_comm; - struct hdmi_format_para *para = NULL; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; u8 mode[32]; enum hdmi_vic vic = HDMI_0_UNKNOWN; @@ -810,8 +811,7 @@ static int set_disp_mode_auto(void) } } - para = hdmitx21_get_fmtpara(mode, tx_comm->fmt_attr); - if (!para) { + if (hdmitx21_get_fmtpara(mode, tx_comm->fmt_attr, para) == 0) { pr_info("%s[%d] %s %s\n", __func__, __LINE__, mode, tx_comm->fmt_attr); mutex_unlock(&hdev->hdmimode_mutex); @@ -827,7 +827,6 @@ static int set_disp_mode_auto(void) hdmitx21_disable_hdcp(hdev); pr_info("setting hdmi mode %s %s\n", mode, tx_comm->fmt_attr); pr_info("cd/cs/cr: %d/%d/%d\n", para->cd, para->cs, para->cr); - hdev->para = para; vic = hdmitx21_edid_get_VIC(hdev, mode, 1); if (strncmp(info->name, "2160p30hz", strlen("2160p30hz")) == 0) { vic = HDMI_95_3840x2160p30_16x9; @@ -846,7 +845,7 @@ static int set_disp_mode_auto(void) if (tx_comm->rxcap.max_frl_rate) { hdev->frl_rate = hdmitx21_select_frl_rate(hdev->dsc_en, vic, - hdev->para->cs, hdev->para->cd); + para->cs, para->cd); if (hdev->frl_rate > hdev->tx_max_frl_rate) pr_info("Current frl_rate %d is larger than tx_max_frl_rate %d\n", hdev->frl_rate, hdev->tx_max_frl_rate); @@ -910,7 +909,7 @@ static ssize_t disp_mode_show(struct device *dev, int pos = 0; int i = 0; struct hdmitx_dev *hdev = get_hdmitx21_device(); - struct hdmi_format_para *para = hdev->para; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; struct hdmi_timing *timing = ¶->timing; struct vinfo_s *vinfo = ¶->hdmitx_vinfo; @@ -1497,7 +1496,7 @@ static void hdmitx_set_drm_pkt(struct master_display_info_s *data) /* if VSIF/DV or VSIF/HDR10P packet is enabled, disable it */ if (hdmitx21_dv_en()) { update_current_para(hdev); - hdmi_avi_infoframe_config(CONF_AVI_CS, hdev->para->cs); + hdmi_avi_infoframe_config(CONF_AVI_CS, hdev->tx_comm.fmt_para.cs); /* if using VSIF/DOVI, then only clear DV_VS10_SIG, else disable VSIF */ if (hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONF_CLR_DV_VS10_SIG, 0) == 0) /* hdmi_vend_infoframe_set(NULL); */ @@ -1651,7 +1650,7 @@ static void update_current_para(struct hdmitx_dev *hdev) memset(mode, 0, sizeof(mode)); strncpy(mode, info->name, sizeof(mode) - 1); - hdev->para = hdmitx21_get_fmtpara(mode, tx_comm->fmt_attr); + hdmitx21_get_fmtpara(mode, tx_comm->fmt_attr, &tx_comm->fmt_para); } static struct vsif_debug_save vsif_debug_info; @@ -1674,6 +1673,7 @@ static void hdmitx_set_vsif_pkt(enum eotf_type type, static u8 ltmode = -1; enum hdmi_tf_type hdr_type = HDMI_NONE; unsigned long flags = 0; + struct hdmi_format_para *fmt_para = &hdev->tx_comm.fmt_para; if (!_check_hdmi_mode()) return; @@ -1803,7 +1803,7 @@ static void hdmitx_set_vsif_pkt(enum eotf_type type, if (signal_sdr) { pr_info("hdmitx: Dolby H14b VSIF, switching signal to SDR\n"); update_current_para(hdev); - hdmi_avi_infoframe_config(CONF_AVI_CS, hdev->para->cs); + hdmi_avi_infoframe_config(CONF_AVI_CS, fmt_para->cs); hdmi_avi_infoframe_config(CONF_AVI_Q01, RGB_RANGE_LIM); hdmi_avi_infoframe_config(CONF_AVI_YQ01, YCC_RANGE_LIM); hdmi_avi_infoframe_config(CONF_AVI_BT2020, CLR_AVI_BT2020);/*BT709*/ @@ -1939,9 +1939,9 @@ static void hdmitx_set_vsif_pkt(enum eotf_type type, pr_info("hdmitx: Dolby VSIF, switching signal to SDR\n"); update_current_para(hdev); pr_info("vic:%d, cd:%d, cs:%d, cr:%d\n", - hdev->para->timing.vic, hdev->para->cd, - hdev->para->cs, hdev->para->cr); - hdmi_avi_infoframe_config(CONF_AVI_CS, hdev->para->cs); + fmt_para->timing.vic, fmt_para->cd, + fmt_para->cs, fmt_para->cr); + hdmi_avi_infoframe_config(CONF_AVI_CS, fmt_para->cs); hdmi_avi_infoframe_config(CONF_AVI_Q01, RGB_RANGE_DEFAULT); hdmi_avi_infoframe_config(CONF_AVI_YQ01, YCC_RANGE_LIM); hdmi_avi_infoframe_config(CONF_AVI_BT2020, CLR_AVI_BT2020);/*BT709*/ @@ -2174,47 +2174,46 @@ static ssize_t config_show(struct device *dev, int pos = 0; u8 *conf; struct hdmitx_dev *hdev = get_hdmitx21_device(); + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; pos += snprintf(buf + pos, PAGE_SIZE, "cur_VIC: %d\n", hdev->tx_comm.cur_VIC); - if (hdev->para) { - switch (hdev->para->cd) { - case COLORDEPTH_24B: - conf = "8bit"; - break; - case COLORDEPTH_30B: - conf = "10bit"; - break; - case COLORDEPTH_36B: - conf = "12bit"; - break; - case COLORDEPTH_48B: - conf = "16bit"; - break; - default: - conf = "reserved"; - } - pos += snprintf(buf + pos, PAGE_SIZE, "colordepth: %s\n", - conf); - switch (hdev->para->cs) { - case HDMI_COLORSPACE_RGB: - conf = "RGB"; - break; - case HDMI_COLORSPACE_YUV422: - conf = "422"; - break; - case HDMI_COLORSPACE_YUV444: - conf = "444"; - break; - case HDMI_COLORSPACE_YUV420: - conf = "420"; - break; - default: - conf = "reserved"; - } - pos += snprintf(buf + pos, PAGE_SIZE, "colorspace: %s\n", - conf); + switch (para->cd) { + case COLORDEPTH_24B: + conf = "8bit"; + break; + case COLORDEPTH_30B: + conf = "10bit"; + break; + case COLORDEPTH_36B: + conf = "12bit"; + break; + case COLORDEPTH_48B: + conf = "16bit"; + break; + default: + conf = "reserved"; } + pos += snprintf(buf + pos, PAGE_SIZE, "colordepth: %s\n", + conf); + switch (para->cs) { + case HDMI_COLORSPACE_RGB: + conf = "RGB"; + break; + case HDMI_COLORSPACE_YUV422: + conf = "422"; + break; + case HDMI_COLORSPACE_YUV444: + conf = "444"; + break; + case HDMI_COLORSPACE_YUV420: + conf = "420"; + break; + default: + conf = "reserved"; + } + pos += snprintf(buf + pos, PAGE_SIZE, "colorspace: %s\n", + conf); switch (hdev->tx_aud_cfg) { case 0: @@ -2672,6 +2671,7 @@ static ssize_t disp_cap_show(struct device *dev, pos += snprintf(buf + pos, PAGE_SIZE, "*"); pos += snprintf(buf + pos, PAGE_SIZE, "\n"); } + if (is_vic_support_y420(vic)) { /* backup only for old android */ /* pos += snprintf(buf + pos, PAGE_SIZE, "%s420\n", */ @@ -4577,9 +4577,7 @@ static struct vinfo_s *hdmitx_get_current_vinfo(void *data) { struct hdmitx_dev *hdev = get_hdmitx21_device(); - if (!hdev->para) - return NULL; - return &hdev->para->hdmitx_vinfo; + return &hdev->tx_comm.fmt_para.hdmitx_vinfo; } static int hdmitx_set_current_vmode(enum vmode_e mode, void *data) @@ -4601,7 +4599,8 @@ static int hdmitx_set_current_vmode(enum vmode_e mode, void *data) update_current_para(hdev); if (tx_comm->rxcap.max_frl_rate) { hdev->frl_rate = hdmitx21_select_frl_rate(hdev->dsc_en, - tx_comm->cur_VIC, hdev->para->cs, hdev->para->cd); + tx_comm->cur_VIC, hdev->tx_comm.fmt_para.cs, + hdev->tx_comm.fmt_para.cd); if (hdev->frl_rate > hdev->tx_max_frl_rate) pr_info("Current frl_rate %d is larger than tx_max_frl_rate %d\n", hdev->frl_rate, hdev->tx_max_frl_rate); @@ -4620,8 +4619,8 @@ static int hdmitx_set_current_vmode(enum vmode_e mode, void *data) static enum vmode_e hdmitx_validate_vmode(char *_mode, u32 frac, void *data) { - struct hdmi_format_para *para = NULL; struct hdmitx_dev *hdev = get_hdmitx21_device(); + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; char mode[32] = {0}; char *y420; @@ -4633,17 +4632,15 @@ static enum vmode_e hdmitx_validate_vmode(char *_mode, u32 frac, void *data) if (y420) *y420 = '\0'; - para = hdmitx21_get_fmtpara(mode, hdev->tx_comm.fmt_attr); - - if (para) { + if (hdmitx21_get_fmtpara(mode, hdev->tx_comm.fmt_attr, para) == 0) { /* //remove frac support for vout api *if (frac) * hdev->frac_rate_policy = 1; *else * hdev->frac_rate_policy = 0; */ - hdev->para->hdmitx_vinfo.info_3d = NON_3D; - hdev->para->hdmitx_vinfo.vout_device = &hdmitx_vdev; + para->hdmitx_vinfo.info_3d = NON_3D; + para->hdmitx_vinfo.vout_device = &hdmitx_vdev; return VMODE_HDMI; } return VMODE_MAX; @@ -4660,14 +4657,13 @@ static int hdmitx_vmode_is_supported(enum vmode_e mode, void *data) static int hdmitx_module_disable(enum vmode_e cur_vmod, void *data) { struct hdmitx_dev *hdev = get_hdmitx21_device(); - struct hdmitx_common *tx_comm = &hdev->tx_comm; hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONF_CLR_AVI_PACKET, 0); hdev->tx_hw.cntlconfig(&hdev->tx_hw, CONF_CLR_VSDB_PACKET, 0); frl_tx_stop(hdev); hdev->tx_hw.cntlmisc(&hdev->tx_hw, MISC_TMDS_PHY_OP, TMDS_PHY_DISABLE); /* hdmitx21_disable_clk(hdev); */ - hdev->para = hdmitx21_get_fmtpara("invalid", tx_comm->fmt_attr); + hdmitx21_get_fmtpara("invalid", hdev->tx_comm.fmt_attr, &hdev->tx_comm.fmt_para); hdmitx_validate_vmode("null", 0, NULL); if (hdev->cedst_policy) cancel_delayed_work(&hdev->work_cedst); @@ -5439,25 +5435,24 @@ int get21_hpd_state(void) /****************************** * hdmitx kernel task *******************************/ - +/*TODO: called when there is no modesetting?*/ static bool is_cur_tmds_div40(struct hdmitx_dev *hdev) { const struct hdmi_timing *tp; const char *name; unsigned int act_clk = 0; struct hdmitx_common *tx_comm = &hdev->tx_comm; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; if (!hdev) return false; tp = hdmitx21_gettiming_from_vic(hdev->tx_comm.cur_VIC); if (tp) { name = tp->sname ? tp->sname : tp->name; - hdev->para = hdmitx21_get_fmtpara(name, - tx_comm->fmt_attr); + hdmitx21_get_fmtpara(name, tx_comm->fmt_attr, para); } - if (!hdev->para) - return false; - act_clk = hdev->para->tmds_clk / 1000; + + act_clk = para->tmds_clk / 1000; pr_info("hdmitx: get vic %d cscd %s act_clk %d\n", hdev->tx_comm.cur_VIC, tx_comm->fmt_attr, act_clk); @@ -5518,7 +5513,7 @@ static int get_dt_vend_init_data(struct device_node *np, return 0; } -void hdmitx21_fmt_attr(struct hdmitx_dev *hdev) +void hdmitx21_rebuild_fmt_attr_str(struct hdmitx_dev *hdev, struct hdmi_format_para *para) { struct hdmitx_common *tx_comm = &hdev->tx_comm; @@ -5527,7 +5522,7 @@ void hdmitx21_fmt_attr(struct hdmitx_dev *hdev) return; } memset(tx_comm->fmt_attr, 0, sizeof(tx_comm->fmt_attr)); - switch (hdev->para->cs) { + switch (para->cs) { case HDMI_COLORSPACE_RGB: memcpy(tx_comm->fmt_attr, "rgb,", 5); break; @@ -5543,7 +5538,7 @@ void hdmitx21_fmt_attr(struct hdmitx_dev *hdev) default: break; } - switch (hdev->para->cd) { + switch (para->cd) { case COLORDEPTH_24B: strcat(tx_comm->fmt_attr, "8bit"); break; @@ -5565,15 +5560,14 @@ void hdmitx21_fmt_attr(struct hdmitx_dev *hdev) static void hdmitx_init_fmt_attr(struct hdmitx_dev *hdev) { struct hdmitx_common *tx_comm = &hdev->tx_comm; + struct hdmi_format_para *para = &tx_comm->fmt_para; - if (!hdev->para) - return; if (strlen(tx_comm->fmt_attr) >= 8) { pr_info("fmt_attr %s\n", tx_comm->fmt_attr); return; } memset(tx_comm->fmt_attr, 0, sizeof(tx_comm->fmt_attr)); - switch (hdev->para->cs) { + switch (para->cs) { case HDMI_COLORSPACE_RGB: memcpy(tx_comm->fmt_attr, "rgb,", 5); break; @@ -5589,7 +5583,7 @@ static void hdmitx_init_fmt_attr(struct hdmitx_dev *hdev) default: break; } - switch (hdev->para->cd) { + switch (para->cd) { case COLORDEPTH_24B: strcat(tx_comm->fmt_attr, "8bit"); break; @@ -5701,17 +5695,14 @@ static void hdmitx_init_parameters(struct hdmitx_info *info) static int amhdmitx21_device_init(struct hdmitx_dev *hdmi_dev) { struct hdmitx_dev *hdev = get_hdmitx21_device(); - static struct hdmi_format_para para; if (!hdmi_dev) return 1; - memset(¶, 0, sizeof(para)); pr_info("Ver: %s\n", HDMITX_VER); hdmi_dev->hdtx_dev = NULL; - hdev->para = ¶ hdev->physical_addr = 0xffff; hdev->hdmi_last_hdr_mode = 0; hdev->hdmi_current_hdr_mode = 0; @@ -6219,7 +6210,10 @@ static int amhdmitx_probe(struct platform_device *pdev) aout_register_client(&hdmitx_notifier_nb_a); #endif hdmitx_extcon_register(pdev, dev); - /* update fmt_attr */ + /** + * update fmt_attr string from fmt_para, + * because fmt_para may update in hdmitx_meson_init(). + */ hdmitx_init_fmt_attr(hdev); tx_comm->hpd_state = !!hdev->tx_hw.cntlmisc(&hdev->tx_hw, diff --git a/drivers/media/vout/hdmitx21/hdmi_tx_scdc.c b/drivers/media/vout/hdmitx21/hdmi_tx_scdc.c index 15179efa7..583c8054d 100644 --- a/drivers/media/vout/hdmitx21/hdmi_tx_scdc.c +++ b/drivers/media/vout/hdmitx21/hdmi_tx_scdc.c @@ -11,7 +11,8 @@ void scdc21_config(struct hdmitx_dev *hdev) { /* TMDS 1/40 & Scramble */ - scdc21_wr_sink(SCDC_TMDS_CFG, hdev->para->tmds_clk_div40 ? 0x3 : 0); + scdc21_wr_sink(SCDC_TMDS_CFG, + hdev->tx_comm.fmt_para.tmds_clk_div40 ? 0x3 : 0); } /* update CED, 10.4.1.8 */ diff --git a/drivers/media/vout/hdmitx21/hdmi_tx_video.c b/drivers/media/vout/hdmitx21/hdmi_tx_video.c index c6044e83c..7296d3033 100644 --- a/drivers/media/vout/hdmitx21/hdmi_tx_video.c +++ b/drivers/media/vout/hdmitx21/hdmi_tx_video.c @@ -30,7 +30,7 @@ static void hdmi_set_vend_spec_infofram(struct hdmitx_dev *hdev, static void construct_avi_packet(struct hdmitx_dev *hdev) { struct hdmi_avi_infoframe *info = &hdev->infoframes.avi.avi; - struct hdmi_format_para *para = hdev->para; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; hdmi_avi_infoframe_init(info); @@ -88,7 +88,7 @@ static int is_dvi_device(struct rx_cap *prxcap) int hdmitx21_set_display(struct hdmitx_dev *hdev, enum hdmi_vic videocode) { - struct hdmi_format_para *param = NULL; + struct hdmi_format_para *param = &hdev->tx_comm.fmt_para; enum hdmi_vic vic; int ret = -1; @@ -100,12 +100,6 @@ int hdmitx21_set_display(struct hdmitx_dev *hdev, enum hdmi_vic videocode) if (vic != HDMI_0_UNKNOWN && vic == videocode) hdev->tx_comm.cur_VIC = vic; - param = hdev->para; - if (!param) { - pr_info("%s[%d]\n", __func__, __LINE__); - return ret; - } - if (param->cs == HDMI_COLORSPACE_YUV444) if (!(hdev->tx_comm.rxcap.native_Mode & (1 << 5))) { param->cs = HDMI_COLORSPACE_YUV422; @@ -132,8 +126,8 @@ int hdmitx21_set_display(struct hdmitx_dev *hdev, enum hdmi_vic videocode) pr_info(VID "rx edid only support RGB format\n"); if (videocode >= HDMITX_VESA_OFFSET) { - hdev->para->cs = HDMI_COLORSPACE_RGB; - hdev->para->cd = COLORDEPTH_24B; + param->cs = HDMI_COLORSPACE_RGB; + param->cd = COLORDEPTH_24B; pr_info("hdmitx: VESA only support RGB format\n"); } diff --git a/drivers/media/vout/hdmitx21/hdmi_tx_vrr.c b/drivers/media/vout/hdmitx21/hdmi_tx_vrr.c index f362ed1a6..a27753397 100644 --- a/drivers/media/vout/hdmitx21/hdmi_tx_vrr.c +++ b/drivers/media/vout/hdmitx21/hdmi_tx_vrr.c @@ -918,15 +918,12 @@ int hdmitx_set_fr_hint(int rate, void *data) struct vrr_conf_para para; enum TARGET_FRAME_RATE tfr = TFR_QMSVRR_INACTIVE; int tmp_rate; + struct hdmi_format_para *fmt_para = &hdev->tx_comm.fmt_para; hdmitx_vrr_disable(); - if (!hdev->para) { - para.vrr_enabled = 0; - return 0; - } /* check current rate, should less or equal than current rate of BRR */ - tmp_rate = hdev->para->timing.v_freq / 10; + tmp_rate = fmt_para->timing.v_freq / 10; if (rate < 2397 || rate > 120000 || rate > tmp_rate) { pr_info("vrr rate over range %d [2397~%d]\n", rate, tmp_rate); return 0; @@ -942,7 +939,7 @@ int hdmitx_set_fr_hint(int rate, void *data) } para.duration = rate; - para.brr_vic = hdev->para->timing.vic; + para.brr_vic = fmt_para->timing.vic; if (para.type == T_VRR_QMS) { tfr = vsync_match_to_tfr(rate); if (tfr == TFR_QMSVRR_INACTIVE || tfr == TFR_MAX) { @@ -1013,9 +1010,7 @@ static struct vinfo_s *hdmitx_get_curvinfo(void *data) { struct hdmitx_dev *hdev = get_hdmitx21_device(); - if (!hdev->para) - return NULL; - return &hdev->para->hdmitx_vinfo; + return &hdev->tx_comm.fmt_para.hdmitx_vinfo; } void hdmitx_register_vrr(struct hdmitx_dev *hdev) diff --git a/drivers/media/vout/hdmitx21/hw/enc_cfg_hw.c b/drivers/media/vout/hdmitx21/hw/enc_cfg_hw.c index 5b17c3d25..98f1c53cb 100644 --- a/drivers/media/vout/hdmitx21/hw/enc_cfg_hw.c +++ b/drivers/media/vout/hdmitx21/hw/enc_cfg_hw.c @@ -48,10 +48,7 @@ static void config_tv_enc_calc(struct hdmitx_dev *hdev, enum hdmi_vic vic) bool y420_mode = 0; int hpara_div = 1; - if (!hdev || !hdev->para) - return; - - if (hdev->para->cs == HDMI_COLORSPACE_YUV420) + if (hdev->tx_comm.fmt_para.cs == HDMI_COLORSPACE_YUV420) y420_mode = 1; tp = hdmitx21_gettiming_from_vic(vic); if (!tp) { @@ -402,9 +399,6 @@ void set_tv_encp_new(struct hdmitx_dev *hdev, u32 enc_index, enum hdmi_vic vic, // VENC2A 0x23 reg_offset = enc_index == 0 ? 0 : enc_index == 1 ? 0x600 : 0x800; - if (!hdev || !hdev->para) - return; - switch (vic) { case HDMI_5_1920x1080i60_16x9: case HDMI_46_1920x1080i120_16x9: @@ -417,7 +411,7 @@ void set_tv_encp_new(struct hdmitx_dev *hdev, u32 enc_index, enum hdmi_vic vic, break; } - if (hdev->frl_rate && hdev->para->cs != HDMI_COLORSPACE_YUV420) + if (hdev->frl_rate && hdev->tx_comm.fmt_para.cs != HDMI_COLORSPACE_YUV420) hd21_set_reg_bits(ENCP_VIDEO_MODE_ADV, 1, 0, 3); else hd21_set_reg_bits(ENCP_VIDEO_MODE_ADV, 0, 0, 3); diff --git a/drivers/media/vout/hdmitx21/hw/hdmi_tx_hw.c b/drivers/media/vout/hdmitx21/hw/hdmi_tx_hw.c index 6f19d20ad..8812aef30 100644 --- a/drivers/media/vout/hdmitx21/hw/hdmi_tx_hw.c +++ b/drivers/media/vout/hdmitx21/hw/hdmi_tx_hw.c @@ -341,6 +341,7 @@ static enum hdmi_vic _get_vic_from_vsif(struct hdmitx_dev *hdev) static void hdmi_hwp_init(struct hdmitx_dev *hdev, u8 reset) { u32 data32; + struct hdmi_format_para tmp_para; if (hdev->data->chip_type >= MESON_CPU_ID_S5) { hd21_set_reg_bits(CLKCTRL_VID_CLK0_CTRL, 7, 0, 3); @@ -371,31 +372,23 @@ static void hdmi_hwp_init(struct hdmitx_dev *hdev, u8 reset) if (ret < 0) { pr_info("hdmitx21: parsing AVI failed %d\n", ret); } else { - if (!hdev->para) - return; - if (hdev->para) { - hdev->para->cs = avi->colorspace; - hdev->para->cd = _get_colordepth(); - if (hdev->para->cs == HDMI_COLORSPACE_YUV422) - hdev->para->cd = COLORDEPTH_36B; - hdmitx21_fmt_attr(hdev); - vic = avi->video_code; - if (vic == HDMI_0_UNKNOWN) - vic = _get_vic_from_vsif(hdev); - hdev->tx_comm.cur_VIC = vic; - tp = hdmitx21_gettiming_from_vic(vic); - if (tp) { - name = tp->sname ? tp->sname : tp->name; - hdev->para = hdmitx21_get_fmtpara(name, - hdev->tx_comm.fmt_attr); - } - } else { - pr_info("hdmitx21: failed to get para\n"); - hdev->para->cs = HDMI_COLORSPACE_YUV444; - hdev->para->cd = COLORDEPTH_24B; + tmp_para.cs = avi->colorspace; + tmp_para.cd = _get_colordepth(); + if (tmp_para.cs == HDMI_COLORSPACE_YUV422) + tmp_para.cd = COLORDEPTH_36B; + hdmitx21_rebuild_fmt_attr_str(hdev, &tmp_para); + vic = avi->video_code; + if (vic == HDMI_0_UNKNOWN) + vic = _get_vic_from_vsif(hdev); + hdev->tx_comm.cur_VIC = vic; + tp = hdmitx21_gettiming_from_vic(vic); + if (tp) { + name = tp->sname ? tp->sname : tp->name; + hdmitx21_get_fmtpara(name, + hdev->tx_comm.fmt_attr, &hdev->tx_comm.fmt_para); } pr_info("hdmitx21: parsing AVI CS%d CD%d VIC%d\n", - avi->colorspace, hdev->para->cd, hdev->tx_comm.cur_VIC); + avi->colorspace, hdev->tx_comm.fmt_para.cd, hdev->tx_comm.cur_VIC); } return; } @@ -541,7 +534,7 @@ static void set_phy_by_mode(u32 mode) set21_phy_by_mode_t7(mode); break; case MESON_CPU_ID_S5: - tmds_clk = hdev->para->tmds_clk; + tmds_clk = hdev->tx_comm.fmt_para.tmds_clk; pr_info("%s[%d] tmds_clk %d\n", __func__, __LINE__, tmds_clk); hdmitx_set_s5_phypara(hdev->frl_rate, tmds_clk); break; @@ -583,9 +576,9 @@ do { \ RESET_HDMI_PHY(); #undef RESET_HDMI_PHY - if (hdev->para->tmds_clk > 340000) + if (hdev->tx_comm.fmt_para.tmds_clk > 340000) set_phy_by_mode(HDMI_PHYPARA_6G); - else if (hdev->para->tmds_clk > 290000) + else if (hdev->tx_comm.fmt_para.tmds_clk > 290000) set_phy_by_mode(HDMI_PHYPARA_3G); else set_phy_by_mode(HDMI_PHYPARA_DEF); @@ -689,7 +682,7 @@ void enable_crt_video_hdmi(u32 enable, u32 in_sel, u8 enc_sel) u32 addr_viid_clk02; u32 addr_vid_clk022; struct hdmitx_dev *hdev = get_hdmitx21_device(); - struct hdmi_format_para *para = hdev->para; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; addr_vid_clk02 = (enc_sel == 0) ? CLKCTRL_VID_CLK0_CTRL : CLKCTRL_VID_CLK2_CTRL; addr_viid_clk02 = (enc_sel == 0) ? CLKCTRL_VIID_CLK0_CTRL : CLKCTRL_VIID_CLK2_CTRL; @@ -762,7 +755,7 @@ MODULE_PARM_DESC(dfm_type, "for dfm debug"); static int hdmitx_set_dispmode(struct hdmitx_dev *hdev) { - struct hdmi_format_para *para = hdev->para; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; u32 data32; enum hdmi_vic vic = para->timing.vic; struct vinfo_s *vinfo = NULL; @@ -893,7 +886,7 @@ static int hdmitx_set_dispmode(struct hdmitx_dev *hdev) data32 |= (1920 << 0); // [13: 0] cntl_hdcp22_min_size_h hdmitx21_wr_reg(HDMITX_TOP_HDCP22_MIN_SIZE, data32); - hdev->tx_comm.cur_VIC = hdev->para->timing.vic; + hdev->tx_comm.cur_VIC = para->timing.vic; //[4] reg_bypass_video_path // For non-DSC, set to bit4 as 0 @@ -961,7 +954,7 @@ static int hdmitx_set_dispmode(struct hdmitx_dev *hdev) data32 |= 1 << 28; } hd21_write_reg(VPU_HDMI_SETTING, data32); - if (hdev->data->chip_type >= MESON_CPU_ID_S5 && hdev->para->cs == HDMI_COLORSPACE_RGB) + if (hdev->data->chip_type >= MESON_CPU_ID_S5 && para->cs == HDMI_COLORSPACE_RGB) hd21_set_reg_bits(VPU_HDMI_SETTING, 4, 16, 3); // [ 1] src_sel_encp: Enable ENCI or ENCP output to HDMI hd21_set_reg_bits(VPU_HDMI_SETTING, 1, (hdev->enc_idx == 0) ? 0 : 1, 1); @@ -969,11 +962,11 @@ static int hdmitx_set_dispmode(struct hdmitx_dev *hdev) if (hdev->frl_rate) { hd21_set_reg_bits(VPU_HDMI_SETTING, 0, 20, 4); hd21_set_reg_bits(VPU_HDMI_SETTING, 0, 24, 4); - if (hdev->para->cs != HDMI_COLORSPACE_YUV420) + if (para->cs != HDMI_COLORSPACE_YUV420) hd21_set_reg_bits(VPU_HDMI_SETTING, 1, 1, 1); } hd21_set_reg_bits(VPU_HDMI_SETTING, 0, 16, 3); //hard code - if (!hdev->frl_rate && hdev->para->cs == HDMI_COLORSPACE_YUV420) { + if (!hdev->frl_rate && para->cs == HDMI_COLORSPACE_YUV420) { hd21_set_reg_bits(VPU_HDMI_SETTING, 0, 20, 8); hd21_set_reg_bits(VPU_HDMI_SETTING, 1, 8, 8); } @@ -989,7 +982,6 @@ static int hdmitx_set_dispmode(struct hdmitx_dev *hdev) if (hdev->data->chip_type >= MESON_CPU_ID_S5) { hdmitx_dfm_cfg(0, 0); if (hdev->frl_rate) { - struct hdmi_format_para *para = hdev->para; enum hdmi_colorspace cs = para->cs; enum hdmi_color_depth cd = para->cd; u32 tribytes_per_line = para->timing.h_active; @@ -1293,27 +1285,26 @@ static void set_aud_acr_pkt(struct hdmitx_dev *hdev, { u32 aud_n_para; u32 char_rate = 0; - struct hdmi_format_para *para; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; - if (!hdev) + if (!hdev || !para) return; - para = hdev->para; - if (!para) + if (para->vic == HDMI_0_UNKNOWN) return; /* if current mode is 59.94hz not 60hz, char_rate will shift down 0.1% */ - char_rate = hdev->para->timing.pixel_freq; - if (para && para->timing.name && likely_frac_rate_mode(para->timing.name)) + char_rate = para->timing.pixel_freq; + if (para->timing.name && likely_frac_rate_mode(para->timing.name)) if (hdev->tx_comm.frac_rate_policy) char_rate = char_rate * 1000 / 1001; - if (hdev->para->cs == HDMI_COLORSPACE_YUV422) + if (para->cs == HDMI_COLORSPACE_YUV422) aud_n_para = hdmi21_get_aud_n_paras(audio_param->sample_rate, COLORDEPTH_24B, char_rate); else aud_n_para = hdmi21_get_aud_n_paras(audio_param->sample_rate, - hdev->para->cd, char_rate); + para->cd, char_rate); if (hdev->frl_rate) aud_n_para = hdmi21_get_frl_aud_n_paras(audio_param->sample_rate, hdev->frl_rate); hdmitx21_set_reg_bits(ACR_CTS_CLK_DIV_IVCTX, hdev->frl_rate ? 1 : 0, 4, 1); @@ -1658,6 +1649,7 @@ static void hdmitx_debug(struct hdmitx_dev *hdev, const char *buf) unsigned long adr = 0; unsigned long value = 0; static enum hdmitx_event event_type = HDMITX_NONE_EVENT; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; struct vinfo_s *vinfo; if (!buf) @@ -1729,10 +1721,7 @@ static void hdmitx_debug(struct hdmitx_dev *hdev, const char *buf) hdev->tx_hw.cntlmisc(&hdev->tx_hw, MISC_I2C_REACTIVE, 0); return; } else if (strncmp(tmpbuf, "bist", 4) == 0) { - if (!hdev->para) - return; - - vinfo = &hdev->para->hdmitx_vinfo; + vinfo = ¶->hdmitx_vinfo; if (strncmp(tmpbuf + 4, "off", 3) == 0) { if (vinfo->viu_mux == VIU_MUX_ENCI) { hd21_write_reg(ENCI_TST_EN, 0); @@ -1763,7 +1752,7 @@ static void hdmitx_debug(struct hdmitx_dev *hdev, const char *buf) return; } /* for encp including 1080i */ - hdmi_avi_infoframe_config(CONF_AVI_CS, hdev->para->cs); + hdmi_avi_infoframe_config(CONF_AVI_CS, para->cs); hd21_set_reg_bits(ENCP_VIDEO_MODE_ADV, 0, 3, 1); hd21_write_reg(VENC_VIDEO_TST_EN, 1); if (strncmp(tmpbuf + 4, "line", 4) == 0) { @@ -1786,15 +1775,12 @@ static void hdmitx_debug(struct hdmitx_dev *hdev, const char *buf) } if (strncmp(tmpbuf + 4, "auto", 4) == 0) { const struct hdmi_timing *t; - - if (!hdev->para) - return; - t = &hdev->para->timing; + t = ¶->timing; value = t->h_active; /* when FRL works, here will be half rate */ if (hdev->frl_rate) { value /= 2; - if (hdev->para->cs == HDMI_COLORSPACE_YUV420) + if (para->cs == HDMI_COLORSPACE_YUV420) value /= 2; } hd21_write_reg(VENC_VIDEO_TST_CLRBAR_STRT, 0x113); @@ -1807,18 +1793,16 @@ static void hdmitx_debug(struct hdmitx_dev *hdev, const char *buf) u32 width = 1920; u32 height = 1080; - if (!hdev->para) - return; if (hdev->data->chip_type < MESON_CPU_ID_S5) { pr_info("s5 or later support x pattern\n"); return; } - t = &hdev->para->timing; + t = ¶->timing; width = t->h_active; /* when FRL works, here will be half rate */ if (hdev->frl_rate) { width /= 2; - if (hdev->para->cs == HDMI_COLORSPACE_YUV420) + if (para->cs == HDMI_COLORSPACE_YUV420) width /= 2; } height = t->v_active; @@ -2005,9 +1989,7 @@ static void hdmitx_debug_bist(struct hdmitx_dev *hdev, u32 num) u32 h_active, video_start; struct vinfo_s *vinfo; - if (!hdev->para) - return; - vinfo = &hdev->para->hdmitx_vinfo; + vinfo = &hdev->tx_comm.fmt_para.hdmitx_vinfo; switch (num) { case 1: case 2: @@ -2338,7 +2320,8 @@ static int hdmitx_hdmi_dvi_config(struct hdmitx_dev *hdev, u32 dvi_mode) { if (dvi_mode == 1) - hdmitx_csc_config(TX_INPUT_COLOR_FORMAT, HDMI_COLORSPACE_RGB, hdev->para->cd); + hdmitx_csc_config(TX_INPUT_COLOR_FORMAT, HDMI_COLORSPACE_RGB, + hdev->tx_comm.fmt_para.cd); return 0; } @@ -2395,7 +2378,8 @@ static int hdmitx_cntl_config(struct hdmitx_hw_common *tx_hw, u32 cmd, case CONF_CLR_VSDB_PACKET: break; case CONF_VIDEO_MAPPING: - config_video_mapping(hdev->para->cs, hdev->para->cd); + config_video_mapping(hdev->tx_comm.fmt_para.cs, + hdev->tx_comm.fmt_para.cd); break; case CONF_CLR_AUDINFO_PACKET: break; @@ -2608,7 +2592,7 @@ static void hdmi_phy_wakeup(struct hdmitx_dev *hdev) static void config_hdmi21_tx(struct hdmitx_dev *hdev) { - struct hdmi_format_para *para = hdev->para; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; u8 color_depth = COLORDEPTH_24B; // Pixel bit width: 4=24-bit; 5=30-bit; 6=36-bit; 7=48-bit. // Pixel format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420. u8 input_color_format = HDMI_COLORSPACE_YUV444; @@ -2904,8 +2888,10 @@ static void hdmitx_csc_config(u8 input_color_format, static void hdmitx_set_hw(struct hdmitx_dev *hdev) { + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; + pr_info(HW " config hdmitx IP vic = %d cd:%d cs: %d\n", - hdev->para->timing.vic, hdev->para->cd, hdev->para->cs); + para->timing.vic, para->cd, para->cs); config_hdmi21_tx(hdev); } @@ -2939,7 +2925,7 @@ int hdmitx21_read_phy_status(void) void hdmitx21_dither_config(struct hdmitx_dev *hdev) { - struct hdmi_format_para *para = hdev->para; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; if (para->cd == COLORDEPTH_24B && hdmitx21_dv_en() == 0) hd21_set_reg_bits(VPU_HDMI_DITH_CNTL, 1, 4, 1); @@ -2956,14 +2942,15 @@ void hdmitx_dhdr_send(u8 *body, int max_size) int blank_lines; int hdr_emp_num; struct hdmitx_dev *hdev = get_hdmitx21_device(); + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; if (!body) { hdmitx21_wr_reg(D_HDR_INSERT_CTRL_IVCTX, 0); return; } - active_lines = hdev->para->timing.v_active; - blank_lines = hdev->para->timing.v_blank; + active_lines = para->timing.v_active; + blank_lines = para->timing.v_blank; hdr_emp_num = (3 - 1) * 28 + 21; //emds total send 3 packet as one dhdr // step1: hdr timing diff --git a/drivers/media/vout/hdmitx21/hw/hw_clk.c b/drivers/media/vout/hdmitx21/hw/hw_clk.c index 25ab1f842..cc63ee774 100644 --- a/drivers/media/vout/hdmitx21/hw/hw_clk.c +++ b/drivers/media/vout/hdmitx21/hw/hw_clk.c @@ -802,19 +802,17 @@ static void set_hdmitx_s5_htx_pll(struct hdmitx_dev *hdev) u32 base_pixel_clk = 25200; u32 htx_vco = 5940000; u32 div = 1; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; - if (!hdev || !hdev->para) - return; - - vic = hdev->para->timing.vic; - cs = hdev->para->cs; - cd = hdev->para->cd; + vic = para->timing.vic; + cs = para->cs; + cd = para->cd; if (vic == HDMI_0_UNKNOWN) { pr_err("%s[%d] not valid vic %d\n", __func__, __LINE__, vic); return; } - base_pixel_clk = hdev->para->timing.pixel_freq; + base_pixel_clk = para->timing.pixel_freq; if (base_pixel_clk < 25175 || base_pixel_clk > 5940000) { pr_err("%s[%d] not valid pixel clock %d\n", __func__, __LINE__, base_pixel_clk); return; @@ -905,9 +903,10 @@ static void set_hdmitx_htx_pll(struct hdmitx_dev *hdev, int i = 0; int j = 0; struct hw_enc_clk_val_group *p_enc = NULL; - enum hdmi_vic vic = hdev->para->timing.vic; - enum hdmi_colorspace cs = hdev->para->cs; - enum hdmi_color_depth cd = hdev->para->cd; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; + enum hdmi_vic vic = para->timing.vic; + enum hdmi_colorspace cs = para->cs; + enum hdmi_color_depth cd = para->cd; #ifndef CONFIG_AMLOGIC_ZAPPER_CUT u8 clk_div_val = VID_PLL_DIV_5; #endif @@ -1078,41 +1077,43 @@ static void hdmitx_set_fpll_without_dsc(struct hdmitx_dev *hdev) u32 tmp_clk = 0; u32 pixel_od = 0; enum hdmi_vic vic = HDMI_0_UNKNOWN; + struct hdmi_format_para *para; - if (!hdev && !hdev->para) + if (!hdev) return; - vic = hdev->para->timing.vic; - tmp_clk = hdev->para->timing.pixel_freq; + para = &hdev->tx_comm.fmt_para; + vic = para->timing.vic; + tmp_clk = para->timing.pixel_freq; if (hdev->frl_rate) tmp_clk /= 2; - switch (hdev->para->cs) { + switch (para->cs) { case HDMI_COLORSPACE_RGB: case HDMI_COLORSPACE_YUV444: - if (hdev->para->cd == COLORDEPTH_30B) { + if (para->cd == COLORDEPTH_30B) { tmp_clk = tmp_clk * 5 / 4; pixel_od = 1; } - if (hdev->para->cd == COLORDEPTH_36B) { + if (para->cd == COLORDEPTH_36B) { tmp_clk = tmp_clk * 3 / 2; pixel_od = 2; } - if (hdev->para->cd == COLORDEPTH_48B) { + if (para->cd == COLORDEPTH_48B) { tmp_clk = tmp_clk * 2; pixel_od = 4; } break; case HDMI_COLORSPACE_YUV420: tmp_clk /= 2; - if (hdev->para->cd == COLORDEPTH_30B) { + if (para->cd == COLORDEPTH_30B) { tmp_clk = tmp_clk * 5 / 4; pixel_od = 1; } - if (hdev->para->cd == COLORDEPTH_36B) { + if (para->cd == COLORDEPTH_36B) { tmp_clk = tmp_clk * 3 / 2; pixel_od = 2; } - if (hdev->para->cd == COLORDEPTH_48B) { + if (para->cd == COLORDEPTH_48B) { tmp_clk *= 1; pixel_od = 4; } @@ -1156,7 +1157,7 @@ static void hdmitx_set_fpll_with_dsc(struct hdmitx_dev *hdev) u32 tmp_clk = 0; u32 pixel_od = 0; - if (!hdev && !hdev->para) + if (!hdev) return; /* HARD CODE, FRL8G4L 4320p60 y420 8bit, HDMI 2.1 Spec, Page 281 */ @@ -1196,30 +1197,32 @@ void hdmitx_set_gp2pll(struct hdmitx_dev *hdev) u32 gp2pll_vco = 2376000; u32 div = 1; u32 tmp_clk = 0; + struct hdmi_format_para *para; - if (!hdev && !hdev->para) + if (!hdev) return; - tmp_clk = hdev->para->timing.pixel_freq; + para = &hdev->tx_comm.fmt_para; + tmp_clk = para->timing.pixel_freq; if (hdev->frl_rate) tmp_clk /= 2; - switch (hdev->para->cs) { + switch (para->cs) { case HDMI_COLORSPACE_RGB: case HDMI_COLORSPACE_YUV444: - if (hdev->para->cd == COLORDEPTH_30B) + if (para->cd == COLORDEPTH_30B) tmp_clk = tmp_clk * 5 / 4; - if (hdev->para->cd == COLORDEPTH_36B) + if (para->cd == COLORDEPTH_36B) tmp_clk = tmp_clk * 3 / 2; - if (hdev->para->cd == COLORDEPTH_48B) + if (para->cd == COLORDEPTH_48B) tmp_clk = tmp_clk * 2; break; case HDMI_COLORSPACE_YUV420: tmp_clk /= 2; - if (hdev->para->cd == COLORDEPTH_30B) + if (para->cd == COLORDEPTH_30B) tmp_clk = tmp_clk * 5 / 4; - if (hdev->para->cd == COLORDEPTH_36B) + if (para->cd == COLORDEPTH_36B) tmp_clk = tmp_clk * 3 / 2; - if (hdev->para->cd == COLORDEPTH_48B) + if (para->cd == COLORDEPTH_48B) tmp_clk *= 1; break; case HDMI_COLORSPACE_YUV422: @@ -1256,7 +1259,7 @@ void hdmitx_set_clkdiv(struct hdmitx_dev *hdev) static void hdmitx_check_frac_rate(struct hdmitx_dev *hdev) { - struct hdmi_format_para *para = hdev->para; + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; frac_rate = hdev->tx_comm.frac_rate_policy; if (para && para->timing.name && likely_frac_rate_mode(para->timing.name)) { @@ -1409,7 +1412,7 @@ void hdmitx21_set_clk(struct hdmitx_dev *hdev) void hdmitx21_disable_clk(struct hdmitx_dev *hdev) { /* cts_encp/enci_clk */ - if (hdev->para->hdmitx_vinfo.viu_mux == VIU_MUX_ENCI) + if (hdev->tx_comm.fmt_para.hdmitx_vinfo.viu_mux == VIU_MUX_ENCI) hdmitx_disable_enci_clk(hdev); else hdmitx_disable_encp_clk(hdev); diff --git a/drivers/media/vout/hdmitx21/hw/hw_s5.c b/drivers/media/vout/hdmitx21/hw/hw_s5.c index 23c9337f3..2797a6e23 100644 --- a/drivers/media/vout/hdmitx21/hw/hw_s5.c +++ b/drivers/media/vout/hdmitx21/hw/hw_s5.c @@ -203,11 +203,11 @@ void set21_s5_htxpll_clk_out(const u32 clk, const u32 div) enum hdmi_colorspace cs = HDMI_COLORSPACE_YUV444; enum hdmi_color_depth cd = COLORDEPTH_24B; - if (!hdev || !hdev->para) + if (!hdev) return; - cs = hdev->para->cs; - cd = hdev->para->cd; + cs = hdev->tx_comm.fmt_para.cs; + cd = hdev->tx_comm.fmt_para.cd; pr_info("%s[%d] htxpll vco %d div %d\n", __func__, __LINE__, clk, div); @@ -357,12 +357,12 @@ void hdmitx_set_s5_gp2pll(u32 clk, u32 div) void hdmitx_set_s5_clkdiv(struct hdmitx_dev *hdev) { - if (!hdev && !hdev->para) + if (!hdev) return; /* cts_htx_tmds_clk selects the htx_tmds20_clk or fll_tmds_clk */ hd21_set_reg_bits(CLKCTRL_HTX_CLK_CTRL1, hdev->frl_rate ? 1 : 0, 25, 2); - if (!hdev->frl_rate && hdev->para->cs == HDMI_COLORSPACE_YUV420) + if (!hdev->frl_rate && hdev->tx_comm.fmt_para.cs == HDMI_COLORSPACE_YUV420) hd21_set_reg_bits(CLKCTRL_HTX_CLK_CTRL1, 1, 16, 7); else hd21_set_reg_bits(CLKCTRL_HTX_CLK_CTRL1, 0, 16, 7); diff --git a/drivers/media/vout/hdmitx21/hw/hw_t7.c b/drivers/media/vout/hdmitx21/hw/hw_t7.c index 07bc66cd7..a52f7b139 100644 --- a/drivers/media/vout/hdmitx21/hw/hw_t7.c +++ b/drivers/media/vout/hdmitx21/hw/hw_t7.c @@ -37,6 +37,7 @@ static bool set_hpll_hclk_v1(u32 m, u32 frac_val) { int ret = 0; struct hdmitx_dev *hdev = get_hdmitx21_device(); + struct hdmi_format_para *para = &hdev->tx_comm.fmt_para; hd21_write_reg(ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | (m & 0xff)); hd21_set_reg_bits(ANACTRL_HDMIPLL_CTRL0, 0x3, 28, 2); @@ -44,11 +45,11 @@ static bool set_hpll_hclk_v1(u32 m, u32 frac_val) hd21_write_reg(ANACTRL_HDMIPLL_CTRL2, 0x00000000); if (frac_val == 0x8148) { - if ((hdev->para->timing.vic == HDMI_96_3840x2160p50_16x9 || - hdev->para->timing.vic == HDMI_97_3840x2160p60_16x9 || - hdev->para->timing.vic == HDMI_106_3840x2160p50_64x27 || - hdev->para->timing.vic == HDMI_107_3840x2160p60_64x27) && - hdev->para->cs != HDMI_COLORSPACE_YUV420) { + if ((para->timing.vic == HDMI_96_3840x2160p50_16x9 || + para->timing.vic == HDMI_97_3840x2160p60_16x9 || + para->timing.vic == HDMI_106_3840x2160p50_64x27 || + para->timing.vic == HDMI_107_3840x2160p60_64x27) && + para->cs != HDMI_COLORSPACE_YUV420) { hd21_write_reg(ANACTRL_HDMIPLL_CTRL3, 0x6a685c00); hd21_write_reg(ANACTRL_HDMIPLL_CTRL4, 0x11551293); } else { @@ -56,13 +57,13 @@ static bool set_hpll_hclk_v1(u32 m, u32 frac_val) hd21_write_reg(ANACTRL_HDMIPLL_CTRL4, 0x44331290); } } else { - if ((hdev->para->timing.vic == HDMI_96_3840x2160p50_16x9 || - hdev->para->timing.vic == HDMI_97_3840x2160p60_16x9 || - hdev->para->timing.vic == HDMI_106_3840x2160p50_64x27 || - hdev->para->timing.vic == HDMI_107_3840x2160p60_64x27 || - hdev->para->timing.vic == HDMI_101_4096x2160p50_256x135 || - hdev->para->timing.vic == HDMI_102_4096x2160p60_256x135) && - hdev->para->cs != HDMI_COLORSPACE_YUV420) { + if ((para->timing.vic == HDMI_96_3840x2160p50_16x9 || + para->timing.vic == HDMI_97_3840x2160p60_16x9 || + para->timing.vic == HDMI_106_3840x2160p50_64x27 || + para->timing.vic == HDMI_107_3840x2160p60_64x27 || + para->timing.vic == HDMI_101_4096x2160p50_256x135 || + para->timing.vic == HDMI_102_4096x2160p60_256x135) && + para->cs != HDMI_COLORSPACE_YUV420) { hd21_write_reg(ANACTRL_HDMIPLL_CTRL3, 0x6a685c00); hd21_write_reg(ANACTRL_HDMIPLL_CTRL4, 0x11551293); } else { diff --git a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h index 9ec5b000f..0b45700d7 100644 --- a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h +++ b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h @@ -11,17 +11,6 @@ #include #include -/* HDMI VIC definitions */ - -/* HDMITX_VIC420_OFFSET and HDMITX_VIC_MASK are associated with - * VIC_MAX_VALID_MODE and VIC_MAX_NUM in hdmi_tx_module.h - */ -#define HDMITX_VIC420_OFFSET 0x100 -#define HDMITX_VIC420_FAKE_OFFSET 0x200 -#define HDMITX_VESA_OFFSET 0x300 - -#define HDMITX_VIC_MASK 0xff - enum hdmi_tf_type { HDMI_NONE = 0, /* HDMI_HDR_TYPE, HDMI_DV_TYPE, and HDMI_HDR10P_TYPE @@ -39,177 +28,121 @@ enum hdmi_tf_type { HDMI_HDR10P_DV_VSIF = HDMI_HDR10P_TYPE | 1, }; -enum hdmi_vic { - /* Refer to CEA 861-D */ - HDMI_UNKNOWN = 0, - HDMI_640x480p60_4x3 = 1, - HDMI_720x480p60_4x3 = 2, - HDMI_720x480p60_16x9 = 3, - HDMI_1280x720p60_16x9 = 4, - HDMI_1920x1080i60_16x9 = 5, - HDMI_720x480i60_4x3 = 6, - HDMI_720x480i60_16x9 = 7, - HDMI_720x240p60_4x3 = 8, - HDMI_720x240p60_16x9 = 9, - HDMI_2880x480i60_4x3 = 10, - HDMI_2880x480i60_16x9 = 11, - HDMI_2880x240p60_4x3 = 12, - HDMI_2880x240p60_16x9 = 13, - HDMI_1440x480p60_4x3 = 14, - HDMI_1440x480p60_16x9 = 15, - HDMI_1920x1080p60_16x9 = 16, - HDMI_720x576p50_4x3 = 17, - HDMI_720x576p50_16x9 = 18, - HDMI_1280x720p50_16x9 = 19, - HDMI_1920x1080i50_16x9 = 20, - HDMI_720x576i50_4x3 = 21, - HDMI_720x576i50_16x9 = 22, - HDMI_720x288p_4x3 = 23, - HDMI_720x288p_16x9 = 24, - HDMI_2880x576i50_4x3 = 25, - HDMI_2880x576i50_16x9 = 26, - HDMI_2880x288p50_4x3 = 27, - HDMI_2880x288p50_16x9 = 28, - HDMI_1440x576p_4x3 = 29, - HDMI_1440x576p_16x9 = 30, - HDMI_1920x1080p50_16x9 = 31, - HDMI_1920x1080p24_16x9 = 32, - HDMI_1920x1080p25_16x9 = 33, - HDMI_1920x1080p30_16x9 = 34, - HDMI_2880x480p60_4x3 = 35, - HDMI_2880x480p60_16x9 = 36, - HDMI_2880x576p50_4x3 = 37, - HDMI_2880x576p50_16x9 = 38, - HDMI_1920x1080i_t1250_50_16x9 = 39, - HDMI_1920x1080i100_16x9 = 40, - HDMI_1280x720p100_16x9 = 41, - HDMI_720x576p100_4x3 = 42, - HDMI_720x576p100_16x9 = 43, - HDMI_720x576i100_4x3 = 44, - HDMI_720x576i100_16x9 = 45, - HDMI_1920x1080i120_16x9 = 46, - HDMI_1280x720p120_16x9 = 47, - HDMI_720x480p120_4x3 = 48, - HDMI_720x480p120_16x9 = 49, - HDMI_720x480i120_4x3 = 50, - HDMI_720x480i120_16x9 = 51, - HDMI_720x576p200_4x3 = 52, - HDMI_720x576p200_16x9 = 53, - HDMI_720x576i200_4x3 = 54, - HDMI_720x576i200_16x9 = 55, - HDMI_720x480p240_4x3 = 56, - HDMI_720x480p240_16x9 = 57, - HDMI_720x480i240_4x3 = 58, - HDMI_720x480i240_16x9 = 59, - /* Refer to CEA 861-F */ - HDMI_1280x720p24_16x9 = 60, - HDMI_1280x720p25_16x9 = 61, - HDMI_1280x720p30_16x9 = 62, - HDMI_1920x1080p120_16x9 = 63, - HDMI_1920x1080p100_16x9 = 64, - HDMI_1280x720p24_64x27 = 65, - HDMI_1280x720p25_64x27 = 66, - HDMI_1280x720p30_64x27 = 67, - HDMI_1280x720p50_64x27 = 68, - HDMI_1280x720p60_64x27 = 69, - HDMI_1280x720p100_64x27 = 70, - HDMI_1280x720p120_64x27 = 71, - HDMI_1920x1080p24_64x27 = 72, - HDMI_1920x1080p25_64x27 = 73, - HDMI_1920x1080p30_64x27 = 74, - HDMI_1920x1080p50_64x27 = 75, - HDMI_1920x1080p60_64x27 = 76, - HDMI_1920x1080p100_64x27 = 77, - HDMI_1920x1080p120_64x27 = 78, - HDMI_1680x720p24_64x27 = 79, - HDMI_1680x720p25_64x27 = 80, - HDMI_1680x720p30_64x27 = 81, - HDMI_1680x720p50_64x27 = 82, - HDMI_1680x720p60_64x27 = 83, - HDMI_1680x720p100_64x27 = 84, - HDMI_1680x720p120_64x27 = 85, - HDMI_2560x1080p24_64x27 = 86, - HDMI_2560x1080p25_64x27 = 87, - HDMI_2560x1080p30_64x27 = 88, - HDMI_2560x1080p50_64x27 = 89, - HDMI_2560x1080p60_64x27 = 90, - HDMI_2560x1080p100_64x27 = 91, - HDMI_2560x1080p120_64x27 = 92, - HDMI_3840x2160p24_16x9 = 93, - HDMI_3840x2160p25_16x9 = 94, - HDMI_3840x2160p30_16x9 = 95, - HDMI_3840x2160p50_16x9 = 96, - HDMI_3840x2160p60_16x9 = 97, - HDMI_4096x2160p24_256x135 = 98, - HDMI_4096x2160p25_256x135 = 99, - HDMI_4096x2160p30_256x135 = 100, - HDMI_4096x2160p50_256x135 = 101, - HDMI_4096x2160p60_256x135 = 102, - HDMI_3840x2160p24_64x27 = 103, - HDMI_3840x2160p25_64x27 = 104, - HDMI_3840x2160p30_64x27 = 105, - HDMI_3840x2160p50_64x27 = 106, - HDMI_3840x2160p60_64x27 = 107, - HDMI_RESERVED = 108, - HDMI_3840x1080p120hz = 109, - HDMI_3840x1080p100hz, - HDMI_3840x540p240hz, - HDMI_3840x540p200hz, +/* Compliance with tx21 definitions */ +#define HDMI_UNKNOWN HDMI_0_UNKNOWN +#define HDMI_640x480p60_4x3 HDMI_1_640x480p60_4x3 +#define HDMI_720x480p60_4x3 HDMI_2_720x480p60_4x3 +#define HDMI_720x480p60_16x9 HDMI_3_720x480p60_16x9 +#define HDMI_1280x720p60_16x9 HDMI_4_1280x720p60_16x9 +#define HDMI_1920x1080i60_16x9 HDMI_5_1920x1080i60_16x9 +#define HDMI_720x480i60_4x3 HDMI_6_720x480i60_4x3 +#define HDMI_720x480i60_16x9 HDMI_7_720x480i60_16x9 +#define HDMI_720x240p60_4x3 HDMI_8_720x240p60_4x3 +#define HDMI_720x240p60_16x9 HDMI_9_720x240p60_16x9 +#define HDMI_2880x480i60_4x3 HDMI_10_2880x480i60_4x3 +#define HDMI_2880x480i60_16x9 HDMI_11_2880x480i60_16x9 +#define HDMI_2880x240p60_4x3 HDMI_12_2880x240p60_4x3 +#define HDMI_2880x240p60_16x9 HDMI_13_2880x240p60_16x9 +#define HDMI_1440x480p60_4x3 HDMI_14_1440x480p60_4x3 +#define HDMI_1440x480p60_16x9 HDMI_15_1440x480p60_16x9 +#define HDMI_1920x1080p60_16x9 HDMI_16_1920x1080p60_16x9 +#define HDMI_720x576p50_4x3 HDMI_17_720x576p50_4x3 +#define HDMI_720x576p50_16x9 HDMI_18_720x576p50_16x9 +#define HDMI_1280x720p50_16x9 HDMI_19_1280x720p50_16x9 +#define HDMI_1920x1080i50_16x9 HDMI_20_1920x1080i50_16x9 +#define HDMI_720x576i50_4x3 HDMI_21_720x576i50_4x3 +#define HDMI_720x576i50_16x9 HDMI_22_720x576i50_16x9 +#define HDMI_720x288p_4x3 HDMI_23_720x288p_4x3 +#define HDMI_720x288p_16x9 HDMI_24_720x288p_16x9 +#define HDMI_2880x576i50_4x3 HDMI_25_2880x576i50_4x3 +#define HDMI_2880x576i50_16x9 HDMI_26_2880x576i50_16x9 +#define HDMI_2880x288p50_4x3 HDMI_27_2880x288p50_4x3 +#define HDMI_2880x288p50_16x9 HDMI_28_2880x288p50_16x9 +#define HDMI_1440x576p_4x3 HDMI_29_1440x576p_4x3 +#define HDMI_1440x576p_16x9 HDMI_30_1440x576p_16x9 +#define HDMI_1920x1080p50_16x9 HDMI_31_1920x1080p50_16x9 +#define HDMI_1920x1080p24_16x9 HDMI_32_1920x1080p24_16x9 +#define HDMI_1920x1080p25_16x9 HDMI_33_1920x1080p25_16x9 +#define HDMI_1920x1080p30_16x9 HDMI_34_1920x1080p30_16x9 +#define HDMI_2880x480p60_4x3 HDMI_35_2880x480p60_4x3 +#define HDMI_2880x480p60_16x9 HDMI_36_2880x480p60_16x9 +#define HDMI_2880x576p50_4x3 HDMI_37_2880x576p50_4x3 +#define HDMI_2880x576p50_16x9 HDMI_38_2880x576p50_16x9 +#define HDMI_1920x1080i_t1250_50_16x9 HDMI_39_1920x1080i_t1250_50_16x9 +#define HDMI_1920x1080i100_16x9 HDMI_40_1920x1080i100_16x9 +#define HDMI_1280x720p100_16x9 HDMI_41_1280x720p100_16x9 +#define HDMI_720x576p100_4x3 HDMI_42_720x576p100_4x3 +#define HDMI_720x576p100_16x9 HDMI_43_720x576p100_16x9 +#define HDMI_720x576i100_4x3 HDMI_44_720x576i100_4x3 +#define HDMI_720x576i100_16x9 HDMI_45_720x576i100_16x9 +#define HDMI_1920x1080i120_16x9 HDMI_46_1920x1080i120_16x9 +#define HDMI_1280x720p120_16x9 HDMI_47_1280x720p120_16x9 +#define HDMI_720x480p120_4x3 HDMI_48_720x480p120_4x3 +#define HDMI_720x480p120_16x9 HDMI_49_720x480p120_16x9 +#define HDMI_720x480i120_4x3 HDMI_50_720x480i120_4x3 +#define HDMI_720x480i120_16x9 HDMI_51_720x480i120_16x9 +#define HDMI_720x576p200_4x3 HDMI_52_720x576p200_4x3 +#define HDMI_720x576p200_16x9 HDMI_53_720x576p200_16x9 +#define HDMI_720x576i200_4x3 HDMI_54_720x576i200_4x3 +#define HDMI_720x576i200_16x9 HDMI_55_720x576i200_16x9 +#define HDMI_720x480p240_4x3 HDMI_56_720x480p240_4x3 +#define HDMI_720x480p240_16x9 HDMI_57_720x480p240_16x9 +#define HDMI_720x480i240_4x3 HDMI_58_720x480i240_4x3 +#define HDMI_720x480i240_16x9 HDMI_59_720x480i240_16x9 +#define HDMI_1280x720p24_16x9 HDMI_60_1280x720p24_16x9 +#define HDMI_1280x720p25_16x9 HDMI_61_1280x720p25_16x9 +#define HDMI_1280x720p30_16x9 HDMI_62_1280x720p30_16x9 +#define HDMI_1920x1080p120_16x9 HDMI_63_1920x1080p120_16x9 +#define HDMI_1920x1080p100_16x9 HDMI_64_1920x1080p100_16x9 +#define HDMI_1280x720p24_64x27 HDMI_65_1280x720p24_64x27 +#define HDMI_1280x720p25_64x27 HDMI_66_1280x720p25_64x27 +#define HDMI_1280x720p30_64x27 HDMI_67_1280x720p30_64x27 +#define HDMI_1280x720p50_64x27 HDMI_68_1280x720p50_64x27 +#define HDMI_1280x720p60_64x27 HDMI_69_1280x720p60_64x27 +#define HDMI_1280x720p100_64x27 HDMI_70_1280x720p100_64x27 +#define HDMI_1280x720p120_64x27 HDMI_71_1280x720p120_64x27 +#define HDMI_1920x1080p24_64x27 HDMI_72_1920x1080p24_64x27 +#define HDMI_1920x1080p25_64x27 HDMI_73_1920x1080p25_64x27 +#define HDMI_1920x1080p30_64x27 HDMI_74_1920x1080p30_64x27 +#define HDMI_1920x1080p50_64x27 HDMI_75_1920x1080p50_64x27 +#define HDMI_1920x1080p60_64x27 HDMI_76_1920x1080p60_64x27 +#define HDMI_1920x1080p100_64x27 HDMI_77_1920x1080p100_64x27 +#define HDMI_1920x1080p120_64x27 HDMI_78_1920x1080p120_64x27 +#define HDMI_1680x720p24_64x27 HDMI_79_1680x720p24_64x27 +#define HDMI_1680x720p25_64x27 HDMI_80_1680x720p25_64x27 +#define HDMI_1680x720p30_64x27 HDMI_81_1680x720p30_64x27 +#define HDMI_1680x720p50_64x27 HDMI_82_1680x720p50_64x27 +#define HDMI_1680x720p60_64x27 HDMI_83_1680x720p60_64x27 +#define HDMI_1680x720p100_64x27 HDMI_84_1680x720p100_64x27 +#define HDMI_1680x720p120_64x27 HDMI_85_1680x720p120_64x27 +#define HDMI_2560x1080p24_64x27 HDMI_86_2560x1080p24_64x27 +#define HDMI_2560x1080p25_64x27 HDMI_87_2560x1080p25_64x27 +#define HDMI_2560x1080p30_64x27 HDMI_88_2560x1080p30_64x27 +#define HDMI_2560x1080p50_64x27 HDMI_89_2560x1080p50_64x27 +#define HDMI_2560x1080p60_64x27 HDMI_90_2560x1080p60_64x27 +#define HDMI_2560x1080p100_64x27 HDMI_91_2560x1080p100_64x27 +#define HDMI_2560x1080p120_64x27 HDMI_92_2560x1080p120_64x27 +#define HDMI_3840x2160p24_16x9 HDMI_93_3840x2160p24_16x9 +#define HDMI_3840x2160p25_16x9 HDMI_94_3840x2160p25_16x9 +#define HDMI_3840x2160p30_16x9 HDMI_95_3840x2160p30_16x9 +#define HDMI_3840x2160p50_16x9 HDMI_96_3840x2160p50_16x9 +#define HDMI_3840x2160p60_16x9 HDMI_97_3840x2160p60_16x9 +#define HDMI_4096x2160p24_256x135 HDMI_98_4096x2160p24_256x135 +#define HDMI_4096x2160p25_256x135 HDMI_99_4096x2160p25_256x135 +#define HDMI_4096x2160p30_256x135 HDMI_100_4096x2160p30_256x135 +#define HDMI_4096x2160p50_256x135 HDMI_101_4096x2160p50_256x135 +#define HDMI_4096x2160p60_256x135 HDMI_102_4096x2160p60_256x135 +#define HDMI_3840x2160p24_64x27 HDMI_103_3840x2160p24_64x27 +#define HDMI_3840x2160p25_64x27 HDMI_104_3840x2160p25_64x27 +#define HDMI_3840x2160p30_64x27 HDMI_105_3840x2160p30_64x27 +#define HDMI_3840x2160p50_64x27 HDMI_106_3840x2160p50_64x27 +#define HDMI_3840x2160p60_64x27 HDMI_107_3840x2160p60_64x27 - /* - * the following vic is for those y420 mode - * they are all beyond OFFSET_HDMITX_VIC420(0x1000) - * and they has same vic with normal vic in the lower bytes. - */ - HDMI_VIC_Y420 = - HDMITX_VIC420_OFFSET, - HDMI_3840x2160p50_16x9_Y420 = - HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_16x9, - HDMI_3840x2160p60_16x9_Y420 = - HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_16x9, - HDMI_4096x2160p50_256x135_Y420 = - HDMITX_VIC420_OFFSET + HDMI_4096x2160p50_256x135, - HDMI_4096x2160p60_256x135_Y420 = - HDMITX_VIC420_OFFSET + HDMI_4096x2160p60_256x135, - HDMI_3840x2160p50_64x27_Y420 = - HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_64x27, - HDMI_3840x2160p60_64x27_Y420 = - HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_64x27, - HDMI_VIC_Y420_MAX, - - HDMI_VIC_FAKE = HDMITX_VIC420_FAKE_OFFSET, - HDMIV_640x480p60hz = HDMITX_VESA_OFFSET, - HDMIV_800x480p60hz, - HDMIV_800x600p60hz, - HDMIV_852x480p60hz, - HDMIV_854x480p60hz, - HDMIV_1024x600p60hz, - HDMIV_1024x768p60hz, - HDMIV_1152x864p75hz, - HDMIV_1280x600p60hz, - HDMIV_1280x768p60hz, - HDMIV_1280x800p60hz, - HDMIV_1280x960p60hz, - HDMIV_1280x1024p60hz, - HDMIV_1360x768p60hz, - HDMIV_1366x768p60hz, - HDMIV_1400x1050p60hz, - HDMIV_1440x900p60hz, - HDMIV_1440x2560p60hz, - HDMIV_1600x900p60hz, - HDMIV_1600x1200p60hz, - HDMIV_1680x1050p60hz, - HDMIV_1920x1200p60hz, - HDMIV_2048x1080p24hz, - HDMIV_2160x1200p90hz, - HDMIV_2560x1080p60hz, - HDMIV_2560x1440p60hz, - HDMIV_2560x1600p60hz, - HDMIV_3440x1440p60hz, - HDMIV_2400x1200p90hz, - HDMIV_3840x1080p60hz, - HDMI_VIC_END, -}; +/*keep for hw verification*/ +#define HDMI_3840x1080p120hz HDMI_109_1280x720p48_64x27 +#define HDMI_3840x1080p100hz HDMI_110_1680x720p48_64x27 +#define HDMI_3840x540p240hz HDMI_111_1920x1080p48_16x9 +#define HDMI_3840x540p200hz HDMI_112_1920x1080p48_64x27 /* Compliance with old definitions */ #define HDMI_640x480p60 HDMI_640x480p60_4x3 @@ -221,7 +154,6 @@ enum hdmi_vic { #define HDMI_480i60_16x9 HDMI_720x480i60_16x9 #define HDMI_480i60_16x9_rpt HDMI_2880x480i60_16x9 #define HDMI_1440x480p60 HDMI_1440x480p60_4x3 -#define HDMI_1440x480p60_16x9 HDMI_1440x480p60_16x9 #define HDMI_1080p60 HDMI_1920x1080p60_16x9 #define HDMI_576p50 HDMI_720x576p50_4x3 #define HDMI_576p50_16x9 HDMI_720x576p50_16x9 @@ -265,29 +197,7 @@ enum hdmi_phy_para { enum hdmi_audio_fs; struct dtd; -/* CEA TIMING STRUCT DEFINITION */ -struct hdmi_cea_timing { - unsigned int pixel_freq; /* Unit: 1000 */ - unsigned int frac_freq; /* 1.001 shift */ - unsigned int h_freq; /* Unit: Hz */ - unsigned int v_freq; /* Unit: 0.001 Hz */ - unsigned int vsync; /* Unit: Hz, rough data */ - unsigned int vsync_polarity:1; - unsigned int hsync_polarity:1; - unsigned short h_active; - unsigned short h_total; - unsigned short h_blank; - unsigned short h_front; - unsigned short h_sync; - unsigned short h_back; - unsigned short v_active; - unsigned short v_total; - unsigned short v_blank; - unsigned short v_front; - unsigned short v_sync; - unsigned short v_back; - unsigned short v_sync_ln; -}; +#define hdmi_cea_timing hdmi_timing enum hdmi_hdr_status { HDR10PLUS_VSIF = 0, @@ -316,23 +226,6 @@ enum hdmi_3d_type { /* t: struct hdmi_cea_timing * */ #define GET_TIMING(name) (t->(name)) -struct hdmi_format_para { - enum hdmi_vic vic; - unsigned char *name; - unsigned char *sname; - char ext_name[32]; - enum hdmi_color_depth cd; /* cd8, cd10 or cd12 */ - enum hdmi_colorspace cs; /* rgb, y444, y422, y420 */ - enum hdmi_quantization_range cr; /* limit, full */ - unsigned int pixel_repetition_factor; - unsigned int progress_mode:1; - unsigned int scrambler_en:1; - unsigned int tmds_clk_div40:1; - unsigned int tmds_clk; /* Unit: 1000 */ - struct hdmi_cea_timing timing; - struct vinfo_s hdmitx_vinfo; -}; - /* HDMI Packet Type Definitions */ #define PT_NULL_PKT 0x00 #define PT_AUD_CLK_REGENERATION 0x01 @@ -388,7 +281,7 @@ enum hdmi_aspect_ratio { struct vesa_standard_timing; -struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic); +const struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic); struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t); void check_detail_fmt(void); unsigned int hdmi_get_csc_coef(unsigned int input_format, @@ -397,7 +290,7 @@ unsigned int hdmi_get_csc_coef(unsigned int input_format, unsigned int color_format, const unsigned char **coef_array, unsigned int *coef_length); -struct hdmi_format_para *hdmi_get_fmt_name(char const *name, char const *attr); +const struct hdmi_format_para *hdmi_get_fmt_name(char const *name, char const *attr); struct hdmi_format_para *hdmi_tst_fmt_name(char const *name, char const *attr); struct vinfo_s *hdmi_get_valid_vinfo(char *mode); const char *hdmi_get_str_cd(struct hdmi_format_para *para); @@ -525,21 +418,6 @@ struct hdmi_audio_fs_ncts { unsigned int def_n; }; -struct parse_cd { - enum hdmi_color_depth cd; - const char *name; -}; - -struct parse_cs { - enum hdmi_colorspace cs; - const char *name; -}; - -struct parse_cr { - enum hdmi_quantization_range cr; - const char *name; -}; - struct vesa_standard_timing { unsigned short hactive; unsigned short vactive; diff --git a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h index 7a7d20ba2..989fabac6 100644 --- a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h +++ b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h @@ -367,7 +367,6 @@ struct hdmitx_dev { /* For some un-well-known TVs, no edid at all */ unsigned int tv_no_edid; unsigned int hpd_lock; - struct hdmi_format_para *para; /* 0: RGB444 1: Y444 2: Y422 3: Y420 */ /* 4: 24bit 5: 30bit 6: 36bit 7: 48bit */ /* if equals to 1, means current video & audio output are blank */ diff --git a/include/linux/amlogic/media/vout/hdmi_tx21/hdmi_common.h b/include/linux/amlogic/media/vout/hdmi_tx21/hdmi_common.h index c2d655170..8237c9594 100644 --- a/include/linux/amlogic/media/vout/hdmi_tx21/hdmi_common.h +++ b/include/linux/amlogic/media/vout/hdmi_tx21/hdmi_common.h @@ -10,15 +10,8 @@ #include #include #include - -/* HDMI VIC definitions */ - -/* HDMITX_VIC_MASK are associated with - * VIC_MAX_VALID_MODE and VIC_MAX_NUM in hdmi_tx_module.h - */ -#define HDMITX_VESA_OFFSET 0x300 - -#define HDMITX_VIC_MASK 0xff +#include +#include #define HDMI_PACKET_TYPE_GCP 0x3 @@ -32,48 +25,11 @@ enum hdmi_hdr_status { SDR, }; -/* CEA TIMING STRUCT DEFINITION */ -struct hdmi_timing { - unsigned int vic; - unsigned char *name; - unsigned char *sname; - unsigned short pi_mode; /* 1: progressive 0: interlaced */ - unsigned int h_freq; /* in Hz */ - unsigned int v_freq; /* in 0.001 Hz */ - unsigned int pixel_freq; /* Unit: 1000 */ - unsigned short h_total; - unsigned short h_blank; - unsigned short h_front; - unsigned short h_sync; - unsigned short h_back; - unsigned short h_active; - unsigned short v_total; - unsigned short v_blank; - unsigned short v_front; - unsigned short v_sync; - unsigned short v_back; - unsigned short v_active; - unsigned short v_sync_ln; - - unsigned short h_pol; - unsigned short v_pol; - unsigned short h_pict; - unsigned short v_pict; - unsigned short h_pixel; - unsigned short v_pixel; - unsigned int pixel_repetition_factor; -}; - u32 calc_frl_bandwidth(u32 pixel_freq, enum hdmi_colorspace cs, enum hdmi_color_depth cd); u32 calc_tmds_bandwidth(u32 pixel_freq, enum hdmi_colorspace cs, enum hdmi_color_depth cd); -struct parse_cd { - enum hdmi_color_depth cd; - const char *name; -}; - enum hdmi_tf_type { HDMI_NONE = 0, /* HDMI_HDR_TYPE, HDMI_DV_TYPE, and HDMI_HDR10P_TYPE @@ -91,213 +47,6 @@ enum hdmi_tf_type { HDMI_HDR10P_DV_VSIF = HDMI_HDR10P_TYPE | 1, }; -enum hdmi_vic { - /* Refer to CEA 861-D */ - HDMI_0_UNKNOWN = 0, - HDMI_1_640x480p60_4x3 = 1, - HDMI_2_720x480p60_4x3 = 2, - HDMI_3_720x480p60_16x9 = 3, - HDMI_4_1280x720p60_16x9 = 4, - HDMI_5_1920x1080i60_16x9 = 5, - HDMI_6_720x480i60_4x3 = 6, - HDMI_7_720x480i60_16x9 = 7, - HDMI_8_720x240p60_4x3 = 8, - HDMI_9_720x240p60_16x9 = 9, - HDMI_10_2880x480i60_4x3 = 10, - HDMI_11_2880x480i60_16x9 = 11, - HDMI_12_2880x240p60_4x3 = 12, - HDMI_13_2880x240p60_16x9 = 13, - HDMI_14_1440x480p60_4x3 = 14, - HDMI_15_1440x480p60_16x9 = 15, - HDMI_16_1920x1080p60_16x9 = 16, - HDMI_17_720x576p50_4x3 = 17, - HDMI_18_720x576p50_16x9 = 18, - HDMI_19_1280x720p50_16x9 = 19, - HDMI_20_1920x1080i50_16x9 = 20, - HDMI_21_720x576i50_4x3 = 21, - HDMI_22_720x576i50_16x9 = 22, - HDMI_23_720x288p_4x3 = 23, - HDMI_24_720x288p_16x9 = 24, - HDMI_25_2880x576i50_4x3 = 25, - HDMI_26_2880x576i50_16x9 = 26, - HDMI_27_2880x288p50_4x3 = 27, - HDMI_28_2880x288p50_16x9 = 28, - HDMI_29_1440x576p_4x3 = 29, - HDMI_30_1440x576p_16x9 = 30, - HDMI_31_1920x1080p50_16x9 = 31, - HDMI_32_1920x1080p24_16x9 = 32, - HDMI_33_1920x1080p25_16x9 = 33, - HDMI_34_1920x1080p30_16x9 = 34, - HDMI_35_2880x480p60_4x3 = 35, - HDMI_36_2880x480p60_16x9 = 36, - HDMI_37_2880x576p50_4x3 = 37, - HDMI_38_2880x576p50_16x9 = 38, - HDMI_39_1920x1080i_t1250_50_16x9 = 39, - HDMI_40_1920x1080i100_16x9 = 40, - HDMI_41_1280x720p100_16x9 = 41, - HDMI_42_720x576p100_4x3 = 42, - HDMI_43_720x576p100_16x9 = 43, - HDMI_44_720x576i100_4x3 = 44, - HDMI_45_720x576i100_16x9 = 45, - HDMI_46_1920x1080i120_16x9 = 46, - HDMI_47_1280x720p120_16x9 = 47, - HDMI_48_720x480p120_4x3 = 48, - HDMI_49_720x480p120_16x9 = 49, - HDMI_50_720x480i120_4x3 = 50, - HDMI_51_720x480i120_16x9 = 51, - HDMI_52_720x576p200_4x3 = 52, - HDMI_53_720x576p200_16x9 = 53, - HDMI_54_720x576i200_4x3 = 54, - HDMI_55_720x576i200_16x9 = 55, - HDMI_56_720x480p240_4x3 = 56, - HDMI_57_720x480p240_16x9 = 57, - HDMI_58_720x480i240_4x3 = 58, - HDMI_59_720x480i240_16x9 = 59, - HDMI_60_1280x720p24_16x9 = 60, - HDMI_61_1280x720p25_16x9 = 61, - HDMI_62_1280x720p30_16x9 = 62, - HDMI_63_1920x1080p120_16x9 = 63, - HDMI_64_1920x1080p100_16x9 = 64, - HDMI_65_1280x720p24_64x27 = 65, - HDMI_66_1280x720p25_64x27 = 66, - HDMI_67_1280x720p30_64x27 = 67, - HDMI_68_1280x720p50_64x27 = 68, - HDMI_69_1280x720p60_64x27 = 69, - HDMI_70_1280x720p100_64x27 = 70, - HDMI_71_1280x720p120_64x27 = 71, - HDMI_72_1920x1080p24_64x27 = 72, - HDMI_73_1920x1080p25_64x27 = 73, - HDMI_74_1920x1080p30_64x27 = 74, - HDMI_75_1920x1080p50_64x27 = 75, - HDMI_76_1920x1080p60_64x27 = 76, - HDMI_77_1920x1080p100_64x27 = 77, - HDMI_78_1920x1080p120_64x27 = 78, - HDMI_79_1680x720p24_64x27 = 79, - HDMI_80_1680x720p25_64x27 = 80, - HDMI_81_1680x720p30_64x27 = 81, - HDMI_82_1680x720p50_64x27 = 82, - HDMI_83_1680x720p60_64x27 = 83, - HDMI_84_1680x720p100_64x27 = 84, - HDMI_85_1680x720p120_64x27 = 85, - HDMI_86_2560x1080p24_64x27 = 86, - HDMI_87_2560x1080p25_64x27 = 87, - HDMI_88_2560x1080p30_64x27 = 88, - HDMI_89_2560x1080p50_64x27 = 89, - HDMI_90_2560x1080p60_64x27 = 90, - HDMI_91_2560x1080p100_64x27 = 91, - HDMI_92_2560x1080p120_64x27 = 92, - HDMI_93_3840x2160p24_16x9 = 93, - HDMI_94_3840x2160p25_16x9 = 94, - HDMI_95_3840x2160p30_16x9 = 95, - HDMI_96_3840x2160p50_16x9 = 96, - HDMI_97_3840x2160p60_16x9 = 97, - HDMI_98_4096x2160p24_256x135 = 98, - HDMI_99_4096x2160p25_256x135 = 99, - HDMI_100_4096x2160p30_256x135 = 100, - HDMI_101_4096x2160p50_256x135 = 101, - HDMI_102_4096x2160p60_256x135 = 102, - HDMI_103_3840x2160p24_64x27 = 103, - HDMI_104_3840x2160p25_64x27 = 104, - HDMI_105_3840x2160p30_64x27 = 105, - HDMI_106_3840x2160p50_64x27 = 106, - HDMI_107_3840x2160p60_64x27 = 107, - HDMI_108_1280x720p48_16x9 = 108, - HDMI_109_1280x720p48_64x27 = 109, - HDMI_110_1680x720p48_64x27 = 110, - HDMI_111_1920x1080p48_16x9 = 111, - HDMI_112_1920x1080p48_64x27 = 112, - HDMI_113_2560x1080p48_64x27 = 113, - HDMI_114_3840x2160p48_16x9 = 114, - HDMI_115_4096x2160p48_256x135 = 115, - HDMI_116_3840x2160p48_64x27 = 116, - HDMI_117_3840x2160p100_16x9 = 117, - HDMI_118_3840x2160p120_16x9 = 118, - HDMI_119_3840x2160p100_64x27 = 119, - HDMI_120_3840x2160p120_64x27 = 120, - HDMI_121_5120x2160p24_64x27 = 121, - HDMI_122_5120x2160p25_64x27 = 122, - HDMI_123_5120x2160p30_64x27 = 123, - HDMI_124_5120x2160p48_64x27 = 124, - HDMI_125_5120x2160p50_64x27 = 125, - HDMI_126_5120x2160p60_64x27 = 126, - HDMI_127_5120x2160p100_64x27 = 127, - /* 127 ~ 192 reserved */ - HDMI_193_5120x2160p120_64x27 = 193, - HDMI_194_7680x4320p24_16x9 = 194, - HDMI_195_7680x4320p25_16x9 = 195, - HDMI_196_7680x4320p30_16x9 = 196, - HDMI_197_7680x4320p48_16x9 = 197, - HDMI_198_7680x4320p50_16x9 = 198, - HDMI_199_7680x4320p60_16x9 = 199, - HDMI_200_7680x4320p100_16x9 = 200, - HDMI_201_7680x4320p120_16x9 = 201, - HDMI_202_7680x4320p24_64x27 = 202, - HDMI_203_7680x4320p25_64x27 = 203, - HDMI_204_7680x4320p30_64x27 = 204, - HDMI_205_7680x4320p48_64x27 = 205, - HDMI_206_7680x4320p50_64x27 = 206, - HDMI_207_7680x4320p60_64x27 = 207, - HDMI_208_7680x4320p100_64x27 = 208, - HDMI_209_7680x4320p120_64x27 = 209, - HDMI_210_10240x4320p24_64x27 = 210, - HDMI_211_10240x4320p25_64x27 = 211, - HDMI_212_10240x4320p30_64x27 = 212, - HDMI_213_10240x4320p48_64x27 = 213, - HDMI_214_10240x4320p50_64x27 = 214, - HDMI_215_10240x4320p60_64x27 = 215, - HDMI_216_10240x4320p100_64x27 = 216, - HDMI_217_10240x4320p120_64x27 = 217, - HDMI_218_4096x2160p100_256x135 = 218, - HDMI_219_4096x2160p120_256x135 = 219, - HDMIV_640x480p60hz = HDMITX_VESA_OFFSET, - HDMIV_800x480p60hz, - HDMIV_800x600p60hz, - HDMIV_852x480p60hz, - HDMIV_854x480p60hz, - HDMIV_1024x600p60hz, - HDMIV_1024x768p60hz, - HDMIV_1152x864p75hz, - HDMIV_1280x600p60hz, - HDMIV_1280x768p60hz, - HDMIV_1280x800p60hz, - HDMIV_1280x960p60hz, - HDMIV_1280x1024p60hz, - HDMIV_1360x768p60hz, - HDMIV_1366x768p60hz, - HDMIV_1400x1050p60hz, - HDMIV_1440x900p60hz, - HDMIV_1440x2560p60hz, - HDMIV_1600x900p60hz, - HDMIV_1600x1200p60hz, - HDMIV_1680x1050p60hz, - HDMIV_1920x1200p60hz, - HDMIV_2160x1200p90hz, - HDMIV_2560x1080p60hz, - HDMIV_2560x1440p60hz, - HDMIV_2560x1600p60hz, - HDMIV_3440x1440p60hz, - HDMIV_2400x1200p90hz, - HDMI_VIC_FAKE, - HDMI_VIC_END, -}; - -struct hdmi_format_para { - enum hdmi_vic vic; - unsigned char *name; - unsigned char *sname; - char ext_name[32]; - enum hdmi_color_depth cd; /* cd8, cd10 or cd12 */ - enum hdmi_colorspace cs; /* 0/1/2/3: rgb/422/444/420 */ - enum hdmi_quantization_range cr; /* limit, full */ - unsigned int pixel_repetition_factor; - unsigned int progress_mode:1; - u32 scrambler_en:1; - u32 tmds_clk_div40:1; - u32 tmds_clk; /* Unit: 1000 */ - struct hdmi_timing timing; - struct vinfo_s hdmitx_vinfo; -}; - enum hdmi_phy_para { HDMI_PHYPARA_6G = 1, /* 2160p60hz 444 8bit */ HDMI_PHYPARA_4p5G, /* 2160p50hz 420 12bit */ @@ -362,8 +111,7 @@ struct hdmi_format_para *hdmitx21_tst_fmt_name(const char *name, const char *attr); const struct hdmi_timing *hdmitx21_gettiming_from_vic(enum hdmi_vic vic); const struct hdmi_timing *hdmitx21_gettiming_from_name(const char *name); -struct hdmi_format_para *hdmitx21_get_fmtpara(const char *mode, - const char *attr); +int hdmitx21_get_fmtpara(const char *mode, const char *attr, struct hdmi_format_para *para); u32 hdmi21_get_aud_n_paras(enum hdmi_audio_fs fs, enum hdmi_color_depth cd, u32 tmds_clk); @@ -487,16 +235,6 @@ struct hdmi_audio_fs_ncts { u32 def_n; }; -struct parse_cs { - enum hdmi_colorspace cs; - const char *name; -}; - -struct parse_cr { - enum hdmi_quantization_range cr; - const char *name; -}; - struct vesa_standard_timing { unsigned short hactive; unsigned short vactive; diff --git a/include/linux/amlogic/media/vout/hdmi_tx21/hdmi_tx_module.h b/include/linux/amlogic/media/vout/hdmi_tx21/hdmi_tx_module.h index 85805e8e8..28d926e7f 100644 --- a/include/linux/amlogic/media/vout/hdmi_tx21/hdmi_tx_module.h +++ b/include/linux/amlogic/media/vout/hdmi_tx21/hdmi_tx_module.h @@ -187,7 +187,6 @@ struct hdmitx_dev { struct workqueue_struct *cedst_wq; struct device *hdtx_dev; struct device *pdev; /* for pinctrl*/ - struct hdmi_format_para *para; struct pinctrl_state *pinctrl_i2c; struct pinctrl_state *pinctrl_default; struct amhdmitx_data_s *data; diff --git a/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_common.h b/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_common.h index ca3cf6202..936abd665 100644 --- a/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_common.h +++ b/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_common.h @@ -12,27 +12,10 @@ #include #include +#include #define HDMI_INFOFRAME_TYPE_VENDOR2 (0x81 | 0x100) -enum hdmi_color_depth { - COLORDEPTH_24B = 4, - COLORDEPTH_30B = 5, - COLORDEPTH_36B = 6, - COLORDEPTH_48B = 7, - COLORDEPTH_RESERVED, -}; - -struct hdmi_format_para_new { - enum hdmi_color_depth cd; /* cd8, cd10 or cd12 */ - enum hdmi_colorspace cs; /* 0/1/2/3: rgb/422/444/420 */ - enum hdmi_quantization_range cr; /* limit, full */ - - u32 scrambler_en:1; - u32 tmds_clk_div40:1; - u32 tmds_clk; /* Unit: 1000 */ -}; - struct hdmitx_common { /* When hdr_priority is 1, then dv_info will be all 0; * when hdr_priority is 2, then dv_info/hdr_info will be all 0 @@ -51,6 +34,8 @@ struct hdmitx_common { /*current mode vic.*/ u32 cur_VIC; + /*current format para.*/ + struct hdmi_format_para fmt_para; /* allm_mode: 1/on 0/off */ u32 allm_mode; diff --git a/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_dev_common.h b/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_dev_common.h index 8adffcbce..7348e9ce4 100644 --- a/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_dev_common.h +++ b/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_dev_common.h @@ -8,6 +8,7 @@ #include #include +#include /************************************************************************************ * hdmitx_dev_common only define api which will use hdmitx_common&hdmitx_hw_common. diff --git a/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_edid.h b/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_edid.h index 4d4ad614e..c18078838 100644 --- a/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_edid.h +++ b/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_edid.h @@ -7,22 +7,13 @@ #include #include +#include #define EDID_MAX_BLOCK 8 #define VESA_MAX_TIMING 64 #define AUD_MAX_NUM 60 #define MAX_RAW_LEN 64 -/* VIC_MAX_VALID_MODE and VIC_MAX_NUM are associated with - * HDMITX_VIC_MASK in hdmi_common.h - */ -#define VIC_MAX_VALID_MODE 256 /* consider 4k2k */ -/* half for valid vic, half for vic with y420*/ -#define VIC_MAX_NUM 512 - -#define VESA_MAX_TIMING 64 -#define Y420_VIC_MAX_NUM 6 /* only 6 4k mode for y420 */ - enum frl_rate_enum { FRL_NONE = 0, FRL_3G3L = 1, diff --git a/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_hw_common.h b/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_hw_common.h index 4d2b7b9bd..a36c141f8 100644 --- a/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_hw_common.h +++ b/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_hw_common.h @@ -7,6 +7,7 @@ #define __HDMITX_HW_COMMON_H #include +#include /*hw cntl cmd define, abstract from hdmi_tx_module.h*/ #define CMD_DDC_OFFSET (0x10 << 24) @@ -70,7 +71,6 @@ #define STAT_AUDIO_CLK_STABLE (CMD_STAT_OFFSET + 0x12) #define STAT_AUDIO_PACK (CMD_STAT_OFFSET + 0x13) #define STAT_HDR_TYPE (CMD_STAT_OFFSET + 0x20) - #define STAT_TX_PHY (CMD_STAT_OFFSET + 0x30) /*********************************************************************** diff --git a/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_mode.h b/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_mode.h new file mode 100644 index 000000000..c637cc168 --- /dev/null +++ b/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_mode.h @@ -0,0 +1,342 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __HDMITX_MODE_H_ +#define __HDMITX_MODE_H_ + +#include +#include + +/* half for valid vic, half for vic with y420*/ +#define VIC_MAX_NUM 512 + +#define VESA_MAX_TIMING 64 +#define Y420_VIC_MAX_NUM 6 /* only 6 4k mode for y420 */ + +/* HDMITX_VIC_MASK are associated with + * VIC_MAX_VALID_MODE and VIC_MAX_NUM in hdmi_tx_module.h + */ +#define HDMITX_VESA_OFFSET 0x300 + +/* HDMITX_VIC420_OFFSET and HDMITX_VIC_MASK are associated with + * VIC_MAX_VALID_MODE and VIC_MAX_NUM in hdmi_tx_module.h + */ +#define HDMITX_VIC_MASK 0xff + +enum hdmi_vic { + /* Refer to CEA 861-D */ + HDMI_0_UNKNOWN = 0, + HDMI_1_640x480p60_4x3 = 1, + HDMI_2_720x480p60_4x3 = 2, + HDMI_3_720x480p60_16x9 = 3, + HDMI_4_1280x720p60_16x9 = 4, + HDMI_5_1920x1080i60_16x9 = 5, + HDMI_6_720x480i60_4x3 = 6, + HDMI_7_720x480i60_16x9 = 7, + HDMI_8_720x240p60_4x3 = 8, + HDMI_9_720x240p60_16x9 = 9, + HDMI_10_2880x480i60_4x3 = 10, + HDMI_11_2880x480i60_16x9 = 11, + HDMI_12_2880x240p60_4x3 = 12, + HDMI_13_2880x240p60_16x9 = 13, + HDMI_14_1440x480p60_4x3 = 14, + HDMI_15_1440x480p60_16x9 = 15, + HDMI_16_1920x1080p60_16x9 = 16, + HDMI_17_720x576p50_4x3 = 17, + HDMI_18_720x576p50_16x9 = 18, + HDMI_19_1280x720p50_16x9 = 19, + HDMI_20_1920x1080i50_16x9 = 20, + HDMI_21_720x576i50_4x3 = 21, + HDMI_22_720x576i50_16x9 = 22, + HDMI_23_720x288p_4x3 = 23, + HDMI_24_720x288p_16x9 = 24, + HDMI_25_2880x576i50_4x3 = 25, + HDMI_26_2880x576i50_16x9 = 26, + HDMI_27_2880x288p50_4x3 = 27, + HDMI_28_2880x288p50_16x9 = 28, + HDMI_29_1440x576p_4x3 = 29, + HDMI_30_1440x576p_16x9 = 30, + HDMI_31_1920x1080p50_16x9 = 31, + HDMI_32_1920x1080p24_16x9 = 32, + HDMI_33_1920x1080p25_16x9 = 33, + HDMI_34_1920x1080p30_16x9 = 34, + HDMI_35_2880x480p60_4x3 = 35, + HDMI_36_2880x480p60_16x9 = 36, + HDMI_37_2880x576p50_4x3 = 37, + HDMI_38_2880x576p50_16x9 = 38, + HDMI_39_1920x1080i_t1250_50_16x9 = 39, + HDMI_40_1920x1080i100_16x9 = 40, + HDMI_41_1280x720p100_16x9 = 41, + HDMI_42_720x576p100_4x3 = 42, + HDMI_43_720x576p100_16x9 = 43, + HDMI_44_720x576i100_4x3 = 44, + HDMI_45_720x576i100_16x9 = 45, + HDMI_46_1920x1080i120_16x9 = 46, + HDMI_47_1280x720p120_16x9 = 47, + HDMI_48_720x480p120_4x3 = 48, + HDMI_49_720x480p120_16x9 = 49, + HDMI_50_720x480i120_4x3 = 50, + HDMI_51_720x480i120_16x9 = 51, + HDMI_52_720x576p200_4x3 = 52, + HDMI_53_720x576p200_16x9 = 53, + HDMI_54_720x576i200_4x3 = 54, + HDMI_55_720x576i200_16x9 = 55, + HDMI_56_720x480p240_4x3 = 56, + HDMI_57_720x480p240_16x9 = 57, + HDMI_58_720x480i240_4x3 = 58, + HDMI_59_720x480i240_16x9 = 59, + HDMI_60_1280x720p24_16x9 = 60, + HDMI_61_1280x720p25_16x9 = 61, + HDMI_62_1280x720p30_16x9 = 62, + HDMI_63_1920x1080p120_16x9 = 63, + HDMI_64_1920x1080p100_16x9 = 64, + HDMI_65_1280x720p24_64x27 = 65, + HDMI_66_1280x720p25_64x27 = 66, + HDMI_67_1280x720p30_64x27 = 67, + HDMI_68_1280x720p50_64x27 = 68, + HDMI_69_1280x720p60_64x27 = 69, + HDMI_70_1280x720p100_64x27 = 70, + HDMI_71_1280x720p120_64x27 = 71, + HDMI_72_1920x1080p24_64x27 = 72, + HDMI_73_1920x1080p25_64x27 = 73, + HDMI_74_1920x1080p30_64x27 = 74, + HDMI_75_1920x1080p50_64x27 = 75, + HDMI_76_1920x1080p60_64x27 = 76, + HDMI_77_1920x1080p100_64x27 = 77, + HDMI_78_1920x1080p120_64x27 = 78, + HDMI_79_1680x720p24_64x27 = 79, + HDMI_80_1680x720p25_64x27 = 80, + HDMI_81_1680x720p30_64x27 = 81, + HDMI_82_1680x720p50_64x27 = 82, + HDMI_83_1680x720p60_64x27 = 83, + HDMI_84_1680x720p100_64x27 = 84, + HDMI_85_1680x720p120_64x27 = 85, + HDMI_86_2560x1080p24_64x27 = 86, + HDMI_87_2560x1080p25_64x27 = 87, + HDMI_88_2560x1080p30_64x27 = 88, + HDMI_89_2560x1080p50_64x27 = 89, + HDMI_90_2560x1080p60_64x27 = 90, + HDMI_91_2560x1080p100_64x27 = 91, + HDMI_92_2560x1080p120_64x27 = 92, + HDMI_93_3840x2160p24_16x9 = 93, + HDMI_94_3840x2160p25_16x9 = 94, + HDMI_95_3840x2160p30_16x9 = 95, + HDMI_96_3840x2160p50_16x9 = 96, + HDMI_97_3840x2160p60_16x9 = 97, + HDMI_98_4096x2160p24_256x135 = 98, + HDMI_99_4096x2160p25_256x135 = 99, + HDMI_100_4096x2160p30_256x135 = 100, + HDMI_101_4096x2160p50_256x135 = 101, + HDMI_102_4096x2160p60_256x135 = 102, + HDMI_103_3840x2160p24_64x27 = 103, + HDMI_104_3840x2160p25_64x27 = 104, + HDMI_105_3840x2160p30_64x27 = 105, + HDMI_106_3840x2160p50_64x27 = 106, + HDMI_107_3840x2160p60_64x27 = 107, + HDMI_108_1280x720p48_16x9 = 108, + HDMI_109_1280x720p48_64x27 = 109, + HDMI_110_1680x720p48_64x27 = 110, + HDMI_111_1920x1080p48_16x9 = 111, + HDMI_112_1920x1080p48_64x27 = 112, + HDMI_113_2560x1080p48_64x27 = 113, + HDMI_114_3840x2160p48_16x9 = 114, + HDMI_115_4096x2160p48_256x135 = 115, + HDMI_116_3840x2160p48_64x27 = 116, + HDMI_117_3840x2160p100_16x9 = 117, + HDMI_118_3840x2160p120_16x9 = 118, + HDMI_119_3840x2160p100_64x27 = 119, + HDMI_120_3840x2160p120_64x27 = 120, + HDMI_121_5120x2160p24_64x27 = 121, + HDMI_122_5120x2160p25_64x27 = 122, + HDMI_123_5120x2160p30_64x27 = 123, + HDMI_124_5120x2160p48_64x27 = 124, + HDMI_125_5120x2160p50_64x27 = 125, + HDMI_126_5120x2160p60_64x27 = 126, + HDMI_127_5120x2160p100_64x27 = 127, + /* 128 ~ 192 reserved */ + HDMI_193_5120x2160p120_64x27 = 193, + HDMI_194_7680x4320p24_16x9 = 194, + HDMI_195_7680x4320p25_16x9 = 195, + HDMI_196_7680x4320p30_16x9 = 196, + HDMI_197_7680x4320p48_16x9 = 197, + HDMI_198_7680x4320p50_16x9 = 198, + HDMI_199_7680x4320p60_16x9 = 199, + HDMI_200_7680x4320p100_16x9 = 200, + HDMI_201_7680x4320p120_16x9 = 201, + HDMI_202_7680x4320p24_64x27 = 202, + HDMI_203_7680x4320p25_64x27 = 203, + HDMI_204_7680x4320p30_64x27 = 204, + HDMI_205_7680x4320p48_64x27 = 205, + HDMI_206_7680x4320p50_64x27 = 206, + HDMI_207_7680x4320p60_64x27 = 207, + HDMI_208_7680x4320p100_64x27 = 208, + HDMI_209_7680x4320p120_64x27 = 209, + HDMI_210_10240x4320p24_64x27 = 210, + HDMI_211_10240x4320p25_64x27 = 211, + HDMI_212_10240x4320p30_64x27 = 212, + HDMI_213_10240x4320p48_64x27 = 213, + HDMI_214_10240x4320p50_64x27 = 214, + HDMI_215_10240x4320p60_64x27 = 215, + HDMI_216_10240x4320p100_64x27 = 216, + HDMI_217_10240x4320p120_64x27 = 217, + HDMI_218_4096x2160p100_256x135 = 218, + HDMI_219_4096x2160p120_256x135 = 219, + HDMI_CEA_VIC_END, + + /* !!!DONT USE IT ANYMORE, WILL REMOVE LATER. + * start from 0x200, the following vic is for those y420 mode + * and they has same vic with normal vic in the lower bytes. + */ + HDMITX_VIC420_OFFSET = 0x100, + HDMI_3840x2160p50_16x9_Y420 = + HDMITX_VIC420_OFFSET + HDMI_96_3840x2160p50_16x9, + HDMI_3840x2160p60_16x9_Y420 = + HDMITX_VIC420_OFFSET + HDMI_97_3840x2160p60_16x9, + HDMI_4096x2160p50_256x135_Y420 = + HDMITX_VIC420_OFFSET + HDMI_101_4096x2160p50_256x135, + HDMI_4096x2160p60_256x135_Y420 = + HDMITX_VIC420_OFFSET + HDMI_102_4096x2160p60_256x135, + HDMI_3840x2160p50_64x27_Y420 = + HDMITX_VIC420_OFFSET + HDMI_106_3840x2160p50_64x27, + HDMI_3840x2160p60_64x27_Y420 = + HDMITX_VIC420_OFFSET + HDMI_107_3840x2160p60_64x27, + + /*FAKE VIC*/ + HDMI_VIC_FAKE = 0X200, + + /*Vesa mode which dont have vic, we specify value for them also*/ + HDMIV_0_640x480p60hz = HDMITX_VESA_OFFSET, + HDMIV_1_800x480p60hz, + HDMIV_2_800x600p60hz, + HDMIV_3_852x480p60hz, + HDMIV_4_854x480p60hz, + HDMIV_5_1024x600p60hz, + HDMIV_6_1024x768p60hz, + HDMIV_7_1152x864p75hz, + HDMIV_8_1280x768p60hz, + HDMIV_9_1280x800p60hz, + HDMIV_10_1280x960p60hz, + HDMIV_11_1280x1024p60hz, + HDMIV_12_1360x768p60hz, + HDMIV_13_1366x768p60hz, + HDMIV_14_1400x1050p60hz, + HDMIV_15_1440x900p60hz, + HDMIV_16_1440x2560p60hz, + HDMIV_17_1600x900p60hz, + HDMIV_18_1600x1200p60hz, + HDMIV_19_1680x1050p60hz, + HDMIV_20_1920x1200p60hz, + HDMIV_21_2048x1080p24hz, + HDMIV_22_2160x1200p90hz, + HDMIV_23_2560x1600p60hz, + HDMIV_24_3440x1440p60hz, + HDMIV_25_2400x1200p90hz, + HDMIV_26_3840x1080p60hz, + /*not supported in timing*/ + HDMIV_2560x1080p60hz, + HDMIV_2560x1440p60hz, + HDMIV_1280x600p60hz, + HDMIV_2560x1600p60hz, + HDMIV_3440x1440p60hz, + HDMIV_2400x1200p90hz, + + HDMI_VIC_END = 0xFFFF, +}; + +/* Compliance with old definitions */ +#define HDMIV_640x480p60hz HDMIV_0_640x480p60hz +#define HDMIV_800x480p60hz HDMIV_1_800x480p60hz +#define HDMIV_800x600p60hz HDMIV_2_800x600p60hz +#define HDMIV_852x480p60hz HDMIV_3_852x480p60hz +#define HDMIV_854x480p60hz HDMIV_4_854x480p60hz +#define HDMIV_1024x600p60hz HDMIV_5_1024x600p60hz +#define HDMIV_1024x768p60hz HDMIV_6_1024x768p60hz +#define HDMIV_1152x864p75hz HDMIV_7_1152x864p75hz +#define HDMIV_1280x768p60hz HDMIV_8_1280x768p60hz +#define HDMIV_1280x800p60hz HDMIV_9_1280x800p60hz +#define HDMIV_1280x960p60hz HDMIV_10_1280x960p60hz +#define HDMIV_1280x1024p60hz HDMIV_11_1280x1024p60hz +#define HDMIV_1360x768p60hz HDMIV_12_1360x768p60hz +#define HDMIV_1366x768p60hz HDMIV_13_1366x768p60hz +#define HDMIV_1400x1050p60hz HDMIV_14_1400x1050p60hz +#define HDMIV_1440x900p60hz HDMIV_15_1440x900p60hz +#define HDMIV_1440x2560p60hz HDMIV_16_1440x2560p60hz +#define HDMIV_1600x900p60hz HDMIV_17_1600x900p60hz +#define HDMIV_1600x1200p60hz HDMIV_18_1600x1200p60hz +#define HDMIV_1680x1050p60hz HDMIV_19_1680x1050p60hz +#define HDMIV_1920x1200p60hz HDMIV_20_1920x1200p60hz +#define HDMIV_2048x1080p24hz HDMIV_21_2048x1080p24hz +#define HDMIV_2160x1200p90hz HDMIV_22_2160x1200p90hz +#define HDMIV_2560x1600p60hz HDMIV_23_2560x1600p60hz +#define HDMIV_3440x1440p60hz HDMIV_24_3440x1440p60hz +#define HDMIV_2400x1200p90hz HDMIV_25_2400x1200p90hz +#define HDMIV_3840x1080p60hz HDMIV_26_3840x1080p60hz + +/* CEA TIMING STRUCT DEFINITION */ +struct hdmi_timing { + unsigned int vic; + unsigned char *name; + unsigned char *sname; + + unsigned short pi_mode; /* 1: progressive 0: interlaced */ + unsigned int h_freq; /* in Hz */ + unsigned int v_freq; /* in 0.001 Hz */ + unsigned int pixel_freq; /* Unit: 1000 */ + + unsigned short h_total; + unsigned short h_blank; + unsigned short h_front; + unsigned short h_sync; + unsigned short h_back; + unsigned short h_active; + unsigned short v_total; + unsigned short v_blank; + unsigned short v_front; + unsigned short v_sync; + unsigned short v_back; + unsigned short v_active; + unsigned short v_sync_ln; + + unsigned short h_pol; /*hsync_polarity*/ + unsigned short v_pol; /*vsync_polarity*/ + unsigned short h_pict; + unsigned short v_pict; + unsigned short h_pixel; + unsigned short v_pixel; + + /*Same as DRM_MODE_FLAG_DBLCLK, now only for 480i&576i*/ + u32 pixel_repetition_factor:1; + + /*hdmi_cea_timing for hdmitx20*/ + unsigned int frac_freq; /* 1.001 shift */ + unsigned int vsync; /* Unit: Hz, rough data */ + unsigned int vsync_polarity:1; + unsigned int hsync_polarity:1; +}; + +enum hdmi_color_depth { + COLORDEPTH_24B = 4, + COLORDEPTH_30B = 5, + COLORDEPTH_36B = 6, + COLORDEPTH_48B = 7, + COLORDEPTH_RESERVED, +}; + +struct parse_cd { + enum hdmi_color_depth cd; + const char *name; +}; + +struct parse_cs { + enum hdmi_colorspace cs; + const char *name; +}; + +struct parse_cr { + enum hdmi_quantization_range cr; + const char *name; +}; + +#endif diff --git a/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_types.h b/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_types.h new file mode 100644 index 000000000..3895885c7 --- /dev/null +++ b/include/linux/amlogic/media/vout/hdmitx_common/hdmitx_types.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __HDMITX_TYPES_H +#define __HDMITX_TYPES_H + +#include +#include +#include +#include + +struct hdmi_format_para { + enum hdmi_vic vic; + unsigned char *name; + unsigned char *sname; + char ext_name[32]; + + /*valid info*/ + enum hdmi_color_depth cd; /* cd8, cd10 or cd12 */ + enum hdmi_colorspace cs; /* 0/1/2/3: rgb/422/444/420 */ + enum hdmi_quantization_range cr; /* limit, full */ + /*valid info end*/ + + unsigned int pixel_repetition_factor; + unsigned int progress_mode:1; + + /*valid info*/ + u32 scrambler_en:1; + u32 tmds_clk_div40:1; + u32 tmds_clk; /* Unit: 1000 */ + /*valid info end*/ + + struct hdmi_timing timing; + struct vinfo_s hdmitx_vinfo; + + /*valid info*/ + u32 frac_mode; + /*valid info end*/ +}; + +#endif diff --git a/include/linux/amlogic/media/vout/vinfo.h b/include/linux/amlogic/media/vout/vinfo.h index f11a74b62..a81e6b201 100644 --- a/include/linux/amlogic/media/vout/vinfo.h +++ b/include/linux/amlogic/media/vout/vinfo.h @@ -6,6 +6,8 @@ #ifndef _VINFO_H_ #define _VINFO_H_ #include +#include +#include #include /* the MSB is represent vmode set by vmode_init */ @@ -416,6 +418,10 @@ struct vinfo_s { * the default value is 0 or 1. */ u8 cur_enc_ppc; + + /*dv need get the cd/cd of hdmitx.*/ + enum hdmi_color_depth cd; + enum hdmi_colorspace cs; }; #ifdef CONFIG_AMLOGIC_MEDIA_FB