diff --git a/drivers/media/common/rdma/rdma.c b/drivers/media/common/rdma/rdma.c index 736db86cf..90eb3bb9c 100644 --- a/drivers/media/common/rdma/rdma.c +++ b/drivers/media/common/rdma/rdma.c @@ -33,6 +33,7 @@ #ifdef CONFIG_AMLOGIC_MEDIA_VIDEO #include #endif +#include #define Wr(adr, val) WRITE_VCBUS_REG(adr, val) #define Rd(adr) READ_VCBUS_REG(adr) @@ -212,8 +213,12 @@ int _vsync_rdma_config(int rdma_type) iret = rdma_config(vsync_rdma_handle[rdma_type], RDMA_TRIGGER_VPP2_VSYNC_INPUT); } else if (rdma_type == PRE_VSYNC_RDMA) { - iret = rdma_config(vsync_rdma_handle[rdma_type], - RDMA_TRIGGER_PRE_VSYNC_INPUT); + if (is_meson_t3x_cpu()) + iret = rdma_config(vsync_rdma_handle[rdma_type], + RDMA_TRIGGER_PRE_VSYNC_INPUT_T3X); + else + iret = rdma_config(vsync_rdma_handle[rdma_type], + RDMA_TRIGGER_PRE_VSYNC_INPUT); } else if (rdma_type == EX_VSYNC_RDMA) { iret = rdma_config(vsync_rdma_handle[rdma_type], RDMA_TRIGGER_VSYNC_INPUT | @@ -449,8 +454,12 @@ static void pre_vsync_rdma_irq(void *arg) int enable_ = cur_enable[PRE_VSYNC_RDMA] & 0xf; if (enable_ == 1) { - iret = rdma_config(vsync_rdma_handle[PRE_VSYNC_RDMA], - RDMA_TRIGGER_PRE_VSYNC_INPUT); + if (is_meson_t3x_cpu()) + iret = rdma_config(vsync_rdma_handle[PRE_VSYNC_RDMA], + RDMA_TRIGGER_PRE_VSYNC_INPUT_T3X); + else + iret = rdma_config(vsync_rdma_handle[PRE_VSYNC_RDMA], + RDMA_TRIGGER_PRE_VSYNC_INPUT); if (iret) vsync_cfg_count[PRE_VSYNC_RDMA]++; } else { diff --git a/drivers/media/video_sink/video.c b/drivers/media/video_sink/video.c index e30c3ff85..e583042b2 100644 --- a/drivers/media/video_sink/video.c +++ b/drivers/media/video_sink/video.c @@ -3720,7 +3720,7 @@ struct vframe_s *amvideo_toggle_frame(s32 *vd_path_id) struct vframe_s *cur_dispbuf_back = cur_dispbuf[0]; int toggle_cnt; bool show_nosync = false; - struct cur_line_info_t *cur_line_info = get_cur_line_info(); + struct cur_line_info_t *cur_line_info = get_cur_line_info(0); toggle_cnt = 0; @@ -12449,10 +12449,7 @@ static ssize_t pre_vsync_enable_store(struct class *cla, pr_err("kstrtoint err\n"); return -EINVAL; } - if (cur_dev->prevsync_support) { - cur_dev->pre_vsync_enable = res; - vd1_set_go_field(); - } + set_pre_vsync_mode(res); return count; } diff --git a/drivers/media/video_sink/video_cut.c b/drivers/media/video_sink/video_cut.c index 2b74cd77e..4bad1ce9e 100644 --- a/drivers/media/video_sink/video_cut.c +++ b/drivers/media/video_sink/video_cut.c @@ -2319,7 +2319,7 @@ struct vframe_s *amvideo_toggle_frame(s32 *vd_path_id) struct vframe_s *vf; struct vframe_s *cur_dispbuf_back = cur_dispbuf[0]; int toggle_cnt; - struct cur_line_info_t *cur_line_info = get_cur_line_info(); + struct cur_line_info_t *cur_line_info = get_cur_line_info(0); toggle_cnt = 0; diff --git a/drivers/media/video_sink/video_func.c b/drivers/media/video_sink/video_func.c index f27bb2149..51bba05c2 100644 --- a/drivers/media/video_sink/video_func.c +++ b/drivers/media/video_sink/video_func.c @@ -70,6 +70,7 @@ #endif #include #include "video_common.h" +#include "video_hw.h" #include "video_hw_s5.h" #include "vpp_post_s5.h" #include "video_receiver.h" @@ -117,7 +118,7 @@ struct vd_func_s vd_fake_func[MAX_VIDEO_FAKE]; #ifdef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA static bool first_irq = true; #endif -static struct cur_line_info_t g_cur_line_info; +static struct cur_line_info_t g_cur_line_info[2]; static u8 new_frame_mask; static bool need_force_black; static u32 always_new_vf_cnt; @@ -2467,9 +2468,9 @@ static void check_src_fmt_change(void) } } -static void set_cur_line_info(void) +static void set_cur_line_info(u8 index) { - struct cur_line_info_t *cur_line_info = &g_cur_line_info; + struct cur_line_info_t *cur_line_info = &g_cur_line_info[index]; struct timeval start; do_gettimeofday(&start); @@ -2481,9 +2482,9 @@ static void set_cur_line_info(void) cur_line_info->end4 = start; } -struct cur_line_info_t *get_cur_line_info(void) +struct cur_line_info_t *get_cur_line_info(u8 index) { - return &g_cur_line_info; + return &g_cur_line_info[index]; } static inline void trace_performance(struct cur_line_info_t *cur_line_info, @@ -2555,7 +2556,7 @@ static void over_field_info_record(void) bool valid_mode = false; u32 timeinfo_th = 0; u32 enc_num = get_cur_enc_num(); - struct cur_line_info_t *cur_line_info = get_cur_line_info(); + struct cur_line_info_t *cur_line_info = get_cur_line_info(0); struct timeval *start; start = &cur_line_info->start; @@ -2733,7 +2734,7 @@ static inline int recvx_early_proc(u8 path_index) if (gvideo_recv[path_index]) { /* normal mode: true; lowlatency mode: false */ gvideo_recv[path_index]->irq_mode = true; - gvideo_recv[path_index]->func->early_proc(gvideo_recv[path_index], + gvideo_recv[path_index]->func->early_proc(gvideo_recv[path_index], //0); over_field ? 1 : 0); } } @@ -2747,7 +2748,7 @@ static int amvideo_early_proc(u8 layer_id) struct vframe_s *vf; struct vframe_s *vf_tmp; s32 vd1_path_id = glayer_info[0].display_path_id; - struct cur_line_info_t *cur_line_info = get_cur_line_info(); + struct cur_line_info_t *cur_line_info = get_cur_line_info(0); vd_dispbuf_to_put(layer_id); get_count_pip[0] = 0; @@ -2975,19 +2976,26 @@ static int vdx_misc_early_proc(u8 layer_id, #endif /* prevsync + postvsync case */ if (cur_dev->pre_vsync_enable) { - if (layer_id == 0 && frc_n2m_worked()) { + if (layer_id == 0) { + u32 pts_inc_scale_base = 0; + + if (frc_n2m_worked()) + pts_inc_scale_base = vsync_pts_inc_scale_base / 2; + else + pts_inc_scale_base = vsync_pts_inc_scale_base; #ifdef CONFIG_AMLOGIC_VIDEO_COMPOSER vsync_notify_video_composer(layer_id, vsync_pts_inc_scale, - vsync_pts_inc_scale_base / 2); + pts_inc_scale_base); #endif #ifdef CONFIG_AMLOGIC_VIDEOQUEUE vsync_notify_videoqueue(layer_id, vsync_pts_inc_scale, - vsync_pts_inc_scale_base / 2); + pts_inc_scale_base); #endif pre_vsync_notify = true; } + if (layer_id != 0 && !post_vsync_notify) { #ifdef CONFIG_AMLOGIC_VIDEO_COMPOSER vsync_notify_video_composer(layer_id, @@ -4080,7 +4088,7 @@ RUN_FIRST_RDMA: vsync_rdma_process(); set_vd_pi_input_size(); enc_line = get_cur_enc_line(); - cur_line_info = get_cur_line_info(); + cur_line_info = get_cur_line_info(0); vpp_trace_encline("AFTER-RDMA", cur_line_info->enc_line_start, enc_line); trace_performance(cur_line_info, enc_line); @@ -4640,6 +4648,8 @@ void pre_vsync_process(void) struct vd_func_s *cur_pre_func = NULL; s32 vd_path_id[MAX_VD_LAYER] = {0}; struct path_id_s path_id; + struct cur_line_info_t *cur_line_info = NULL; + int enc_line; if (cur_dev->vsync_2to1_enable && frc_n2m_worked()) { #ifdef CONFIG_AMLOGIC_VIDEO_COMPOSER @@ -4653,7 +4663,12 @@ void pre_vsync_process(void) vsync_pts_inc_scale_base / 2); #endif } - set_cur_line_info(); + + set_cur_line_info(1); + enc_line = get_cur_enc_line(); + cur_line_info = get_cur_line_info(1); + vpp_trace_encline("ENTER-PRE-VSYNC", cur_line_info->enc_line_start, enc_line); + for (i = 0; i < MAX_VD_LAYER; i++) vd_path_id[i] = glayer_info[i].display_path_id; path_id.vd1_path_id = vd_path_id[0]; @@ -4665,7 +4680,7 @@ void pre_vsync_process(void) vd_layer[0].cur_pre_func = vd_layer[0].next_pre_func; cur_pre_func = vd_layer[0].cur_pre_func; if (!cur_pre_func) - return; + goto pre_exit_1; #ifdef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA pre_vsync_rdma_config_pre(); @@ -4677,13 +4692,13 @@ void pre_vsync_process(void) ret = cur_pre_func->vd_misc_early_proc (0, rdma_enable, _rdma_enable_pre); if (ret < 0) - goto pre_exit; + goto pre_exit_2; } /* early process */ if (cur_pre_func->vd_early_process) { ret = cur_pre_func->vd_early_process(0, 0); if (ret < 0) - goto pre_exit; + goto pre_exit_2; } if (cur_pre_func->vd_toggle_frame) { @@ -4709,7 +4724,7 @@ void pre_vsync_process(void) /* filter setting management */ if (cur_pre_func->vd_render_frame) cur_pre_func->vd_render_frame(&vd_layer[0], vinfo); -pre_exit: +pre_exit_2: if (cur_pre_func->vd_late_process) cur_pre_func->vd_late_process(0, 0); @@ -4721,6 +4736,10 @@ pre_exit: pre_vsync_rdma_enable_pre = is_pre_vsync_rdma_enable(); #endif cur_vd1_path_id = vd_path_id[0]; +pre_exit_1: + //trace_for_pre_vsync(); + enc_line = get_cur_enc_line(); + vpp_trace_encline("AFTER-PRE-VSYNC-RDMA", cur_line_info->enc_line_start, enc_line); } #endif @@ -4737,13 +4756,18 @@ void post_vsync_process(void) bool path_switch = false; u32 path_frame_index; struct path_id_s path_id; + struct cur_line_info_t *cur_line_info = NULL; + int enc_line; #ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION if (is_amdv_on()) print_dv_ro(); #endif - set_cur_line_info(); + set_cur_line_info(0); + enc_line = get_cur_enc_line(); + cur_line_info = get_cur_line_info(0); + vpp_trace_encline("ENTER-VSYNC", cur_line_info->enc_line_start, enc_line); if (cur_dev->display_module != S5_DISPLAY_MODULE) blend_reg_conflict_detect(); @@ -5857,6 +5881,15 @@ void set_vsync_2to1_mode(u8 enable) } EXPORT_SYMBOL(set_vsync_2to1_mode); +void set_pre_vsync_mode(u8 enable) +{ + if (cur_dev->prevsync_support) { + cur_dev->pre_vsync_enable = enable; + vd1_set_go_field(); + } +} +EXPORT_SYMBOL(set_pre_vsync_mode); + /********************************************************* * Utilities *********************************************************/ diff --git a/drivers/media/video_sink/video_func.h b/drivers/media/video_sink/video_func.h index 83b7b072a..83270a01a 100644 --- a/drivers/media/video_sink/video_func.h +++ b/drivers/media/video_sink/video_func.h @@ -162,7 +162,7 @@ int get_display_info(void *data); struct vframe_s *amvideo_toggle_frame (s32 *vd_path_id); struct vframe_s *get_dispbuf(u8 layer_id); -struct cur_line_info_t *get_cur_line_info(void); +struct cur_line_info_t *get_cur_line_info(u8 index); inline bool is_tunnel_mode(const char *receiver_name); void post_vsync_process(void); diff --git a/drivers/media/video_sink/video_hw.c b/drivers/media/video_sink/video_hw.c index 3590cf02d..f064a25dd 100644 --- a/drivers/media/video_sink/video_hw.c +++ b/drivers/media/video_sink/video_hw.c @@ -9467,8 +9467,9 @@ int set_layer_slice_display_canvas_s5(struct video_layer_s *layer, struct canvas_s tmp; canvas_read(cur_canvas_tbl[0], &tmp); - pr_info("%s %d: vf:%px, y:%02x, adr:0x%lx, canvas0Addr:%x, pnum:%d, type:%x, flag:%x, afbc:0x%lx-0x%lx, vf->vf_ext:%px, line:%d\n", + pr_info("%s %d: vf:%p, omx_index=%d, y:%02x, adr:0x%lx, canvas0Addr:%x, pnum:%d, type:%x, flag:%x, afbc:0x%lx-0x%lx, vf->vf_ext:%px, line:%d\n", __func__, layer_id, vf, + vf->omx_index, cur_canvas_tbl[0], tmp.addr, vf->canvas0Addr, vf->plane_num, vf->type, vf->flag, @@ -9691,9 +9692,10 @@ int set_layer_display_canvas(struct video_layer_s *layer, struct canvas_s tmp; canvas_read(cur_canvas_tbl[0], &tmp); - pr_info("%s %d: update_mif %d: vf:%px, y:%02x, adr:0x%lx (0x%lx), canvas0:%x, pnum:%d, type:%x, flag:%x, afbc:0x%lx-0x%lx, vf_ext:%px uvm_vf:%px di_flag:%x size:%d %d, vframe size:%d line:%d\n", + pr_info("%s %d: update_mif %d: vf:%p, omx_index=%d, y:%02x, adr:0x%lx (0x%lx), canvas0:%x, pnum:%d, type:%x, flag:%x, afbc:0x%lx-0x%lx, vf_ext:%px uvm_vf:%px di_flag:%x size:%d %d, vframe size:%d line:%d\n", __func__, layer_id, update_mif ? 1 : 0, - vf, cur_canvas_tbl[0], tmp.addr, vf->canvas0_config[0].phy_addr, + vf, vf->omx_index, cur_canvas_tbl[0], + tmp.addr, vf->canvas0_config[0].phy_addr, vf->canvas0Addr, vf->plane_num, vf->type, vf->flag, vf->compHeadAddr, vf->compBodyAddr, @@ -10438,6 +10440,12 @@ static void vd_set_alpha(struct video_layer_s *layer, u32 win_en = alpha_win->win_en; vpp_index = layer->vpp_index; + /* for vd1 pip alpha, always after memc, need used post vsync */ + if (layer->layer_id == 0 && + cur_dev->pre_vsync_enable && + vpp_index == PRE_VSYNC) + vpp_index = VPP0; + if (!win_en) alph_gen_byps = 1; cur_dev->rdma_func[vpp_index].rdma_wr(vpp_blend_reg->vd_pip_alph_ctrl, @@ -13166,12 +13174,16 @@ static void vd_set_go_field_default(void) void vd1_set_go_field(void) { if (cur_dev->prevsync_support) { - if (cur_dev->pre_vsync_enable) - /* set vd1 vpp0_pre_go_field if it is vpp0 */ - WRITE_VCBUS_REG_BITS(PATH_START_SEL, 0, 0, 2); - else - /* set vd1 vpp0_post_go_field if it is vpp0 */ - WRITE_VCBUS_REG_BITS(PATH_START_SEL, 3, 0, 2); + if (cur_dev->display_module == S5_DISPLAY_MODULE) { + vd1_set_go_field_s5(); + } else { + if (cur_dev->pre_vsync_enable) + /* set vd1 vpp0_pre_go_field if it is vpp0 */ + WRITE_VCBUS_REG_BITS(PATH_START_SEL, 0, 0, 2); + else + /* set vd1 vpp0_post_go_field if it is vpp0 */ + WRITE_VCBUS_REG_BITS(PATH_START_SEL, 3, 0, 2); + } } } diff --git a/drivers/media/video_sink/video_hw_s5.c b/drivers/media/video_sink/video_hw_s5.c index d52c3aa87..c3ce8aded 100644 --- a/drivers/media/video_sink/video_hw_s5.c +++ b/drivers/media/video_sink/video_hw_s5.c @@ -11469,6 +11469,12 @@ void vd_set_alpha_s5(struct video_layer_s *layer, return; vd_pip_alpha_reg = &vd_proc_reg.vd_pip_alpha_reg[layer_id]; vpp_index = layer->vpp_index; + /* for vd1 pip alpha, always after memc, need used post vsync */ + if (layer_id == 0 && + cur_dev->pre_vsync_enable && + vpp_index == PRE_VSYNC) + vpp_index = VPP0; + if (!win_en) alph_gen_byps = 1; cur_dev->rdma_func[vpp_index].rdma_wr(vd_pip_alpha_reg->vd_pip_alph_ctrl, @@ -12176,6 +12182,23 @@ void update_frc_in_size(struct video_layer_s *layer) layer->next_frame_par->frc_v_size = layer->next_frame_par->nnhf_input_h; } +void vd1_set_go_field_s5(void) +{ + if (cur_dev->prevsync_support) { + if (video_is_meson_t3x_cpu()) { + if (cur_dev->pre_vsync_enable) { + /* set vd1 vpp0_pre_go_field if it is vpp0 */ + WRITE_VCBUS_REG_BITS(S5_VIU_VD1_MISC, 3, 0, 2); + WRITE_VCBUS_REG_BITS(S5_VIU_VD2_MISC, 3, 0, 2); + } else { + /* set vd1 vpp0_post_go_field if it is vpp0 */ + WRITE_VCBUS_REG_BITS(S5_VIU_VD1_MISC, 0, 0, 2); + WRITE_VCBUS_REG_BITS(S5_VIU_VD2_MISC, 0, 0, 2); + } + } + } +} + static void save_vd_pps_reg(void) { int i; diff --git a/drivers/media/video_sink/video_hw_s5.h b/drivers/media/video_sink/video_hw_s5.h index 4d35c3904..5b0795a19 100644 --- a/drivers/media/video_sink/video_hw_s5.h +++ b/drivers/media/video_sink/video_hw_s5.h @@ -419,4 +419,5 @@ u32 get_pps_data(int slice); u32 get_vpu_venc_error_status(void); void clear_vpu_venc_error(void); void update_frc_in_size(struct video_layer_s *layer); +void vd1_set_go_field_s5(void); #endif diff --git a/drivers/media/video_sink/video_priv.h b/drivers/media/video_sink/video_priv.h index 25927dca8..391cf3857 100644 --- a/drivers/media/video_sink/video_priv.h +++ b/drivers/media/video_sink/video_priv.h @@ -971,6 +971,7 @@ bool video_is_meson_t3_cpu(void); bool video_is_meson_c3_cpu(void); bool video_is_meson_t5w_cpu(void); bool video_is_meson_s5_cpu(void); +bool video_is_meson_t3x_cpu(void); bool video_is_meson_t5m_cpu(void); bool video_is_meson_txhd2_cpu(void); bool video_is_meson_s1a_cpu(void); diff --git a/drivers/media/video_sink/video_receiver.c b/drivers/media/video_sink/video_receiver.c index 32e10f8a9..7da6c923e 100644 --- a/drivers/media/video_sink/video_receiver.c +++ b/drivers/media/video_sink/video_receiver.c @@ -88,9 +88,9 @@ static inline struct vframe_s *common_vf_get(struct video_recv_s *ins) if (vf) { if (debug_flag & DEBUG_FLAG_PRINT_FRAME_DETAIL) - pr_info("%s:vf=%p, vf->type=0x%x, vf->flag=0x%x,canvas adr:0x%lx, canvas0:%x, pnum:%d, afbc:0x%lx-0x%lx,\n", + pr_info("%s:vf=%p, omx_index=%d, vf->type=0x%x, vf->flag=0x%x,canvas adr:0x%lx, canvas0:%x, pnum:%d, afbc:0x%lx-0x%lx\n", __func__, - vf, vf->type, vf->flag, + vf, vf->omx_index, vf->type, vf->flag, vf->canvas0_config[0].phy_addr, vf->canvas0Addr, vf->plane_num, vf->compHeadAddr, vf->compBodyAddr); vpp_trace_vframe("common_vf_get", @@ -144,9 +144,9 @@ static inline void common_vf_put(struct video_recv_s *ins, ins->vpp_id, vsync_cnt[ins->vpp_id]); vf_put(vf, ins->recv_name); if (debug_flag & DEBUG_FLAG_PRINT_FRAME_DETAIL) - pr_info("%s:vf=%p, vf->type=0x%x, vf->flag=0x%x,canvas adr:0x%lx, canvas0:%x, pnum:%d, afbc:0x%lx-0x%lx,\n", + pr_info("%s:vf=%p, omx_index=%d, vf->type=0x%x, vf->flag=0x%x,canvas adr:0x%lx, canvas0:%x, pnum:%d, afbc:0x%lx-0x%lx\n", __func__, - vf, vf->type, vf->flag, + vf, vf->omx_index, vf->type, vf->flag, vf->canvas0_config[0].phy_addr, vf->canvas0Addr, vf->plane_num, vf->compHeadAddr, vf->compBodyAddr); #ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION diff --git a/drivers/media/video_sink/vpp_post_s5.c b/drivers/media/video_sink/vpp_post_s5.c index 0b688da64..f4cde389f 100644 --- a/drivers/media/video_sink/vpp_post_s5.c +++ b/drivers/media/video_sink/vpp_post_s5.c @@ -880,7 +880,8 @@ static int vpp_blend_param_set(struct vpp_post_input_s *vpp_input, vpp_post_blend->bld_out_en = 1; /* 1:din0 2:din1 3:din2 4:din3 5:din4 else :close */ - if (vd_layer[0].vpp_index == VPP0) { + if (vd_layer[0].vpp_index == VPP0 || + vd_layer[0].vpp_index == PRE_VSYNC) { if (vd_layer[0].post_blend_en) vpp_post_blend->bld_src1_sel = 1; else diff --git a/include/linux/amlogic/media/rdma/rdma_mgr.h b/include/linux/amlogic/media/rdma/rdma_mgr.h index ef3ea3a91..ccb8a9950 100644 --- a/include/linux/amlogic/media/rdma/rdma_mgr.h +++ b/include/linux/amlogic/media/rdma/rdma_mgr.h @@ -16,6 +16,7 @@ struct rdma_op_s { #define RDMA_TRIGGER_VPP1_VSYNC_INPUT BIT(9) #define RDMA_TRIGGER_VPP2_VSYNC_INPUT BIT(19) #define RDMA_TRIGGER_PRE_VSYNC_INPUT BIT(24) +#define RDMA_TRIGGER_PRE_VSYNC_INPUT_T3X BIT(10) #define RDMA_TRIGGER_MANUAL BIT(28) #define RDMA_TRIGGER_DEBUG1 BIT(29) #define RDMA_TRIGGER_DEBUG2 BIT(30) diff --git a/include/linux/amlogic/media/video_sink/video.h b/include/linux/amlogic/media/video_sink/video.h index 4287ac289..97ef58ba4 100644 --- a/include/linux/amlogic/media/video_sink/video.h +++ b/include/linux/amlogic/media/video_sink/video.h @@ -510,6 +510,7 @@ u32 get_tvin_delay_min_ms(void); u32 get_tvin_dv_flag(void); void clear_vsync_2to1_info(void); void set_vsync_2to1_mode(u8 enable); +void set_pre_vsync_mode(u8 enable); void get_vdx_axis(u32 index, int *buf); void vpu_module_clk_enable(u32 vpp_index, u32 module, bool async);