From 59bbff3a08f027754b2da3e4dcdeb52c506e3630 Mon Sep 17 00:00:00 2001 From: "ruofei.zhao" Date: Tue, 3 Dec 2024 17:07:42 +0800 Subject: [PATCH] hdmitx: dump hdmitx phy and pll regs [1/1] PD#SWPL-194568 Problem: need to dump hdmitx phy and pll registers Solution: add nodes for dumping hdmitx phy and pll registers Verify: S905X5 Test: DRM-TX-78 Change-Id: I26da4af5ec4280c58b4d02fa0157e027e442d7d2 Signed-off-by: ruofei.zhao --- drivers/media/vout/hdmitx20/hw/hdmi_tx_dump.c | 52 +++++++++++ drivers/media/vout/hdmitx21/hw/hdmi_tx_dump.c | 90 ++++++++++++++++++- 2 files changed, 141 insertions(+), 1 deletion(-) diff --git a/drivers/media/vout/hdmitx20/hw/hdmi_tx_dump.c b/drivers/media/vout/hdmitx20/hw/hdmi_tx_dump.c index dd548cd14..6a5cc9b6c 100644 --- a/drivers/media/vout/hdmitx20/hw/hdmi_tx_dump.c +++ b/drivers/media/vout/hdmitx20/hw/hdmi_tx_dump.c @@ -18,6 +18,7 @@ #include "mach_reg.h" #include "reg_ops.h" #include "hdmi_tx_reg.h" +#include "reg_sc2.h" #define PR_BUS(a) \ do { \ @@ -28,8 +29,58 @@ hd_read_reg(addr)); \ } while (0) +#define PR_ANACTRL(a) \ + do { \ + typeof(a) addr = (a); \ + seq_printf(s, "[0x%08x] = 0x%08x\n", \ + TO_PHY_ADDR(addr), \ + hd_read_reg(addr)); \ + } while (0) + static inline unsigned int get_msr_cts(void); +static int dump_hdmi_phy_pll_reg_show(struct seq_file *s, void *p) +{ + int i; + struct hdmitx_dev *hdev = get_hdmitx_device(); + + seq_puts(s, "\n--------HDMITX basic information --------\n"); + seq_printf(s, "resolution: %s\n", hdev->tx_comm.fmt_para.name); + seq_printf(s, "attr: %s\n", hdev->tx_comm.fmt_attr); + seq_printf(s, "tmds clock: %dkhz\n", hdev->tx_comm.fmt_para.tmds_clk); + + switch (hdev->tx_hw.chip_data->chip_type) { + case MESON_CPU_ID_SC2: + if (reg_maps[ANACTRL_REG_IDX].phy_addr) { + seq_puts(s, "\n--------ANACTRL_HDMIPHY registers--------\n"); + /* ((0x0080 << 2) + 0xfe008000) ~ ((0x0085 << 2) + 0xfe008000) */ + for (i = ANACTRL_HDMIPHY_CTRL0; i <= ANACTRL_HDMIPHY_CTRL5; i++) + PR_ANACTRL(ANACTRL_REG_ADDR(i)); + + seq_puts(s, "\n--------ANACTRL_HDMIPLL registers--------\n"); + /* ((0x0070 << 2) + 0xfe008000) ~ ((0x0076 << 2) + 0xfe008000) */ + for (i = ANACTRL_HDMIPLL_CTRL0; i <= ANACTRL_HDMIPLL_CTRL6; i++) + PR_ANACTRL(ANACTRL_REG_ADDR(i)); + } + break; + default: + break; + } + + return 0; +} + +static int dump_hdmi_phy_pll_regs_open(struct inode *inode, struct file *file) +{ + return single_open(file, dump_hdmi_phy_pll_reg_show, inode->i_private); +} + +static const struct file_operations dump_hdmi_phy_pll_reg_fops = { + .open = dump_hdmi_phy_pll_regs_open, + .read = seq_read, + .release = single_release, +}; + static int dump_regs_show(struct seq_file *s, void *p) { int i; @@ -1521,6 +1572,7 @@ static struct hdmitx_dbg_files_s hdmitx_dbg_files[] = { {"hdmi_pkt", S_IFREG | 0444, &dump_hdmipkt_fops}, {"hdmi_ver", S_IFREG | 0444, &dump_hdmiver_fops}, {"aud_cts", S_IFREG | 0444, &dump_audcts_fops}, + {"hdmi_phy_pll_reg", S_IFREG | 0444, &dump_hdmi_phy_pll_reg_fops}, }; static struct dentry *hdmitx_dbgfs; diff --git a/drivers/media/vout/hdmitx21/hw/hdmi_tx_dump.c b/drivers/media/vout/hdmitx21/hw/hdmi_tx_dump.c index 7693e39ba..c054baed2 100644 --- a/drivers/media/vout/hdmitx21/hw/hdmi_tx_dump.c +++ b/drivers/media/vout/hdmitx21/hw/hdmi_tx_dump.c @@ -29,11 +29,97 @@ static void dump32(struct seq_file *s, u32 start, u32 end) for (; start <= end; start += 4) { value = hd21_read_reg(start); - seq_printf(s, "[0x%08x] 0x%08x\n", + seq_printf(s, "[0x%08x] = 0x%08x\n", TO21_PHY_ADDR(start), value); } } +static int dump_hdmi_phy_pll_show(struct seq_file *s, void *p) +{ + struct hdmitx_dev *hdev = get_hdmitx21_device(); + + seq_puts(s, "\n--------HDMITX basic information --------\n"); + seq_printf(s, "resolution: %s\n", hdev->tx_comm.fmt_para.name); + seq_printf(s, "attr: %s\n", hdev->tx_comm.fmt_attr); + seq_printf(s, "tmds clock: %dkhz\n", hdev->tx_comm.fmt_para.tmds_clk); + if (hdev->frl_rate != FRL_NONE) { + seq_printf(s, "frl rate: %d\n", hdev->frl_rate); + switch (hdev->frl_rate) { + case FRL_3G3L: + seq_puts(s, "FRL_3G3L\n"); + break; + case FRL_6G3L: + seq_puts(s, "FRL_6G3L\n"); + break; + case FRL_6G4L: + seq_puts(s, "FRL_6G4L\n"); + break; + case FRL_8G4L: + seq_puts(s, "FRL_8G4L\n"); + break; + case FRL_10G4L: + seq_puts(s, "FRL_10G4L\n"); + break; + case FRL_12G4L: + seq_puts(s, "FRL_12G4L\n"); + break; + default: + break; + } + } + + switch (hdev->tx_hw.chip_data->chip_type) { + case MESON_CPU_ID_S6: + case MESON_CPU_ID_S7D: + case MESON_CPU_ID_S7: + seq_puts(s, "\n--------ANACTRL_HDMIPHY registers--------\n"); + /* ((0x0080 << 2) + 0xfe008000) ~ ((0x0085 << 2) + 0xfe008000) */ + dump32(s, ANACTRL_HDMIPHY_CTRL0, ANACTRL_HDMIPHY_CTRL5); + seq_puts(s, "\n--------ANACTRL_HDMIPLL registers--------\n"); + /* ((0x0070 << 2) + 0xfe008000) ~ ((0x0073 << 2) + 0xfe008000) */ + dump32(s, ANACTRL_HDMIPLL_CTRL0, ANACTRL_HDMIPLL_CTRL3); + break; + case MESON_CPU_ID_S1A: + case MESON_CPU_ID_T7: + seq_puts(s, "\n--------ANACTRL_HDMIPHY registers--------\n"); + /* ((0x0080 << 2) + 0xfe008000) ~ ((0x0085 << 2) + 0xfe008000) */ + dump32(s, ANACTRL_HDMIPHY_CTRL0, ANACTRL_HDMIPHY_CTRL5); + seq_puts(s, "\n--------ANACTRL_HDMIPLL registers--------\n"); + /* ((0x0070 << 2) + 0xfe008000) ~ ((0x0076 << 2) + 0xfe008000) */ + dump32(s, ANACTRL_HDMIPLL_CTRL0, ANACTRL_HDMIPLL_CTRL6); + break; + case MESON_CPU_ID_S5: + seq_puts(s, "\n--------ANACTRL_HDMIPHY registers--------\n"); + /* ((0x0080 << 2) + 0xfe008000) ~ ((0x0086 << 2) + 0xfe008000) */ + dump32(s, ANACTRL_HDMIPHY_CTRL0, ANACTRL_HDMIPHY_CTRL6); + seq_puts(s, "\n--------ANACTRL_HDMIPLL registers--------\n"); + /* ((0x0070 << 2) + 0xfe008000) ~ ((0x0077 << 2) + 0xfe008000) */ + dump32(s, ANACTRL_HDMIPLL_CTRL0, ANACTRL_HDMIPLL_STS); + break; + default: + break; + } + + return 0; +} + +static int dump_hdmi_phy_pll_open(struct inode *inode, struct file *file) +{ + return single_open(file, dump_hdmi_phy_pll_show, inode->i_private); +} + +static const struct file_operations dump_hdmi_phy_pll_reg_fops = { + .open = dump_hdmi_phy_pll_open, + .read = seq_read, + .release = single_release, +}; + +static const struct proc_ops dump_hdmi_phy_pll_reg_pops = { + .proc_open = dump_hdmi_phy_pll_open, + .proc_read = seq_read, + .proc_release = single_release, +}; + static int dump_regs_show(struct seq_file *s, void *p) { struct hdmitx_dev *hdev = get_hdmitx21_device(); @@ -945,6 +1031,8 @@ static struct hdmitx_dbg_files_s hdmitx_dbg_files[] = { #endif {"cts_enc_clk", S_IFREG | 0444, &dump_cts_enc_clk_fops, &dump_cts_enc_clk_pops}, {"frl_status", S_IFREG | 0444, &dump_frl_status_fops, &dump_frl_status_pops}, + {"hdmi_phy_pll_reg", S_IFREG | 0444, &dump_hdmi_phy_pll_reg_fops, + &dump_hdmi_phy_pll_reg_pops}, }; static struct dentry *hdmitx_file_dbgfs;