From 60550567f3452004dc927e2ea4ef37cc9392adeb Mon Sep 17 00:00:00 2001 From: jiebing chen Date: Mon, 19 Aug 2024 20:03:51 +0800 Subject: [PATCH] Audio: add ad82120b driver support [2/2] PD#SWPL-182569 Problem: need to support ad82120b driver Solution: add ad82120b driver Verify: use T6d Change-Id: I04ad5d64af2241dc5b7e051afa0052f5153b8238 Signed-off-by: jiebing chen --- .../dts/amlogic/t6d_t950d5_br301_1.5g.dts | 9 +- .../boot/dts/amlogic/t6d_t950d5_br301_1g.dts | 11 +- .../dts/amlogic/t6d_t950d5_br309_1.5g.dts | 2 +- .../boot/dts/amlogic/t6d_t950d5_br309_1g.dts | 6 +- arch/arm/configs/amlogic_a32.fragment | 7 + sound/soc/codecs/amlogic/Kconfig | 11 + sound/soc/codecs/amlogic/Makefile | 7 + sound/soc/codecs/amlogic/ad82120b.c | 1446 +++++++++++++++++ sound/soc/codecs/amlogic/ad82120b.h | 66 + .../amlogic/ad82120b_eq/ad82120b_eq_mode_1.h | 510 ++++++ .../amlogic/ad82120b_eq/ad82120b_eq_mode_2.h | 511 ++++++ 11 files changed, 2572 insertions(+), 14 deletions(-) create mode 100644 sound/soc/codecs/amlogic/ad82120b.c create mode 100644 sound/soc/codecs/amlogic/ad82120b.h create mode 100644 sound/soc/codecs/amlogic/ad82120b_eq/ad82120b_eq_mode_1.h create mode 100644 sound/soc/codecs/amlogic/ad82120b_eq/ad82120b_eq_mode_2.h diff --git a/arch/arm/boot/dts/amlogic/t6d_t950d5_br301_1.5g.dts b/arch/arm/boot/dts/amlogic/t6d_t950d5_br301_1.5g.dts index 5a862be73..c9f596d50 100644 --- a/arch/arm/boot/dts/amlogic/t6d_t950d5_br301_1.5g.dts +++ b/arch/arm/boot/dts/amlogic/t6d_t950d5_br301_1.5g.dts @@ -533,6 +533,7 @@ compatible = "amlogic, auge-sound-card"; aml-audio-card,name = "AML-AUGESOUND"; + avout_mute-gpios = <&gpio GPIOD_6 GPIO_ACTIVE_HIGH>; spk_mute-gpios = <&gpio GPIOD_9 GPIO_ACTIVE_LOW>; spk_mute_sleep_time = <800>; @@ -1192,12 +1193,12 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins1>; clock-frequency = <300000>; - ad82128: ad82128@6c { - compatible = "ESMT,ad82128"; + ad82120b: ad82120b@6c { + compatible = "ESMT,ad82120b"; #sound-dai-cells = <0>; - //reset_pin-gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; + reset_pin-gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; reg = <0x6c>; - status = "okay"; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/amlogic/t6d_t950d5_br301_1g.dts b/arch/arm/boot/dts/amlogic/t6d_t950d5_br301_1g.dts index 46abf8105..46b19db89 100644 --- a/arch/arm/boot/dts/amlogic/t6d_t950d5_br301_1g.dts +++ b/arch/arm/boot/dts/amlogic/t6d_t950d5_br301_1g.dts @@ -533,6 +533,7 @@ compatible = "amlogic, auge-sound-card"; aml-audio-card,name = "AML-AUGESOUND"; + avout_mute-gpios = <&gpio GPIOD_6 GPIO_ACTIVE_HIGH>; spk_mute-gpios = <&gpio GPIOD_9 GPIO_ACTIVE_LOW>; spk_mute_sleep_time = <800>; @@ -597,7 +598,7 @@ }; tdmbcodec: codec { prefix-names = "AMP"; - sound-dai = ; + sound-dai = ; }; }; @@ -1161,12 +1162,12 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins1>; clock-frequency = <300000>; - ad82128: ad82128@6c { - compatible = "ESMT,ad82128"; + ad82120b: ad82120b@6c { + compatible = "ESMT,ad82120b"; #sound-dai-cells = <0>; - //reset_pin-gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; + reset_pin-gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; reg = <0x6c>; - status = "okay"; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/amlogic/t6d_t950d5_br309_1.5g.dts b/arch/arm/boot/dts/amlogic/t6d_t950d5_br309_1.5g.dts index 4bb0ffde0..489ceef6a 100644 --- a/arch/arm/boot/dts/amlogic/t6d_t950d5_br309_1.5g.dts +++ b/arch/arm/boot/dts/amlogic/t6d_t950d5_br309_1.5g.dts @@ -545,7 +545,7 @@ avout_mute-gpios = <&gpio GPIOD_6 GPIO_ACTIVE_HIGH>; /* headphone insert det */ - // aml-audio-card,hp-det-gpio = <&analog_gpio CDAC_IOUT GPIO_ACTIVE_LOW>; + aml-audio-card,hp-det-gpio = <&gpio_analog CDAC_IOUT GPIO_ACTIVE_LOW>; interrupts = ; interrupt-names = "audio_exception64"; diff --git a/arch/arm/boot/dts/amlogic/t6d_t950d5_br309_1g.dts b/arch/arm/boot/dts/amlogic/t6d_t950d5_br309_1g.dts index 49b099a2a..c0fcb498a 100644 --- a/arch/arm/boot/dts/amlogic/t6d_t950d5_br309_1g.dts +++ b/arch/arm/boot/dts/amlogic/t6d_t950d5_br309_1g.dts @@ -543,12 +543,10 @@ auge_sound { compatible = "amlogic, auge-sound-card"; aml-audio-card,name = "AML-AUGESOUND"; - avout_mute-gpios = <&gpio GPIOD_6 GPIO_ACTIVE_HIGH>; /* headphone insert det */ - // aml-audio-card,hp-det-gpio = <&analog_gpio CDAC_IOUT GPIO_ACTIVE_LOW>; - - interrupts = ; + aml-audio-card,hp-det-gpio = <&gpio_analog CDAC_IOUT GPIO_ACTIVE_LOW>; + interrupts = ; interrupt-names = "audio_exception64"; aml-audio-card,dai-link@0 { diff --git a/arch/arm/configs/amlogic_a32.fragment b/arch/arm/configs/amlogic_a32.fragment index e6b0b467d..6c8beb4ea 100644 --- a/arch/arm/configs/amlogic_a32.fragment +++ b/arch/arm/configs/amlogic_a32.fragment @@ -415,6 +415,9 @@ CONFIG_AMLOGIC_SND_CODEC_TL1_ACODEC=m #amlogic-snd-codec-t6d.ko CONFIG_AMLOGIC_SND_CODEC_T6D_ACODEC=m +#snd-soc-ad82120b.ko +CONFIG_AMLOGIC_SND_SOC_AD82120B=m + # snd-soc-tas5805.ko CONFIG_AMLOGIC_SND_SOC_TAS5805=m @@ -423,6 +426,10 @@ CONFIG_AMLOGIC_SND_SOC_PA1=m #snd-soc-AD82128.ko CONFIG_AMLOGIC_SND_SOC_AD82128=m + +# amlogic-snd-codec-tas5707.ko +CONFIG_AMLOGIC_SND_SOC_TAS5707=m + # amlogic-usb ko CONFIG_AMLOGIC_USB=y CONFIG_AMLOGIC_USB_SUPPORT=m diff --git a/sound/soc/codecs/amlogic/Kconfig b/sound/soc/codecs/amlogic/Kconfig index 55c96495b..1051a68d4 100644 --- a/sound/soc/codecs/amlogic/Kconfig +++ b/sound/soc/codecs/amlogic/Kconfig @@ -254,6 +254,17 @@ config AMLOGIC_SND_SOC_AD82584F Enable Support for ESMT AD82584f CODEC. Select this if your AD82584F is connected via an I2C bus. +config AMLOGIC_SND_SOC_AD82120B + tristate "ESMT AD82120B" + depends on AMLOGIC_SND_SOC_CODECS + depends on I2C + default n + help + Enable Support for ESMT AD82120B CODEC. + Select this if your AD82120B is connected via an I2C bus. + Enable Support for ESMT AD82120B CODEC. + Select this if your AD82120B is connected via an I2C bus. + config AMLOGIC_SND_SOC_CS42528 tristate "Cirrus Logic CS42528" depends on AMLOGIC_SND_SOC_CODECS diff --git a/sound/soc/codecs/amlogic/Makefile b/sound/soc/codecs/amlogic/Makefile index 48ef74660..ef3d46fe1 100644 --- a/sound/soc/codecs/amlogic/Makefile +++ b/sound/soc/codecs/amlogic/Makefile @@ -95,3 +95,10 @@ PR_FMT_DEFINE_SY6026L = "-Dpr_fmt(fmt)= \"[$(PR_FMT_SY6026L)]: \" fmt" obj-$(CONFIG_AMLOGIC_SND_SOC_SY6026L) += $(MODULE_NAME_SY6026L).o CFLAGS_SY6026L.o += $(PR_FMT_DEFINE_SY6026L) $(MODULE_NAME_SY6026L)-y += sy602x.o + +MODULE_NAME_AD82120B = amlogic-snd-codec-ad82120b +PR_FMT_AD82120B = $(subst amlogic-,,$(MODULE_NAME_AD82120B)) +PR_FMT_DEFINE_AD82120B = "-Dpr_fmt(fmt)= \"[$(PR_FMT_AD82120B)]: \" fmt" +obj-$(CONFIG_AMLOGIC_SND_SOC_AD82120B) += $(MODULE_NAME_AD82120B).o +CFLAGS_ad82120b.o += $(PR_FMT_DEFINE_AD82120B) +$(MODULE_NAME_AD82120B)-y += ad82120b.o \ No newline at end of file diff --git a/sound/soc/codecs/amlogic/ad82120b.c b/sound/soc/codecs/amlogic/ad82120b.c new file mode 100644 index 000000000..b70091921 --- /dev/null +++ b/sound/soc/codecs/amlogic/ad82120b.c @@ -0,0 +1,1446 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ad82120b.h" + +// after enable,you can use "tinymix" or "amixer" cmd to change eq mode. +// If you do not need to change eq mode, you can ignore it +//#define AD82120B_CHANGE_EQ_MODE_EN + +#ifdef AD82120B_CHANGE_EQ_MODE_EN + // eq file, add Parameter file in "codec\ad82120b_eq", and then include the header file. + #include "ad82120b_eq/ad82120b_eq_mode_1.h" + #include "ad82120b_eq/ad82120b_eq_mode_2.h" + + // the value range of eq mode, modify them according to your request. + #define AD82120B_EQ_MODE_MIN 1 + #define AD82120B_EQ_MODE_MAX 2 +#endif + +/* Define how often to check (and clear) the fault status register (in ms) */ +#define AD82120B_FAULT_CHECK_INTERVAL 500 + +// you can read out the register and ram data, and check them. +//#define AD82120B_REG_RAM_CHECK + +enum ad82120b_type { + AD82120B, +}; + +static const char * const ad82120b_supply_names[] = { + "dvdd", /* Digital power supply. Connect to 3.3-V supply. */ + "pvdd", /* Class-D amp and analog power supply (connected). */ +}; + +#define AD82120B_NUM_SUPPLIES ARRAY_SIZE(ad82120b_supply_names) + +static int m_reg_tab[AD82120B_REGISTER_COUNT][2] = { +{0x00, 0x00}, //##State_Control_1 +{0x01, 0x82}, //##State_Control_2 +{0x02, 0x00}, //##State_Control_3 +{0x03, 0x40}, //##Master_volume_control +{0x04, 0x18}, //##Channel_1_volume_control +{0x05, 0x18}, //##Channel_2_volume_control +{0x06, 0x18}, //##Channel_3_volume_control +{0x07, 0x18}, //##Channel_4_volume_control +{0x08, 0x18}, //##Channel_5_volume_control +{0x09, 0x18}, //##Channel_6_volume_control +{0x0A, 0x40}, //##DTC_Setting +{0x0B, 0x00}, //##Reserve +{0x0C, 0x90}, //##State_Control_4 +{0x0D, 0x80}, //##Channel_1_configuration_registers +{0x0E, 0x80}, //##Channel_2_configuration_registers +{0x0F, 0x80}, //##Channel_3_configuration_registers +{0x10, 0x80}, //##Channel_4_configuration_registers +{0x11, 0x80}, //##Channel_5_configuration_registers +{0x12, 0x80}, //##Channel_6_configuration_registers +{0x13, 0x80}, //##Channel_7_configuration_registers +{0x14, 0x80}, //##Channel_8_configuration_registers +{0x15, 0x00}, //##Reserve +{0x16, 0x00}, //##Reserve +{0x17, 0x00}, //##Reserve +{0x18, 0x00}, //##Reserve +{0x19, 0x80}, //##Reserve +{0x1A, 0x28}, //##State_Control_5 +{0x1B, 0x80}, //##State_Control_6 +{0x1C, 0x20}, //##State_Control_7 +{0x1D, 0x00}, //##Coefficient_RAM_Base_Address +{0x1E, 0x00}, //##First_4-bits_of_coefficients_A1 +{0x1F, 0x00}, //##Second_8-bits_of_coefficients_A1 +{0x20, 0x00}, //##Third_8-bits_of_coefficients_A1 +{0x21, 0x00}, //##Fourth-bits_of_coefficients_A1 +{0x22, 0x00}, //##First_4-bits_of_coefficients_A2 +{0x23, 0x00}, //##Second_8-bits_of_coefficients_A2 +{0x24, 0x00}, //##Third_8-bits_of_coefficients_A2 +{0x25, 0x00}, //##Fourth_8-bits_of_coefficients_A2 +{0x26, 0x00}, //##First_4-bits_of_coefficients_B1 +{0x27, 0x00}, //##Second_8-bits_of_coefficients_B1 +{0x28, 0x00}, //##Third_8-bits_of_coefficients_B1 +{0x29, 0x00}, //##Fourth_8-bits_of_coefficients_B1 +{0x2A, 0x00}, //##First_4-bits_of_coefficients_B2 +{0x2B, 0x00}, //##Second_8-bits_of_coefficients_B2 +{0x2C, 0x00}, //##Third_8-bits_of_coefficients_B2 +{0x2D, 0x00}, //##Fourth-bits_of_coefficients_B2 +{0x2E, 0x00}, //##First_4-bits_of_coefficients_A0 +{0x2F, 0x80}, //##Second_8-bits_of_coefficients_A0 +{0x30, 0x00}, //##Third_8-bits_of_coefficients_A0 +{0x31, 0x00}, //##Fourth_8-bits_of_coefficients_A0 +{0x32, 0x00}, //##Coefficient_RAM_R/W_control +{0x33, 0x02}, //##State_Control_8 +{0x34, 0x00}, //##Reserve +{0x35, 0x00}, //##Volume_Fine_tune +{0x36, 0x00}, //##Volume_Fine_tune +{0x37, 0xA0}, //##Device_ID_register +{0x38, 0x00}, //##Level_Meter_Clear +{0x39, 0x00}, //##Power_Meter_Clear +{0x3A, 0x00}, //##First_8bits_of_C1_Level_Meter +{0x3B, 0x00}, //##Second_8bits_of_C1_Level_Meter +{0x3C, 0x00}, //##Third_8bits_of_C1_Level_Meter +{0x3D, 0x00}, //##Fourth_8bits_of_C1_Level_Meter +{0x3E, 0x00}, //##First_8bits_of_C2_Level_Meter +{0x3F, 0x00}, //##Second_8bits_of_C2_Level_Meter +{0x40, 0x00}, //##Third_8bits_of_C2_Level_Meter +{0x41, 0x00}, //##Fourth_8bits_of_C2_Level_Meter +{0x42, 0x00}, //##CHK_stat +{0x43, 0x00}, //##First_4_bits_of_BEQ_CHK_val +{0x44, 0x00}, //##Second_8_bits_of_BEQ_CHK_val +{0x45, 0x00}, //##Third_4_bits_of_BEQ_CHK_val +{0x46, 0x00}, //##Bottom_4_bits_of_BEQ_CHK_val +{0x47, 0x00}, //##First_4_bits_of_BEQ_CHK_result +{0x48, 0x00}, //##Second_4_bits_of_BEQ_CHK_result +{0x49, 0x00}, //##Third_4_bits_of_BEQ_CHK_result +{0x4A, 0x00}, //##Bottom_4_bits_of_BEQ_CHK_result +{0x4B, 0x10}, //##digital_DC_control +{0x4C, 0x20}, //##digital_DC_judge_threshold +{0x4D, 0xFF}, //##ERROR_register +{0x4E, 0xFF}, //##ERROR_latch_register +{0x4F, 0x00}, //##ERROR_clear_register +{0x50, 0x01}, //##ERROR_register_2 +{0x51, 0x01}, //##ERROR_latch_register_2 +{0x52, 0x00}, //##ERROR_clear_register_2 +{0x53, 0x00}, //##Reserve +{0x54, 0x00}, //##Reserve +{0x55, 0x20}, //##clock_FS_detection +{0x56, 0x10}, //##CLK_DET +{0x57, 0x00}, //##TDM_word_width_selection +{0x58, 0x00}, //##TDM_offset +{0x59, 0x06}, //##I2S_Data_output_selection_register +{0x5A, 0x08}, //##PWM_frequency_selection +{0x5B, 0x00}, //##Mono_Key_High_Byte +{0x5C, 0x00}, //##Mono_Key_Low_Byte +{0x5D, 0x07}, //##Hi-res_Item +{0x5E, 0x00}, //##analog_gain +{0x5F, 0x00}, //##AGC_Control +{0x60, 0x00}, //##Channel1_EQ_bypass_1 +{0x61, 0x00}, //##Channel1_EQ_bypass_2 +{0x62, 0x00}, //##Channel1_EQ_bypass_3 +{0x63, 0x00}, //##Channel2_EQ_bypass_1 +{0x64, 0x00}, //##Channel2_EQ_bypass_2 +{0x65, 0x00}, //##Channel2_EQ_bypass_3 +{0x66, 0x00}, //##ATTACK_HOLD_SET +{0x67, 0x00}, //##Reserve +{0x68, 0x00}, //##Reserve +{0x69, 0x00}, //##Reserve +{0x6A, 0x00}, //##Reserve +{0x6B, 0x00}, //##Reserve +{0x6C, 0x02}, //##FS_and_PMF_read_out +{0x6D, 0x03}, //##OC_Selection +{0x6E, 0x00}, //##digital_DC_control_testmode +{0x6F, 0x32}, //##test_mode_register0 +{0x70, 0x07}, //##noise_gate_analog_gain +{0x71, 0x41}, //##Testmode_register1 +{0x72, 0x38}, //##Testmode_register2 +{0x73, 0x18}, //##dither_signal_setting +{0x74, 0x0D}, //##Error_Delay +{0x75, 0x05}, //##First_4bits_of_MBIST_User_Program_Even +{0x76, 0x55}, //##Second_8bits_of_MBIST_User_Program_Even +{0x77, 0x55}, //##Third_8bits_of_MBIST_User_Program_Even +{0x78, 0x55}, //##Fourth_8bits_of_MBIST_User_Program_Even +{0x79, 0x55}, //##Fifth_8bits_of_MBIST_User_Program_Even +{0x7A, 0x05}, //##First_8bits_of_MBIST_User_Program_Odd +{0x7B, 0x55}, //##Second_8bits_of_MBIST_User_Program_Odd +{0x7C, 0x55}, //##Third_8bits_of_MBIST_User_Program_Odd +{0x7D, 0x55}, //##Fourth_8bits_of_MBIST_User_Program_Odd +{0x7E, 0x55}, //##Fifth_8bits_of_MBIST_User_Program_Odd +{0x7F, 0x50}, //##IP_shutdown_register +{0x80, 0x00}, //##Protection_Register_Set +{0x81, 0x00}, //##MBIST_Status +{0x82, 0x00}, //##PWM_output_control +{0x83, 0x00}, //##Test_Mode_Control +{0x84, 0x00}, //##RAM1_test_register_address +{0x85, 0x00}, //##First_4bits_of_RAM1_data +{0x86, 0x00}, //##Second_8bits_of_RAM1_Data +{0x87, 0x00}, //##Third_8bits_of_RAM1_data +{0x88, 0x00}, //##Fourth_8bits_of_RAM1_Data +{0x89, 0x00}, //##Fifth_8bits_of_RAM1_Data +{0x8A, 0x00}, //##RAM1_test_r/w_control +{0x8B, 0x00}, //##RAM2_test_register_address +{0x8C, 0x00}, //##First_4bits_of_RAM2_data +{0x8D, 0x00}, //##Second_8bits_of_RAM2_Data +{0x8E, 0x00}, //##Third_8bits_of_RAM2_data +{0x8F, 0x00}, //##Fourth_8bits_of_RAM2_Data +{0x90, 0x00}, //##Fifth_8bits_of_RAM2_Data +{0x91, 0x00}, //##RAM2_test_r/w_control +{0x92, 0x00}, //##BURN_EN1 +{0x93, 0x00}, //##BURN_EN2 +{0x94, 0x00}, //##OSC_TRIM_CTRL +{0x95, 0x80}, //##PLL_CTRL +{0x96, 0x11}, //##PLL_CTRL2 +{0x97, 0x06}, //##CLKDET_read_out1 +{0x98, 0x11}, //##CLKDET_read_out2 +{0x99, 0x02}, //##CLKDET_read_out3 +{0x9A, 0x56}, //##CLKDET_read_out4 +{0x9B, 0x90}, //##CLKDET_read_out5 +{0x9C, 0x3F}, //##CLKDET_read_out6 +{0x9D, 0x00}, //##CLKDET_read_out7 +{0x9E, 0x02}, //##CLKDET_read_out8 +{0x9F, 0x02}, //##RECOUNT_CTRL +{0xA0, 0xE4}, //##RECOUNT_STABLE_CTRL +{0xA1, 0x04}, //##Auto_clock_detect_FS96k_window +{0xA2, 0x04}, //##Auto_clock_detect_FS48k_window +{0xA3, 0x04}, //##Auto_clock_detect_FS16k_window +{0xA4, 0x04}, //##Auto_clock_detect_FS8k_window +{0xA5, 0x80}, //##SYNC_LR +}; + +static int m_ram1_tab[][5] = { +{0x00, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ1 +{0x01, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ1 +{0x02, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ1 +{0x03, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ1 +{0x04, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ1 +{0x05, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ2 +{0x06, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ2 +{0x07, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ2 +{0x08, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ2 +{0x09, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ2 +{0x0A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ3 +{0x0B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ3 +{0x0C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ3 +{0x0D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ3 +{0x0E, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ3 +{0x0F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ4 +{0x10, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ4 +{0x11, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ4 +{0x12, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ4 +{0x13, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ4 +{0x14, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ5 +{0x15, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ5 +{0x16, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ5 +{0x17, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ5 +{0x18, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ5 +{0x19, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ6 +{0x1A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ6 +{0x1B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ6 +{0x1C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ6 +{0x1D, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ6 +{0x1E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ7 +{0x1F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ7 +{0x20, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ7 +{0x21, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ7 +{0x22, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ7 +{0x23, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ8 +{0x24, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ8 +{0x25, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ8 +{0x26, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ8 +{0x27, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ8 +{0x28, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ9 +{0x29, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ9 +{0x2A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ9 +{0x2B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ9 +{0x2C, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ9 +{0x2D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ10 +{0x2E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ10 +{0x2F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ10 +{0x30, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ10 +{0x31, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ10 +{0x32, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ11 +{0x33, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ11 +{0x34, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ11 +{0x35, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ11 +{0x36, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ11 +{0x37, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ12 +{0x38, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ12 +{0x39, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ12 +{0x3A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ12 +{0x3B, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ12 +{0x3C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ13 +{0x3D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ13 +{0x3E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ13 +{0x3F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ13 +{0x40, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ13 +{0x41, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ14 +{0x42, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ14 +{0x43, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ14 +{0x44, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ14 +{0x45, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ14 +{0x46, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ15 +{0x47, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ15 +{0x48, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ15 +{0x49, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ15 +{0x4A, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ15 +{0x4B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ16 +{0x4C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ16 +{0x4D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ16 +{0x4E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ16 +{0x4F, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ16 +{0x50, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ17 +{0x51, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ17 +{0x52, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ17 +{0x53, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ17 +{0x54, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ17 +{0x55, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ18 +{0x56, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ18 +{0x57, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ18 +{0x58, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ18 +{0x59, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ18 +{0x5A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ19 +{0x5B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ19 +{0x5C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ19 +{0x5D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ19 +{0x5E, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ19 +{0x5F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ20 +{0x60, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ20 +{0x61, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ20 +{0x62, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ20 +{0x63, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ20 +{0x64, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ21 +{0x65, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ21 +{0x66, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ21 +{0x67, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ21 +{0x68, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ21 +{0x69, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ22 +{0x6A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ22 +{0x6B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ22 +{0x6C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ22 +{0x6D, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ22 +{0x6E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ23 +{0x6F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ23 +{0x70, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ23 +{0x71, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ23 +{0x72, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ23 +{0x73, 0x07, 0xFF, 0xFF, 0xFF}, //##Channel_1_Mixer1 +{0x74, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_Mixer2 +{0x75, 0x00, 0x7E, 0x88, 0xE0}, //##Channel_1_Prescale +{0x76, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_Postscale +{0x77, 0x02, 0x00, 0x00, 0x00}, //##CH1.2_Power_Clipping +{0x78, 0x00, 0x00, 0x01, 0xA0}, //####Noise_Gate_Attack_Level +{0x79, 0x00, 0x00, 0x05, 0x30}, //##Noise_Gate_Release_Level +{0x7A, 0x00, 0x01, 0x00, 0x00}, //##DRC1_Energy_Coefficient +{0x7B, 0x00, 0x01, 0x00, 0x00}, //##DRC2_Energy_Coefficient +{0x7C, 0x00, 0x01, 0x00, 0x00}, //##DRC3_Energy_Coefficient +{0x7D, 0x00, 0x01, 0x00, 0x00}, //##DRC4_Energy_Coefficient +{0x7E, 0x00, 0x00, 0x00, 0x00}, //##DRC1_Power_Meter +{0x7F, 0x00, 0x00, 0x00, 0x00}, //##DRC3_Power_Meter +{0x80, 0x00, 0x00, 0x00, 0x00}, //##DRC5_Power_Meter +{0x81, 0x00, 0x00, 0x00, 0x00}, //##DRC7_Power_Meter +{0x82, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN1 +{0x83, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN2 +{0x84, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN3 +{0x85, 0x0E, 0x01, 0xC0, 0x70}, //##DRC1_FF_threshold +{0x86, 0x02, 0x00, 0x00, 0x00}, //##DRC1_FF_slope +{0x87, 0x00, 0x00, 0x40, 0x00}, //##DRC1_FF_aa +{0x88, 0x00, 0x00, 0x40, 0x00}, //##DRC1_FF_da +{0x89, 0x0E, 0x01, 0xC0, 0x70}, //##DRC2_FF_threshold +{0x8A, 0x02, 0x00, 0x00, 0x00}, //##DRC2_FF_slope +{0x8B, 0x00, 0x00, 0x40, 0x00}, //##DRC2_FF_aa +{0x8C, 0x00, 0x00, 0x40, 0x00}, //##DRC2_FF_da +{0x8D, 0x0E, 0x01, 0xC0, 0x70}, //##DRC3_FF_threshold +{0x8E, 0x02, 0x00, 0x00, 0x00}, //##DRC3_FF_slope +{0x8F, 0x00, 0x00, 0x40, 0x00}, //##DRC3_FF_aa +{0x90, 0x00, 0x00, 0x40, 0x00}, //##DRC3_FF_da +{0x91, 0x0E, 0x01, 0xC0, 0x70}, //##DRC4_FF_threshold +{0x92, 0x02, 0x00, 0x00, 0x00}, //##DRC4_FF_slope +{0x93, 0x00, 0x00, 0x40, 0x00}, //##DRC4_FF_aa +{0x94, 0x00, 0x00, 0x40, 0x00}, //##DRC4_FF_da +{0x95, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x96, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x97, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x98, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x99, 0x00, 0x80, 0x00, 0x00}, //##I2SO_LCH_GAIN +{0x9A, 0x02, 0x00, 0x00, 0x00}, //##SRS_Gain +{0x9B, 0x01, 0xD7, 0xE6, 0xE0}, //##Compensate_A0 +{0x9C, 0x00, 0x2E, 0x77, 0x40}, //##Compensate_A1 +{0x9D, 0x0F, 0xF9, 0xA1, 0xE0}, //##Compensate_B1 +{0x9E, 0x01, 0x91, 0x2B, 0xE0}, //##QT_AT +{0x9F, 0x01, 0x1B, 0x5A, 0xB9}, //##QT_RT +{0xA0, 0x00, 0x5F, 0xCA, 0xCA}, //##QT_Region_T +{0xA1, 0x00, 0x00, 0x00, 0x00}, //##QT_Region_B +}; + +static int m_ram2_tab[][5] = { +{0x00, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ1 +{0x01, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ1 +{0x02, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ1 +{0x03, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ1 +{0x04, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ1 +{0x05, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ2 +{0x06, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ2 +{0x07, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ2 +{0x08, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ2 +{0x09, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ2 +{0x0A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ3 +{0x0B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ3 +{0x0C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ3 +{0x0D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ3 +{0x0E, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ3 +{0x0F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ4 +{0x10, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ4 +{0x11, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ4 +{0x12, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ4 +{0x13, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ4 +{0x14, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ5 +{0x15, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ5 +{0x16, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ5 +{0x17, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ5 +{0x18, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ5 +{0x19, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ6 +{0x1A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ6 +{0x1B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ6 +{0x1C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ6 +{0x1D, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ6 +{0x1E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ7 +{0x1F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ7 +{0x20, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ7 +{0x21, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ7 +{0x22, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ7 +{0x23, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ8 +{0x24, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ8 +{0x25, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ8 +{0x26, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ8 +{0x27, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ8 +{0x28, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ9 +{0x29, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ9 +{0x2A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ9 +{0x2B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ9 +{0x2C, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ9 +{0x2D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ10 +{0x2E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ10 +{0x2F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ10 +{0x30, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ10 +{0x31, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ10 +{0x32, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ11 +{0x33, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ11 +{0x34, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ11 +{0x35, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ11 +{0x36, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ11 +{0x37, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ12 +{0x38, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ12 +{0x39, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ12 +{0x3A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ12 +{0x3B, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ12 +{0x3C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ13 +{0x3D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ13 +{0x3E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ13 +{0x3F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ13 +{0x40, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ13 +{0x41, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ14 +{0x42, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ14 +{0x43, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ14 +{0x44, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ14 +{0x45, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ14 +{0x46, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ15 +{0x47, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ15 +{0x48, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ15 +{0x49, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ15 +{0x4A, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ15 +{0x4B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ16 +{0x4C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ16 +{0x4D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ16 +{0x4E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ16 +{0x4F, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ16 +{0x50, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ17 +{0x51, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ17 +{0x52, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ17 +{0x53, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ17 +{0x54, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ17 +{0x55, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ18 +{0x56, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ18 +{0x57, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ18 +{0x58, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ18 +{0x59, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ18 +{0x5A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ19 +{0x5B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ19 +{0x5C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ19 +{0x5D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ19 +{0x5E, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ19 +{0x5F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ20 +{0x60, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ20 +{0x61, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ20 +{0x62, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ20 +{0x63, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ20 +{0x64, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ21 +{0x65, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ21 +{0x66, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ21 +{0x67, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ21 +{0x68, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ21 +{0x69, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ22 +{0x6A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ22 +{0x6B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ22 +{0x6C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ22 +{0x6D, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ22 +{0x6E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ23 +{0x6F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ23 +{0x70, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ23 +{0x71, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ23 +{0x72, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ23 +{0x73, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_Mixer1 +{0x74, 0x07, 0xFF, 0xFF, 0xFF}, //##Channel_2_Mixer2 +{0x75, 0x00, 0x80, 0x00, 0x00}, //##Channel_2_Prescale +{0x76, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_Postscale +{0x77, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x78, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x79, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7A, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7B, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7C, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7D, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7E, 0x00, 0x00, 0x00, 0x00}, //##DRC2_Power_Meter +{0x7F, 0x00, 0x00, 0x00, 0x00}, //##DRC4_Power_Meter +{0x80, 0x00, 0x00, 0x00, 0x00}, //##DRC6_Power_Meter +{0x81, 0x00, 0x00, 0x00, 0x00}, //##DRC8_Power_Meter +{0x82, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN1 +{0x83, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN2 +{0x84, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN3 +{0x85, 0x00, 0x02, 0x00, 0x00}, //##DPEQ_Energy_Coefficient +{0x86, 0x0D, 0x2D, 0x26, 0x00}, //##DPEQ_UP_TH +{0x87, 0x0B, 0x83, 0xF1, 0x10}, //##DPEQ_Low_TH +{0x88, 0x00, 0x26, 0x87, 0xF0}, //##DBE_1_div_(Upper-Lower) +{0x89, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8A, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8B, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8C, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8D, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8E, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8F, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x90, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x91, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x92, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x93, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x94, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x95, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x96, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x97, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x98, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x99, 0x00, 0x80, 0x00, 0x00}, //##I2SO_RCH_GAIN +{0x9A, 0x00, 0x5A, 0x9D, 0xF0}, //##AGC_Attach_threshold +{0x9B, 0x00, 0x47, 0xFA, 0xD0}, //##AGC_Release_threshold +{0x9C, 0x00, 0x00, 0x08, 0x64}, //##AGC_AR_RR +{0x9D, 0x00, 0x00, 0x08, 0x64}, //##AGC_AT_RT +{0x9E, 0x00, 0x10, 0x00, 0x00}, //##AGC ALPHA +}; + +struct ad82120b_data { + int pd_gpio; + int CHIP_SYNC; + int CHIP_SYNC_lock; + int ASR_DET; + int ASR_DET_lock; + struct snd_soc_component *component; + struct regmap *regmap; + struct i2c_client *ad82120b_client; + enum ad82120b_type devtype; + struct delayed_work fault_check_work; + unsigned int last_fault; +#ifdef AD82120B_CHANGE_EQ_MODE_EN + unsigned int eq_mode; + unsigned char (*m_ram_tab)[5]; +#endif + struct gpio_desc *reset_pin_desc; +}; + +static int ad82120b_pd_gpio_set(struct snd_soc_component *component, bool enable) +{ + struct ad82120b_data *ad82120b = + snd_soc_component_get_drvdata(component); + if (!IS_ERR(ad82120b->reset_pin_desc)) { + if (enable) + gpiod_direction_output(ad82120b->reset_pin_desc, GPIOF_OUT_INIT_HIGH); + else + gpiod_direction_output(ad82120b->reset_pin_desc, GPIOF_OUT_INIT_LOW); + } + return 0; +} + +static int ad82120b_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + unsigned int rate = params_rate(params); + unsigned int ssz_ds; + int ret; + + pr_info("rate in amp is (%d)\n", rate); + switch (rate) { + case 44100: + case 48000: + ssz_ds = 0; + break; + case 88200: + case 96000: + ssz_ds = AD82120B_SSZ_DS; + break; + default: + dev_err(component->dev, "unsupported sample rate: %u\n", rate); + return -EINVAL; + } + + ad82120b_pd_gpio_set(component, true); // pull high amp PD pin + msleep(20); + + ret = snd_soc_component_update_bits(component, AD82120B_STATE_CTRL2_REG, + AD82120B_SSZ_DS, ssz_ds); + + if (ret < 0) { + dev_err(component->dev, "error setting sample rate: %d\n", ret); + return ret; + } + + return 0; +} + +static int ad82120b_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_component *component = dai->component; + u8 serial_format; + int ret; + + if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) { + dev_vdbg(component->dev, "DAI Format master is not found\n"); + return -EINVAL; + } + + switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | + SND_SOC_DAIFMT_INV_MASK)) { + case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): + /* 1st data bit occur one BCLK cycle after the frame sync */ + serial_format = AD82120B_SAIF_I2S; + break; + case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_NB_NF): + /* + * Note that although the AD82120B does not have a dedicated DSP + * mode it doesn't care about the LRCLK duty cycle during TDM + * operation. Therefore we can use the device's I2S mode with + * its delaying of the 1st data bit to receive DSP_A formatted + * data. See device datasheet for additional details. + */ + serial_format = AD82120B_SAIF_I2S; + break; + case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_NB_NF): + /* + * Similar to DSP_A, we can use the fact that the AD82120B does + * not care about the LRCLK duty cycle during TDM to receive + * DSP_B formatted data in LEFTJ mode (no delaying of the 1st + * data bit). + */ + serial_format = AD82120B_SAIF_LEFTJ; + break; + case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): + /* No delay after the frame sync */ + serial_format = AD82120B_SAIF_LEFTJ; + break; + default: + dev_vdbg(component->dev, "DAI Format is not found\n"); + return -EINVAL; + } + + ad82120b_pd_gpio_set(component, true); // pull high amp PD pin + msleep(20); + + ret = snd_soc_component_update_bits(component, AD82120B_STATE_CTRL1_REG, + AD82120B_SAIF_FORMAT_MASK, + serial_format); + if (ret < 0) { + dev_err(component->dev, "error setting SAIF format: %d\n", ret); + return ret; + } + + return 0; +} + +#ifdef AD82120B_CHANGE_EQ_MODE_EN +static int ad82120b_change_eq_mode(struct snd_soc_component *component, int channel) +{ + struct ad82120b_data *ad82120b = snd_soc_component_get_drvdata(component); + int eq_seg = 0; + int i = 0; + int cmd = 0; + + for (i = 0; i < 20; i++) { + // ram addr + regmap_write(ad82120b->regmap, 0x1d, ad82120b->m_ram_tab[eq_seg][0]); + + // write A1 + regmap_write(ad82120b->regmap, 0x1e, ad82120b->m_ram_tab[eq_seg][1]); + regmap_write(ad82120b->regmap, 0x1f, ad82120b->m_ram_tab[eq_seg][2]); + regmap_write(ad82120b->regmap, 0x20, ad82120b->m_ram_tab[eq_seg][3]); + regmap_write(ad82120b->regmap, 0x21, ad82120b->m_ram_tab[eq_seg][4]); + + eq_seg += 1; + // write A2 + regmap_write(ad82120b->regmap, 0x22, ad82120b->m_ram_tab[eq_seg][1]); + regmap_write(ad82120b->regmap, 0x23, ad82120b->m_ram_tab[eq_seg][2]); + regmap_write(ad82120b->regmap, 0x24, ad82120b->m_ram_tab[eq_seg][3]); + regmap_write(ad82120b->regmap, 0x25, ad82120b->m_ram_tab[eq_seg][4]); + + eq_seg += 1; + // write B1 + regmap_write(ad82120b->regmap, 0x26, ad82120b->m_ram_tab[eq_seg][1]); + regmap_write(ad82120b->regmap, 0x27, ad82120b->m_ram_tab[eq_seg][2]); + regmap_write(ad82120b->regmap, 0x28, ad82120b->m_ram_tab[eq_seg][3]); + regmap_write(ad82120b->regmap, 0x29, ad82120b->m_ram_tab[eq_seg][4]); + + eq_seg += 1; + // write B2 + regmap_write(ad82120b->regmap, 0x2a, ad82120b->m_ram_tab[eq_seg][1]); + regmap_write(ad82120b->regmap, 0x2b, ad82120b->m_ram_tab[eq_seg][2]); + regmap_write(ad82120b->regmap, 0x2c, ad82120b->m_ram_tab[eq_seg][3]); + regmap_write(ad82120b->regmap, 0x2d, ad82120b->m_ram_tab[eq_seg][4]); + eq_seg += 1; + // write A0 + regmap_write(ad82120b->regmap, 0x2e, ad82120b->m_ram_tab[eq_seg][1]); + regmap_write(ad82120b->regmap, 0x2f, ad82120b->m_ram_tab[eq_seg][2]); + regmap_write(ad82120b->regmap, 0x30, ad82120b->m_ram_tab[eq_seg][3]); + regmap_write(ad82120b->regmap, 0x31, ad82120b->m_ram_tab[eq_seg][4]); + + if (channel == 1) + cmd = 0x02; + else if (channel == 2) + cmd = 0x42; + regmap_write(ad82120b->regmap, 0x32, cmd); + + eq_seg += 1; + + if (eq_seg > 0x72) + break; + } + + for (eq_seg = 0x73; eq_seg < 0x9E; eq_seg++) { + if (eq_seg >= 0x7E && eq_seg <= 0x81) + continue; + + regmap_write(ad82120b->regmap, CFADDR, ad82120b->m_ram_tab[eq_seg][0]); + regmap_write(ad82120b->regmap, A1CF1, ad82120b->m_ram_tab[eq_seg][1]); + regmap_write(ad82120b->regmap, A1CF2, ad82120b->m_ram_tab[eq_seg][2]); + regmap_write(ad82120b->regmap, A1CF3, ad82120b->m_ram_tab[eq_seg][3]); + regmap_write(ad82120b->regmap, A1CF4, ad82120b->m_ram_tab[eq_seg][4]); + + if (channel == 1) + cmd = 0x01; + else if (channel == 2) + cmd = 0x41; + else + cmd = 0; + + regmap_write(ad82120b->regmap, CFUD, cmd); + } + + return 0; +} + +static int ad82120b_eq_mode_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->access = (SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE); + uinfo->count = 1; + + uinfo->value.integer.min = AD82120B_EQ_MODE_MIN; + uinfo->value.integer.max = AD82120B_EQ_MODE_MAX; + uinfo->value.integer.step = 1; + + return 0; +} + +static int ad82120b_eq_mode_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct ad82120b_data *ad82120b = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = ad82120b->eq_mode; + + return 0; +} + +static int ad82120b_eq_mode_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct ad82120b_data *ad82120b = snd_soc_component_get_drvdata(component); + int id_reg = 0xff; + + if (ucontrol->value.integer.value[0] > AD82120B_EQ_MODE_MAX || + ucontrol->value.integer.value[0] < AD82120B_EQ_MODE_MIN) { + dev_err(component->dev, "error mode value setting, please check!\n"); + return -1; + } + + ad82120b_pd_gpio_set(component, true); // pull high amp PD pin + msleep(20); + + regmap_read(ad82120b->regmap, AD82120B_DEVICE_ID_REG, &id_reg); + if (id_reg & 0xf0 != AD82120B_DEVICE_ID) { + dev_err(component->dev, "error device id 0x%02x, please check!\n", id_reg); + return -1; + } + + ad82120b->eq_mode = ucontrol->value.integer.value[0]; + + pr_info("change ad82120b eq mode = %d\n", ad82120b->eq_mode); + + if (ad82120b->eq_mode == 1) { + ad82120b->m_ram_tab = eq_mode_1_ram1_tab; + ad82120b_change_eq_mode(component, 1); + #ifdef CONFIG_SND_SOC_AD82120B_2CHANNEL + ad82120b->m_ram_tab = eq_mode_1_ram2_tab; + ad82120b_change_eq_mode(component, 2); + #endif + } + if (ad82120b->eq_mode == 2) { + ad82120b->m_ram_tab = eq_mode_2_ram1_tab; + ad82120b_change_eq_mode(component, 1); + #ifdef CONFIG_SND_SOC_AD82120B_2CHANNEL + ad82120b->m_ram_tab = eq_mode_2_ram2_tab; + ad82120b_change_eq_mode(component, 2); + #endif + } + + // add your other eq mode here + // ... + + return 0; +} + +static const struct snd_kcontrol_new ad82120b_eq_mode_control[] = { + { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "AD82120B EQ Mode", // Just fake the name + .info = ad82120b_eq_mode_info, + .get = ad82120b_eq_mode_get, + .put = ad82120b_eq_mode_put, + }, +}; +#endif + +static int ad82120b_mute(struct snd_soc_dai *dai, int mute, int stream) +{ + struct snd_soc_component *component = dai->component; + int ret = 0; + + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { + ret = snd_soc_component_update_bits(component, AD82120B_STATE_CTRL3_REG, + AD82120B_MUTE, mute ? AD82120B_MUTE : 0); + if (ret < 0) { + dev_err(component->dev, "error (un-)muting device: %d\n", ret); + return ret; + } + } + + return ret; +} + +static void ad82120b_fault_check_work(struct work_struct *work) +{ + struct ad82120b_data *ad82120b = container_of(work, struct ad82120b_data, + fault_check_work.work); + struct device *dev = ad82120b->component->dev; + unsigned int curr_fault; + int ret = 0; + + // if CHIP SYNC is enable at initialization, (enable-> delay 200us -> disable) + //it again Whenever i2s clk on, + // both BCLK and LRCK are required to be simultaneously and stably supplied to the AMP. + if (ad82120b->CHIP_SYNC == 1 && ad82120b->CHIP_SYNC_lock == 0) { + /* Set CHIP SYNC to enable */ + snd_soc_component_update_bits(ad82120b->component, AD82120B_STATE_CTRL4_REG, + AD82120B_CHIP_SYNC_EN, AD82120B_CHIP_SYNC_EN); + + usleep_range(1000, 2000); + /* Set CHIP SYNC to disable */ + snd_soc_component_update_bits(ad82120b->component, AD82120B_STATE_CTRL4_REG, + AD82120B_CHIP_SYNC_EN, 0); + + ad82120b->CHIP_SYNC_lock = 1; + } + + // Force Auto sample rate detection function to turn off during initialization, + //and now turn it on(I2S clock is out). + if (ad82120b->ASR_DET != 0 && ad82120b->ASR_DET_lock == 0) { + regmap_write(ad82120b->regmap, AD82120B_CLK_DET_CTRL, ad82120b->ASR_DET); + ad82120b->ASR_DET_lock = 1; + } + + // amp fault check + ret = regmap_read(ad82120b->regmap, AD82120B_FAULT_REG, &curr_fault); + if (ret < 0) { + dev_err(dev, "failed to read FAULT register: %d\n", ret); + goto out; + } + + /* Check/handle all errors except SAIF clock errors */ + curr_fault &= AD82120B_OCE | AD82120B_DCDE | AD82120B_OTE | + AD82120B_UVE | AD82120B_BSUVE | AD82120B_OVPE; + + /* + * Only flag errors once for a given occurrence. This is needed as + * the AD82120B will take time clearing the fault condition internally + * during which we don't want to bombard the system with the same + * error message over and over. + */ + if (!(curr_fault & AD82120B_OCE) && (ad82120b->last_fault & AD82120B_OCE)) + dev_crit(dev, "experienced an over current hardware fault\n"); + + if (!(curr_fault & AD82120B_DCDE) && (ad82120b->last_fault & AD82120B_DCDE)) + dev_crit(dev, "experienced an DCD detection fault\n"); + + if (!(curr_fault & AD82120B_OTE) && (ad82120b->last_fault & AD82120B_OTE)) + dev_crit(dev, "experienced an over temperature fault\n"); + + if (!(curr_fault & AD82120B_UVE) && (ad82120b->last_fault & AD82120B_UVE)) + dev_crit(dev, "experienced an UV fault\n"); + + if (!(curr_fault & AD82120B_BSUVE) && (ad82120b->last_fault & AD82120B_BSUVE)) + dev_crit(dev, "experienced an BSUV fault\n"); + + if (!(curr_fault & AD82120B_OVPE) && (ad82120b->last_fault & AD82120B_OVPE)) + dev_crit(dev, "experienced an OVP fault\n"); + /* Store current fault value so we can detect any changes next time */ + ad82120b->last_fault = curr_fault; + + if (curr_fault == (AD82120B_OCE | AD82120B_DCDE | AD82120B_OTE | + AD82120B_UVE | AD82120B_BSUVE | AD82120B_OVPE)) + goto out; + + /* + * Periodically toggle SDZ (shutdown bit) H->L->H to clear any latching + * faults as long as a fault condition persists. Always going through + * the full sequence no matter the first return value to minimizes + * chances for the device to end up in shutdown mode. + */ + dev_crit(dev, "toggle pd pin H->L->H to clear latching faults\n"); + + ad82120b_pd_gpio_set(ad82120b->component, false); // pull low amp PD pin + msleep(20); + ad82120b_pd_gpio_set(ad82120b->component, true); // pull high amp PD pin + +out: + /* Schedule the next fault check at the specified interval */ + schedule_delayed_work(&ad82120b->fault_check_work, + msecs_to_jiffies(AD82120B_FAULT_CHECK_INTERVAL)); +} + +static int ad82120b_reg_ram_init(struct snd_soc_component *component) +{ + struct ad82120b_data *ad82120b = snd_soc_component_get_drvdata(component); + int ret; + int i; + int reg_data; + + pr_info("ad82120b i2c address = %p, %s!\n", component, __func__); + + ad82120b_pd_gpio_set(component, true); // pull high amp PD pin + + msleep(45); + + // software reset amp + ret = snd_soc_component_update_bits(component, AD82120B_STATE_CTRL5_REG, + AD82120B_SW_RESET, 0); + if (ret < 0) + goto error_snd_soc_component_update_reg; + + usleep_range(5000, 6000); + + ret = snd_soc_component_update_bits(component, AD82120B_STATE_CTRL5_REG, + AD82120B_SW_RESET, AD82120B_SW_RESET); + if (ret < 0) + goto error_snd_soc_component_update_reg; + + msleep(20); // wait 20ms + + /* Set device to mute */ + ret = snd_soc_component_update_bits(component, AD82120B_STATE_CTRL3_REG, + AD82120B_MUTE, AD82120B_MUTE); + if (ret < 0) + goto error_snd_soc_component_update_reg; + + // Write register table + for (i = 0; i < AD82120B_REGISTER_COUNT; i++) { + reg_data = m_reg_tab[i][1]; + + if (m_reg_tab[i][0] == 0x02) + continue; + + // set stereo + if (m_reg_tab[i][0] == 0x1A) + reg_data &= (~0x40); // mono_en = 0 + if (m_reg_tab[i][0] == 0x5B) + reg_data = 0x00; + if (m_reg_tab[i][0] == 0x5C) + reg_data = 0x00; + // set stereo end + + // check if CHIP SYNC enable ? + if (m_reg_tab[i][0] == AD82120B_STATE_CTRL4_REG) { + if ((reg_data & AD82120B_CHIP_SYNC_EN) == AD82120B_CHIP_SYNC_EN) { + ad82120b->CHIP_SYNC = 1; + pr_info("ad82120b chip sync enable!\n"); + } else { + ad82120b->CHIP_SYNC = 0; + } + } + + // check if Auto sample rate detection enable ? + ad82120b->ASR_DET_lock = 0; + if (m_reg_tab[i][0] == AD82120B_CLK_DET_CTRL) { + if ((reg_data & AD82120B_ASR_DET) == AD82120B_ASR_DET) { + ad82120b->ASR_DET = reg_data; + pr_info("ad82120b Auto sample rate detection enable!\n"); + reg_data = 0x10; + } else { + ad82120b->ASR_DET = 0; + } + } + + ret = regmap_write(ad82120b->regmap, m_reg_tab[i][0], reg_data); + if (ret < 0) + goto error_snd_soc_component_update_reg; + } + + // Write ram1 + for (i = 0; i < AD82120B_RAM1_TABLE_COUNT; i++) { + regmap_write(ad82120b->regmap, CFADDR, m_ram1_tab[i][0]); + regmap_write(ad82120b->regmap, A1CF1, m_ram1_tab[i][1]); + regmap_write(ad82120b->regmap, A1CF2, m_ram1_tab[i][2]); + regmap_write(ad82120b->regmap, A1CF3, m_ram1_tab[i][3]); + regmap_write(ad82120b->regmap, A1CF4, m_ram1_tab[i][4]); + regmap_write(ad82120b->regmap, CFUD, 0x01); + } + // Write ram2 + for (i = 0; i < AD82120B_RAM2_TABLE_COUNT; i++) { + regmap_write(ad82120b->regmap, CFADDR, m_ram2_tab[i][0]); + regmap_write(ad82120b->regmap, A1CF1, m_ram2_tab[i][1]); + regmap_write(ad82120b->regmap, A1CF2, m_ram2_tab[i][2]); + regmap_write(ad82120b->regmap, A1CF3, m_ram2_tab[i][3]); + regmap_write(ad82120b->regmap, A1CF4, m_ram2_tab[i][4]); + regmap_write(ad82120b->regmap, CFUD, 0x41); + } + return 0; + +error_snd_soc_component_update_reg: + dev_err(component->dev, "error init device registers: %d\n", ret); + + return ret; +} + +static int ad82120b_codec_probe(struct snd_soc_component *component) +{ + struct ad82120b_data *ad82120b = snd_soc_component_get_drvdata(component); + //unsigned int device_id, expected_device_id; + int ret; +#ifdef AD82120B_REG_RAM_CHECK + int i; + int reg_data; + int ram_h8_data; + int ram_m8_data; + int ram_l8_data; + int ram_ll8_data; +#endif + ad82120b->component = component; + + pr_info("ad82120b i2c address = %p, %s!\n", component, __func__); + + ret = ad82120b_reg_ram_init(component); + if (ret < 0) + goto error_snd_soc_component_update_bits; + + usleep_range(2000, 3000); + + // if CHIP SYNC is enable, need disable it before unmute + if (ad82120b->CHIP_SYNC == 1) { + /* Set CHIP SYNC to disable */ + ret = snd_soc_component_update_bits(component, AD82120B_STATE_CTRL4_REG, + AD82120B_CHIP_SYNC_EN, 0); + + ad82120b->CHIP_SYNC_lock = 0; + } + + /* Set device to unmute */ + ret = snd_soc_component_update_bits(component, AD82120B_STATE_CTRL3_REG, + AD82120B_MUTE, 0); + if (ret < 0) + goto error_snd_soc_component_update_bits; + + INIT_DELAYED_WORK(&ad82120b->fault_check_work, ad82120b_fault_check_work); + +#ifdef AD82120B_CHANGE_EQ_MODE_EN + ret = snd_soc_add_component_controls(component, ad82120b_eq_mode_control, 1); + if (ret != 0) + pr_info("Failed to register ad82120b_eq_mode_control (%d)\n", ret); +#endif + +#ifdef AD82120B_REG_RAM_CHECK + + msleep(1000); + + for (i = 0; i < AD82120B_REGISTER_COUNT; i++) { + regmap_read(ad82120b->regmap, m_reg_tab[i][0], ®_data); + pr_info("register addr, data 0x%02x, 0x%02x\n", m_reg_tab[i][0], reg_data); + } + + for (i = 0; i < AD82120B_RAM1_TABLE_COUNT; i++) { + regmap_write(ad82120b->regmap, CFADDR, m_ram1_tab[i][0]); + regmap_write(ad82120b->regmap, CFUD, 0x04); + + regmap_read(ad82120b->regmap, A1CF1, &ram_h8_data); + regmap_read(ad82120b->regmap, A1CF2, &ram_m8_data); + regmap_read(ad82120b->regmap, A1CF3, &ram_l8_data); + regmap_read(ad82120b->regmap, A1CF4, &ram_ll8_data); + //pr_info("ram1 {addr, H8, M8, L8, LL8} = + // {0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x}\n", + // m_ram1_tab[i][0], ram_h8_data, + // ram_m8_data, ram_l8_data, ram_ll8_data); + } +#endif + + return 0; + +error_snd_soc_component_update_bits: + dev_err(component->dev, "error configuring device registers: %d\n", ret); + + return ret; +} + +static void ad82120b_codec_remove(struct snd_soc_component *component) +{ + struct ad82120b_data *ad82120b = snd_soc_component_get_drvdata(component); + + cancel_delayed_work_sync(&ad82120b->fault_check_work); + ad82120b->CHIP_SYNC_lock = 0; + ad82120b->ASR_DET_lock = 0; +}; + +static int ad82120b_dac_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + int ret; + struct ad82120b_data *ad82120b = snd_soc_component_get_drvdata(component); + + if (event & SND_SOC_DAPM_POST_PMU) { + pr_info("ad82120b dac event post PMU.\n"); + /* Take AD82120B out of shutdown mode */ + ad82120b_pd_gpio_set(component, true);// pull high amp PD pin + + /* + * Observe codec shutdown-to-active time. The datasheet only + * lists a nominal value however just use-it as-is without + * additional padding to minimize the delay introduced in + * starting to play audio (actually there is other setup done + * by the ASoC framework that will provide additional delays, + * so we should always be safe). + */ + msleep(20); + ret = snd_soc_component_update_bits(component, AD82120B_STATE_CTRL3_REG, + AD82120B_MUTE, 0); + if (ret < 0) + dev_err(component->dev, "failed to write MUTE register: %d\n", ret); + + /* Turn on AD82120B periodic fault checking/handling */ + ad82120b->last_fault = 0xFF; + schedule_delayed_work(&ad82120b->fault_check_work, + msecs_to_jiffies(AD82120B_FAULT_CHECK_INTERVAL)); + } else if (event & SND_SOC_DAPM_PRE_PMD) { + pr_info("ad82120b dac event pre PMD.\n"); + /* Disable AD82120B periodic fault checking/handling */ + cancel_delayed_work_sync(&ad82120b->fault_check_work); + + // clear amp sync lock + ad82120b->CHIP_SYNC_lock = 0; + // disable ASR_DET function and clear lock before I2S clk stop + if (ad82120b->ASR_DET != 0) + regmap_write(ad82120b->regmap, AD82120B_CLK_DET_CTRL, 0x10); + ad82120b->ASR_DET_lock = 0; + + /* Place AD82120B in shutdown mode to minimize current draw */ + ret = snd_soc_component_update_bits(component, AD82120B_STATE_CTRL3_REG, + AD82120B_MUTE, AD82120B_MUTE); + if (ret < 0) + dev_err(component->dev, "failed to write MUTE register: %d\n", ret); + + msleep(20); + + ad82120b_pd_gpio_set(component, false); // pull low amp PD pin + } + + return 0; +} + +#ifdef CONFIG_PM +static int ad82120b_suspend(struct snd_soc_component *component) +{ + pr_info("ad82120b suspend.\n"); + + //regcache_cache_only(ad82120b->regmap, true); + //regcache_mark_dirty(ad82120b->regmap); + return 0; +} + +static int ad82120b_resume(struct snd_soc_component *component) +{ + int ret; + + pr_info("ad82120b resume.\n"); + + //regcache_cache_only(ad82120b->regmap, false); + + //ret = regcache_sync(ad82120b->regmap); + //if (ret < 0) { + // dev_err(component->dev, "failed to sync regcache: %d\n", ret); + // return ret; + //} + + msleep(20); + + ret = ad82120b_reg_ram_init(component); + if (ret < 0) + goto resume_error_snd_soc_component_update_bits; + + return 0; + +resume_error_snd_soc_component_update_bits: + dev_err(component->dev, "resume error configuring device registers: %d\n", ret); + + return ret; +} +#else +#define ad82120b_suspend NULL +#define ad82120b_resume NULL +#endif + +static bool ad82120b_is_volatile_reg(struct device *dev, unsigned int reg) +{ +#ifdef AD82120B_REG_RAM_CHECK + if (reg <= AD82120B_MAX_REG) + return true; + else + return false; +#else + switch (reg) { + case AD82120B_FAULT_REG: + case AD82120B_STATE_CTRL1_REG: + case AD82120B_STATE_CTRL2_REG: + case AD82120B_STATE_CTRL3_REG: + case AD82120B_STATE_CTRL5_REG: + case AD82120B_DEVICE_ID_REG: + return true; + default: + return false; + } +#endif +} + +static const struct regmap_config ad82120b_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = AD82120B_MAX_REG, + + //.reg_defaults = m_reg_tab, + // + .cache_type = REGCACHE_RBTREE, + .volatile_reg = ad82120b_is_volatile_reg, +}; + +/* + * DAC digital volumes. From -103.5 to 24 dB in 0.5 dB steps. Note that + * setting the gain below -100 dB (register value <0x7) is effectively a MUTE + * as per device datasheet. + */ +static DECLARE_TLV_DB_SCALE(dac_tlv, -10350, 50, 0); + +static const struct snd_kcontrol_new ad82120b_snd_controls[] = { + SOC_SINGLE_TLV("Speaker Driver Playback Volume", + AD82120B_VOLUME_CTRL_REG, 0, 0xff, 0, dac_tlv), +}; + +static const struct snd_soc_dapm_widget ad82120b_dapm_widgets[] = { + SND_SOC_DAPM_AIF_IN("DAC IN", "Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0, ad82120b_dac_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_OUTPUT("OUT") +}; + +static const struct snd_soc_dapm_route ad82120b_audio_map[] = { + { "DAC", NULL, "DAC IN" }, + { "OUT", NULL, "DAC" }, +}; + +static const struct snd_soc_component_driver soc_component_dev_ad82120b = { + .probe = ad82120b_codec_probe, + .remove = ad82120b_codec_remove, + .suspend = ad82120b_suspend, + .resume = ad82120b_resume, + .controls = ad82120b_snd_controls, + .num_controls = ARRAY_SIZE(ad82120b_snd_controls), + .dapm_widgets = ad82120b_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(ad82120b_dapm_widgets), + .dapm_routes = ad82120b_audio_map, + .num_dapm_routes = ARRAY_SIZE(ad82120b_audio_map), + .idle_bias_on = 1, + .use_pmdown_time = 1, + .endianness = 1, + .non_legacy_dai_naming = 1, +}; + +/* PCM rates supported by the AD82120B driver */ +#define AD82120B_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) + +#define AD82120B_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S20_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static const struct snd_soc_dai_ops ad82120b_speaker_dai_ops = { + .hw_params = ad82120b_hw_params, + .set_fmt = ad82120b_set_dai_fmt, + .mute_stream = ad82120b_mute, + .no_capture_mute = 1, +}; + +/* + * AD82120B DAI structure + * + * Note that were are advertising .playback.channels_max = 2 despite this being + * a mono amplifier. The reason for that is that some serial ports such as ESMT's + * McASP module have a minimum number of channels (2) that they can output. + * Advertising more channels than we have will allow us to interface with such + * a serial port without really any negative side effects as the AD82120B will + * simply ignore any extra channel(s) asides from the one channel that is + * configured to be played back. + */ +static struct snd_soc_dai_driver ad82120b_dai[] = { + { + .name = "ad82120b", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = AD82120B_RATES, + .formats = AD82120B_FORMATS, + }, + .ops = &ad82120b_speaker_dai_ops, + }, +}; + +static int ad82120b_parse_dt(struct ad82120b_data *ad82120b, struct device *dev) +{ + ad82120b->reset_pin_desc = gpiod_get(dev, "reset_pin", GPIOF_OUT_INIT_LOW); + if (!IS_ERR(ad82120b->reset_pin_desc)) { + gpiod_direction_output(ad82120b->reset_pin_desc, GPIOF_OUT_INIT_HIGH); + pr_info("%s,av out status: %s\n", + __func__, + gpiod_get_value(ad82120b->reset_pin_desc) ? + "high" : "low"); + } + + return 0; +} + +static int ad82120b_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct ad82120b_data *data; + const struct regmap_config *regmap_config; + int ret; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->ad82120b_client = client; + data->devtype = id->driver_data; + + switch (id->driver_data) { + case AD82120B: + regmap_config = &ad82120b_regmap_config; + break; + default: + dev_err(dev, "unexpected private driver data\n"); + return -EINVAL; + } + data->regmap = devm_regmap_init_i2c(client, regmap_config); + if (IS_ERR(data->regmap)) { + ret = PTR_ERR(data->regmap); + dev_err(dev, "failed to allocate register map: %d\n", ret); + return ret; + } + dev_set_drvdata(dev, data); + + ad82120b_parse_dt(data, &client->dev); + + ret = devm_snd_soc_register_component(&client->dev, + &soc_component_dev_ad82120b, + ad82120b_dai, ARRAY_SIZE(ad82120b_dai)); + if (ret < 0) { + dev_err(dev, "failed to register component: %d\n", ret); + return ret; + } + pr_info("load %s ok\n", __func__); + return 0; +} + +static const struct i2c_device_id ad82120b_id[] = { + { "ad82120b", AD82120B }, + { } +}; +MODULE_DEVICE_TABLE(i2c, ad82120b_id); + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id ad82120b_of_match[] = { + { .compatible = "ESMT,ad82120b", }, + { }, +}; +MODULE_DEVICE_TABLE(of, ad82120b_of_match); +#endif + +static struct i2c_driver ad82120b_i2c_driver = { + .driver = { + .name = "ad82120b", + .of_match_table = of_match_ptr(ad82120b_of_match), + }, + .probe = ad82120b_probe, + .id_table = ad82120b_id, +}; + +module_i2c_driver(ad82120b_i2c_driver); + +MODULE_AUTHOR("ESMT BU2"); +MODULE_DESCRIPTION("AD82120B Audio amplifier driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/amlogic/ad82120b.h b/sound/soc/codecs/amlogic/ad82120b.h new file mode 100644 index 000000000..3f490246d --- /dev/null +++ b/sound/soc/codecs/amlogic/ad82120b.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AD82120B_H__ +#define __AD82120B_H__ + +#define AD82120B_REGISTER_COUNT 166 +#define AD82120B_RAM1_TABLE_COUNT 162 +#define AD82120B_RAM2_TABLE_COUNT 159 +/* Register Address Map */ +#define AD82120B_STATE_CTRL1_REG 0x00 +#define AD82120B_STATE_CTRL2_REG 0x01 +#define AD82120B_STATE_CTRL3_REG 0x02 +#define AD82120B_VOLUME_CTRL_REG 0x03 +#define AD82120B_STATE_CTRL4_REG 0x0C +#define AD82120B_STATE_CTRL5_REG 0x1A + +#define CFADDR 0x1d +#define A1CF1 0x1e +#define A1CF2 0x1f +#define A1CF3 0x20 +#define A1CF4 0x21 +#define CFUD 0x32 + +#define AD82120B_DEVICE_ID_REG 0x37 + +#define AD82120B_CLK_DET_CTRL 0x56 + +#define AD82120B_FAULT_REG 0x4D +#define AD82120B_MAX_REG 0xA5 + +/* AD82120B_STATE_CTRL2_REG */ +#define AD82120B_SSZ_DS BIT(5) + +/* AD82120B_STATE_CTRL1_REG */ +#define AD82120B_SAIF_I2S (0x0 << 5) +#define AD82120B_SAIF_LEFTJ (0x1 << 5) +#define AD82120B_SAIF_FORMAT_MASK GENMASK(7, 5) + +/* AD82120B_STATE_CTRL3_REG */ +#define AD82120B_MUTE BIT(6) + +/* AD82120B_STATE_CTRL5_REG */ +#define AD82120B_SW_RESET BIT(5) + +/* AD82120B_CLK_DET_CTRL */ +#define AD82120B_ASR_DET BIT(7) + +/* AD82120B_DEVICE_ID_REG */ +#define AD82120B_DEVICE_ID 0xA0 + +/* AD82120B_STATE_CTRL4_REG */ +#define AD82120B_CHIP_SYNC_EN BIT(1) + +/* AD82120B_FAULT_REG */ +#define AD82120B_OCE BIT(7) +#define AD82120B_OTE BIT(6) +#define AD82120B_UVE BIT(5) +#define AD82120B_DCDE BIT(4) +#define AD82120B_BSUVE BIT(3) +#define AD82120B_CLKE BIT(2) +#define AD82120B_OVPE BIT(1) +#define AD82120B_D_CLKE BIT(0) +#endif /* __AD82120B_H__ */ diff --git a/sound/soc/codecs/amlogic/ad82120b_eq/ad82120b_eq_mode_1.h b/sound/soc/codecs/amlogic/ad82120b_eq/ad82120b_eq_mode_1.h new file mode 100644 index 000000000..2e4fe71be --- /dev/null +++ b/sound/soc/codecs/amlogic/ad82120b_eq/ad82120b_eq_mode_1.h @@ -0,0 +1,510 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#if DEBUG_0 +static unsigned char eq_mode_1_reg_tab[AD82120B_REGISTER_COUNT][2] = { +{0x00, 0x00}, //##State_Control_1 +{0x01, 0x82}, //##State_Control_2 +{0x02, 0x00}, //##State_Control_3 +{0x03, 0x40}, //##Master_volume_control +{0x04, 0x18}, //##Channel_1_volume_control +{0x05, 0x18}, //##Channel_2_volume_control +{0x06, 0x18}, //##Channel_3_volume_control +{0x07, 0x18}, //##Channel_4_volume_control +{0x08, 0x18}, //##Channel_5_volume_control +{0x09, 0x18}, //##Channel_6_volume_control +{0x0A, 0x40}, //##DTC_Setting +{0x0B, 0x00}, //##Reserve +{0x0C, 0x90}, //##State_Control_4 +{0x0D, 0x80}, //##Channel_1_configuration_registers +{0x0E, 0x80}, //##Channel_2_configuration_registers +{0x0F, 0x80}, //##Channel_3_configuration_registers +{0x10, 0x80}, //##Channel_4_configuration_registers +{0x11, 0x80}, //##Channel_5_configuration_registers +{0x12, 0x80}, //##Channel_6_configuration_registers +{0x13, 0x80}, //##Channel_7_configuration_registers +{0x14, 0x80}, //##Channel_8_configuration_registers +{0x15, 0x00}, //##Reserve +{0x16, 0x00}, //##Reserve +{0x17, 0x00}, //##Reserve +{0x18, 0x00}, //##Reserve +{0x19, 0x80}, //##Reserve +{0x1A, 0x28}, //##State_Control_5 +{0x1B, 0x80}, //##State_Control_6 +{0x1C, 0x20}, //##State_Control_7 +{0x1D, 0x00}, //##Coefficient_RAM_Base_Address +{0x1E, 0x00}, //##First_4-bits_of_coefficients_A1 +{0x1F, 0x00}, //##Second_8-bits_of_coefficients_A1 +{0x20, 0x00}, //##Third_8-bits_of_coefficients_A1 +{0x21, 0x00}, //##Fourth-bits_of_coefficients_A1 +{0x22, 0x00}, //##First_4-bits_of_coefficients_A2 +{0x23, 0x00}, //##Second_8-bits_of_coefficients_A2 +{0x24, 0x00}, //##Third_8-bits_of_coefficients_A2 +{0x25, 0x00}, //##Fourth_8-bits_of_coefficients_A2 +{0x26, 0x00}, //##First_4-bits_of_coefficients_B1 +{0x27, 0x00}, //##Second_8-bits_of_coefficients_B1 +{0x28, 0x00}, //##Third_8-bits_of_coefficients_B1 +{0x29, 0x00}, //##Fourth_8-bits_of_coefficients_B1 +{0x2A, 0x00}, //##First_4-bits_of_coefficients_B2 +{0x2B, 0x00}, //##Second_8-bits_of_coefficients_B2 +{0x2C, 0x00}, //##Third_8-bits_of_coefficients_B2 +{0x2D, 0x00}, //##Fourth-bits_of_coefficients_B2 +{0x2E, 0x00}, //##First_4-bits_of_coefficients_A0 +{0x2F, 0x80}, //##Second_8-bits_of_coefficients_A0 +{0x30, 0x00}, //##Third_8-bits_of_coefficients_A0 +{0x31, 0x00}, //##Fourth_8-bits_of_coefficients_A0 +{0x32, 0x00}, //##Coefficient_RAM_R/W_control +{0x33, 0x02}, //##State_Control_8 +{0x34, 0x00}, //##Reserve +{0x35, 0x00}, //##Volume_Fine_tune +{0x36, 0x00}, //##Volume_Fine_tune +{0x37, 0xA0}, //##Device_ID_register +{0x38, 0x00}, //##Level_Meter_Clear +{0x39, 0x00}, //##Power_Meter_Clear +{0x3A, 0x00}, //##First_8bits_of_C1_Level_Meter +{0x3B, 0x00}, //##Second_8bits_of_C1_Level_Meter +{0x3C, 0x00}, //##Third_8bits_of_C1_Level_Meter +{0x3D, 0x00}, //##Fourth_8bits_of_C1_Level_Meter +{0x3E, 0x00}, //##First_8bits_of_C2_Level_Meter +{0x3F, 0x00}, //##Second_8bits_of_C2_Level_Meter +{0x40, 0x00}, //##Third_8bits_of_C2_Level_Meter +{0x41, 0x00}, //##Fourth_8bits_of_C2_Level_Meter +{0x42, 0x00}, //##CHK_stat +{0x43, 0x00}, //##First_4_bits_of_BEQ_CHK_val +{0x44, 0x00}, //##Second_8_bits_of_BEQ_CHK_val +{0x45, 0x00}, //##Third_4_bits_of_BEQ_CHK_val +{0x46, 0x00}, //##Bottom_4_bits_of_BEQ_CHK_val +{0x47, 0x00}, //##First_4_bits_of_BEQ_CHK_result +{0x48, 0x00}, //##Second_4_bits_of_BEQ_CHK_result +{0x49, 0x00}, //##Third_4_bits_of_BEQ_CHK_result +{0x4A, 0x00}, //##Bottom_4_bits_of_BEQ_CHK_result +{0x4B, 0x10}, //##digital_DC_control +{0x4C, 0x20}, //##digital_DC_judge_threshold +{0x4D, 0xFF}, //##ERROR_register +{0x4E, 0xFF}, //##ERROR_latch_register +{0x4F, 0x00}, //##ERROR_clear_register +{0x50, 0x01}, //##ERROR_register_2 +{0x51, 0x01}, //##ERROR_latch_register_2 +{0x52, 0x00}, //##ERROR_clear_register_2 +{0x53, 0x00}, //##Reserve +{0x54, 0x00}, //##Reserve +{0x55, 0x20}, //##clock_FS_detection +{0x56, 0x10}, //##CLK_DET +{0x57, 0x00}, //##TDM_word_width_selection +{0x58, 0x00}, //##TDM_offset +{0x59, 0x06}, //##I2S_Data_output_selection_register +{0x5A, 0x08}, //##PWM_frequency_selection +{0x5B, 0x00}, //##Mono_Key_High_Byte +{0x5C, 0x00}, //##Mono_Key_Low_Byte +{0x5D, 0x07}, //##Hi-res_Item +{0x5E, 0x00}, //##analog_gain +{0x5F, 0x00}, //##AGC_Control +{0x60, 0x00}, //##Channel1_EQ_bypass_1 +{0x61, 0x00}, //##Channel1_EQ_bypass_2 +{0x62, 0x00}, //##Channel1_EQ_bypass_3 +{0x63, 0x00}, //##Channel2_EQ_bypass_1 +{0x64, 0x00}, //##Channel2_EQ_bypass_2 +{0x65, 0x00}, //##Channel2_EQ_bypass_3 +{0x66, 0x00}, //##ATTACK_HOLD_SET +{0x67, 0x00}, //##Reserve +{0x68, 0x00}, //##Reserve +{0x69, 0x00}, //##Reserve +{0x6A, 0x00}, //##Reserve +{0x6B, 0x00}, //##Reserve +{0x6C, 0x02}, //##FS_and_PMF_read_out +{0x6D, 0x03}, //##OC_Selection +{0x6E, 0x00}, //##digital_DC_control_testmode +{0x6F, 0x32}, //##test_mode_register0 +{0x70, 0x07}, //##noise_gate_analog_gain +{0x71, 0x41}, //##Testmode_register1 +{0x72, 0x38}, //##Testmode_register2 +{0x73, 0x18}, //##dither_signal_setting +{0x74, 0x0D}, //##Error_Delay +{0x75, 0x05}, //##First_4bits_of_MBIST_User_Program_Even +{0x76, 0x55}, //##Second_8bits_of_MBIST_User_Program_Even +{0x77, 0x55}, //##Third_8bits_of_MBIST_User_Program_Even +{0x78, 0x55}, //##Fourth_8bits_of_MBIST_User_Program_Even +{0x79, 0x55}, //##Fifth_8bits_of_MBIST_User_Program_Even +{0x7A, 0x05}, //##First_8bits_of_MBIST_User_Program_Odd +{0x7B, 0x55}, //##Second_8bits_of_MBIST_User_Program_Odd +{0x7C, 0x55}, //##Third_8bits_of_MBIST_User_Program_Odd +{0x7D, 0x55}, //##Fourth_8bits_of_MBIST_User_Program_Odd +{0x7E, 0x55}, //##Fifth_8bits_of_MBIST_User_Program_Odd +{0x7F, 0x50}, //##IP_shutdown_register +{0x80, 0x00}, //##Protection_Register_Set +{0x81, 0x00}, //##MBIST_Status +{0x82, 0x00}, //##PWM_output_control +{0x83, 0x00}, //##Test_Mode_Control +{0x84, 0x00}, //##RAM1_test_register_address +{0x85, 0x00}, //##First_4bits_of_RAM1_data +{0x86, 0x00}, //##Second_8bits_of_RAM1_Data +{0x87, 0x00}, //##Third_8bits_of_RAM1_data +{0x88, 0x00}, //##Fourth_8bits_of_RAM1_Data +{0x89, 0x00}, //##Fifth_8bits_of_RAM1_Data +{0x8A, 0x00}, //##RAM1_test_r/w_control +{0x8B, 0x00}, //##RAM2_test_register_address +{0x8C, 0x00}, //##First_4bits_of_RAM2_data +{0x8D, 0x00}, //##Second_8bits_of_RAM2_Data +{0x8E, 0x00}, //##Third_8bits_of_RAM2_data +{0x8F, 0x00}, //##Fourth_8bits_of_RAM2_Data +{0x90, 0x00}, //##Fifth_8bits_of_RAM2_Data +{0x91, 0x00}, //##RAM2_test_r/w_control +{0x92, 0x00}, //##BURN_EN1 +{0x93, 0x00}, //##BURN_EN2 +{0x94, 0x00}, //##OSC_TRIM_CTRL +{0x95, 0x80}, //##PLL_CTRL +{0x96, 0x11}, //##PLL_CTRL2 +{0x97, 0x06}, //##CLKDET_read_out1 +{0x98, 0x11}, //##CLKDET_read_out2 +{0x99, 0x02}, //##CLKDET_read_out3 +{0x9A, 0x56}, //##CLKDET_read_out4 +{0x9B, 0x90}, //##CLKDET_read_out5 +{0x9C, 0x3F}, //##CLKDET_read_out6 +{0x9D, 0x00}, //##CLKDET_read_out7 +{0x9E, 0x02}, //##CLKDET_read_out8 +{0x9F, 0x02}, //##RECOUNT_CTRL +{0xA0, 0xE4}, //##RECOUNT_STABLE_CTRL +{0xA1, 0x04}, //##Auto_clock_detect_FS96k_window +{0xA2, 0x04}, //##Auto_clock_detect_FS48k_window +{0xA3, 0x04}, //##Auto_clock_detect_FS16k_window +{0xA4, 0x04}, //##Auto_clock_detect_FS8k_window +{0xA5, 0x80}, //##SYNC_LR +}; +#endif + +#ifdef AD82120B_CHANGE_EQ_MODE_EN +//###################RAM1_Table {RAM1 Address, Top Byte Of RAM1 Data , +//Middle Byte Of RAM1 Data , Botton Byte Of RAM1 Data }#################### +static unsigned char eq_mode_1_ram1_tab[][5] = { +{0x00, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ1 +{0x01, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ1 +{0x02, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ1 +{0x03, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ1 +{0x04, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ1 +{0x05, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ2 +{0x06, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ2 +{0x07, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ2 +{0x08, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ2 +{0x09, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ2 +{0x0A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ3 +{0x0B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ3 +{0x0C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ3 +{0x0D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ3 +{0x0E, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ3 +{0x0F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ4 +{0x10, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ4 +{0x11, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ4 +{0x12, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ4 +{0x13, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ4 +{0x14, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ5 +{0x15, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ5 +{0x16, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ5 +{0x17, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ5 +{0x18, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ5 +{0x19, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ6 +{0x1A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ6 +{0x1B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ6 +{0x1C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ6 +{0x1D, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ6 +{0x1E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ7 +{0x1F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ7 +{0x20, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ7 +{0x21, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ7 +{0x22, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ7 +{0x23, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ8 +{0x24, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ8 +{0x25, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ8 +{0x26, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ8 +{0x27, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ8 +{0x28, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ9 +{0x29, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ9 +{0x2A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ9 +{0x2B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ9 +{0x2C, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ9 +{0x2D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ10 +{0x2E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ10 +{0x2F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ10 +{0x30, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ10 +{0x31, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ10 +{0x32, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ11 +{0x33, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ11 +{0x34, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ11 +{0x35, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ11 +{0x36, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ11 +{0x37, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ12 +{0x38, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ12 +{0x39, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ12 +{0x3A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ12 +{0x3B, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ12 +{0x3C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ13 +{0x3D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ13 +{0x3E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ13 +{0x3F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ13 +{0x40, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ13 +{0x41, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ14 +{0x42, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ14 +{0x43, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ14 +{0x44, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ14 +{0x45, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ14 +{0x46, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ15 +{0x47, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ15 +{0x48, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ15 +{0x49, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ15 +{0x4A, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ15 +{0x4B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ16 +{0x4C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ16 +{0x4D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ16 +{0x4E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ16 +{0x4F, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ16 +{0x50, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ17 +{0x51, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ17 +{0x52, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ17 +{0x53, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ17 +{0x54, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ17 +{0x55, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ18 +{0x56, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ18 +{0x57, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ18 +{0x58, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ18 +{0x59, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ18 +{0x5A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ19 +{0x5B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ19 +{0x5C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ19 +{0x5D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ19 +{0x5E, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ19 +{0x5F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ20 +{0x60, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ20 +{0x61, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ20 +{0x62, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ20 +{0x63, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ20 +{0x64, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ21 +{0x65, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ21 +{0x66, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ21 +{0x67, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ21 +{0x68, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ21 +{0x69, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ22 +{0x6A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ22 +{0x6B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ22 +{0x6C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ22 +{0x6D, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ22 +{0x6E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ23 +{0x6F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ23 +{0x70, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ23 +{0x71, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ23 +{0x72, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ23 +{0x73, 0x07, 0xFF, 0xFF, 0xFF}, //##Channel_1_Mixer1 +{0x74, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_Mixer2 +{0x75, 0x00, 0x7E, 0x88, 0xE0}, //##Channel_1_Prescale +{0x76, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_Postscale +{0x77, 0x02, 0x00, 0x00, 0x00}, //##CH1.2_Power_Clipping +{0x78, 0x00, 0x00, 0x01, 0xA0}, //####Noise_Gate_Attack_Level +{0x79, 0x00, 0x00, 0x05, 0x30}, //##Noise_Gate_Release_Level +{0x7A, 0x00, 0x01, 0x00, 0x00}, //##DRC1_Energy_Coefficient +{0x7B, 0x00, 0x01, 0x00, 0x00}, //##DRC2_Energy_Coefficient +{0x7C, 0x00, 0x01, 0x00, 0x00}, //##DRC3_Energy_Coefficient +{0x7D, 0x00, 0x01, 0x00, 0x00}, //##DRC4_Energy_Coefficient +{0x7E, 0x00, 0x00, 0x00, 0x00}, //##DRC1_Power_Meter +{0x7F, 0x00, 0x00, 0x00, 0x00}, //##DRC3_Power_Meter +{0x80, 0x00, 0x00, 0x00, 0x00}, //##DRC5_Power_Meter +{0x81, 0x00, 0x00, 0x00, 0x00}, //##DRC7_Power_Meter +{0x82, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN1 +{0x83, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN2 +{0x84, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN3 +{0x85, 0x0E, 0x01, 0xC0, 0x70}, //##DRC1_FF_threshold +{0x86, 0x02, 0x00, 0x00, 0x00}, //##DRC1_FF_slope +{0x87, 0x00, 0x00, 0x40, 0x00}, //##DRC1_FF_aa +{0x88, 0x00, 0x00, 0x40, 0x00}, //##DRC1_FF_da +{0x89, 0x0E, 0x01, 0xC0, 0x70}, //##DRC2_FF_threshold +{0x8A, 0x02, 0x00, 0x00, 0x00}, //##DRC2_FF_slope +{0x8B, 0x00, 0x00, 0x40, 0x00}, //##DRC2_FF_aa +{0x8C, 0x00, 0x00, 0x40, 0x00}, //##DRC2_FF_da +{0x8D, 0x0E, 0x01, 0xC0, 0x70}, //##DRC3_FF_threshold +{0x8E, 0x02, 0x00, 0x00, 0x00}, //##DRC3_FF_slope +{0x8F, 0x00, 0x00, 0x40, 0x00}, //##DRC3_FF_aa +{0x90, 0x00, 0x00, 0x40, 0x00}, //##DRC3_FF_da +{0x91, 0x0E, 0x01, 0xC0, 0x70}, //##DRC4_FF_threshold +{0x92, 0x02, 0x00, 0x00, 0x00}, //##DRC4_FF_slope +{0x93, 0x00, 0x00, 0x40, 0x00}, //##DRC4_FF_aa +{0x94, 0x00, 0x00, 0x40, 0x00}, //##DRC4_FF_da +{0x95, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x96, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x97, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x98, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x99, 0x00, 0x80, 0x00, 0x00}, //##I2SO_LCH_GAIN +{0x9A, 0x02, 0x00, 0x00, 0x00}, //##SRS_Gain +{0x9B, 0x01, 0xD7, 0xE6, 0xE0}, //##Compensate_A0 +{0x9C, 0x00, 0x2E, 0x77, 0x40}, //##Compensate_A1 +{0x9D, 0x0F, 0xF9, 0xA1, 0xE0}, //##Compensate_B1 +{0x9E, 0x01, 0x91, 0x2B, 0xE0}, //##QT_AT +{0x9F, 0x01, 0x1B, 0x5A, 0xB9}, //##QT_RT +{0xA0, 0x00, 0x5F, 0xCA, 0xCA}, //##QT_Region_T +{0xA1, 0x00, 0x00, 0x00, 0x00}, //##QT_Region_B +}; + +#ifdef CONFIG_SND_SOC_AD82120B_2CHANNEL +//###################RAM2_Table {RAM2 Address, Top Byte Of RAM2 Data , +//Middle Byte Of RAM2 Data , Botton Byte Of RAM2 Data }#################### +static unsigned char eq_mode_1_ram2_tab[][5] = { +{0x00, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ1 +{0x01, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ1 +{0x02, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ1 +{0x03, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ1 +{0x04, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ1 +{0x05, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ2 +{0x06, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ2 +{0x07, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ2 +{0x08, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ2 +{0x09, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ2 +{0x0A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ3 +{0x0B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ3 +{0x0C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ3 +{0x0D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ3 +{0x0E, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ3 +{0x0F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ4 +{0x10, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ4 +{0x11, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ4 +{0x12, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ4 +{0x13, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ4 +{0x14, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ5 +{0x15, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ5 +{0x16, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ5 +{0x17, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ5 +{0x18, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ5 +{0x19, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ6 +{0x1A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ6 +{0x1B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ6 +{0x1C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ6 +{0x1D, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ6 +{0x1E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ7 +{0x1F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ7 +{0x20, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ7 +{0x21, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ7 +{0x22, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ7 +{0x23, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ8 +{0x24, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ8 +{0x25, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ8 +{0x26, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ8 +{0x27, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ8 +{0x28, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ9 +{0x29, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ9 +{0x2A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ9 +{0x2B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ9 +{0x2C, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ9 +{0x2D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ10 +{0x2E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ10 +{0x2F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ10 +{0x30, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ10 +{0x31, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ10 +{0x32, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ11 +{0x33, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ11 +{0x34, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ11 +{0x35, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ11 +{0x36, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ11 +{0x37, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ12 +{0x38, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ12 +{0x39, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ12 +{0x3A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ12 +{0x3B, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ12 +{0x3C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ13 +{0x3D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ13 +{0x3E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ13 +{0x3F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ13 +{0x40, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ13 +{0x41, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ14 +{0x42, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ14 +{0x43, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ14 +{0x44, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ14 +{0x45, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ14 +{0x46, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ15 +{0x47, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ15 +{0x48, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ15 +{0x49, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ15 +{0x4A, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ15 +{0x4B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ16 +{0x4C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ16 +{0x4D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ16 +{0x4E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ16 +{0x4F, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ16 +{0x50, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ17 +{0x51, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ17 +{0x52, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ17 +{0x53, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ17 +{0x54, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ17 +{0x55, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ18 +{0x56, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ18 +{0x57, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ18 +{0x58, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ18 +{0x59, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ18 +{0x5A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ19 +{0x5B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ19 +{0x5C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ19 +{0x5D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ19 +{0x5E, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ19 +{0x5F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ20 +{0x60, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ20 +{0x61, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ20 +{0x62, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ20 +{0x63, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ20 +{0x64, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ21 +{0x65, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ21 +{0x66, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ21 +{0x67, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ21 +{0x68, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ21 +{0x69, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ22 +{0x6A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ22 +{0x6B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ22 +{0x6C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ22 +{0x6D, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ22 +{0x6E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ23 +{0x6F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ23 +{0x70, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ23 +{0x71, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ23 +{0x72, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ23 +{0x73, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_Mixer1 +{0x74, 0x07, 0xFF, 0xFF, 0xFF}, //##Channel_2_Mixer2 +{0x75, 0x00, 0x80, 0x00, 0x00}, //##Channel_2_Prescale +{0x76, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_Postscale +{0x77, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x78, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x79, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7A, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7B, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7C, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7D, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7E, 0x00, 0x00, 0x00, 0x00}, //##DRC2_Power_Meter +{0x7F, 0x00, 0x00, 0x00, 0x00}, //##DRC4_Power_Meter +{0x80, 0x00, 0x00, 0x00, 0x00}, //##DRC6_Power_Meter +{0x81, 0x00, 0x00, 0x00, 0x00}, //##DRC8_Power_Meter +{0x82, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN1 +{0x83, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN2 +{0x84, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN3 +{0x85, 0x00, 0x02, 0x00, 0x00}, //##DPEQ_Energy_Coefficient +{0x86, 0x0D, 0x2D, 0x26, 0x00}, //##DPEQ_UP_TH +{0x87, 0x0B, 0x83, 0xF1, 0x10}, //##DPEQ_Low_TH +{0x88, 0x00, 0x26, 0x87, 0xF0}, //##DBE_1_div_(Upper-Lower) +{0x89, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8A, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8B, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8C, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8D, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8E, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8F, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x90, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x91, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x92, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x93, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x94, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x95, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x96, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x97, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x98, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x99, 0x00, 0x80, 0x00, 0x00}, //##I2SO_RCH_GAIN +{0x9A, 0x00, 0x5A, 0x9D, 0xF0}, //##AGC_Attach_threshold +{0x9B, 0x00, 0x47, 0xFA, 0xD0}, //##AGC_Release_threshold +{0x9C, 0x00, 0x00, 0x08, 0x64}, //##AGC_AR_RR +{0x9D, 0x00, 0x00, 0x08, 0x64}, //##AGC_AT_RT +{0x9E, 0x00, 0x10, 0x00, 0x00}, //##AGC ALPHA +}; +#endif +#endif diff --git a/sound/soc/codecs/amlogic/ad82120b_eq/ad82120b_eq_mode_2.h b/sound/soc/codecs/amlogic/ad82120b_eq/ad82120b_eq_mode_2.h new file mode 100644 index 000000000..d9cac16ec --- /dev/null +++ b/sound/soc/codecs/amlogic/ad82120b_eq/ad82120b_eq_mode_2.h @@ -0,0 +1,511 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#if DEBUG_0 +static unsigned char eq_mode_2_reg_tab[AD82120B_REGISTER_COUNT][2] = { +{0x00, 0x00}, //##State_Control_1 +{0x01, 0x82}, //##State_Control_2 +{0x02, 0x00}, //##State_Control_3 +{0x03, 0x40}, //##Master_volume_control +{0x04, 0x18}, //##Channel_1_volume_control +{0x05, 0x18}, //##Channel_2_volume_control +{0x06, 0x18}, //##Channel_3_volume_control +{0x07, 0x18}, //##Channel_4_volume_control +{0x08, 0x18}, //##Channel_5_volume_control +{0x09, 0x18}, //##Channel_6_volume_control +{0x0A, 0x40}, //##DTC_Setting +{0x0B, 0x00}, //##Reserve +{0x0C, 0x90}, //##State_Control_4 +{0x0D, 0x80}, //##Channel_1_configuration_registers +{0x0E, 0x80}, //##Channel_2_configuration_registers +{0x0F, 0x80}, //##Channel_3_configuration_registers +{0x10, 0x80}, //##Channel_4_configuration_registers +{0x11, 0x80}, //##Channel_5_configuration_registers +{0x12, 0x80}, //##Channel_6_configuration_registers +{0x13, 0x80}, //##Channel_7_configuration_registers +{0x14, 0x80}, //##Channel_8_configuration_registers +{0x15, 0x00}, //##Reserve +{0x16, 0x00}, //##Reserve +{0x17, 0x00}, //##Reserve +{0x18, 0x00}, //##Reserve +{0x19, 0x80}, //##Reserve +{0x1A, 0x28}, //##State_Control_5 +{0x1B, 0x80}, //##State_Control_6 +{0x1C, 0x20}, //##State_Control_7 +{0x1D, 0x00}, //##Coefficient_RAM_Base_Address +{0x1E, 0x00}, //##First_4-bits_of_coefficients_A1 +{0x1F, 0x00}, //##Second_8-bits_of_coefficients_A1 +{0x20, 0x00}, //##Third_8-bits_of_coefficients_A1 +{0x21, 0x00}, //##Fourth-bits_of_coefficients_A1 +{0x22, 0x00}, //##First_4-bits_of_coefficients_A2 +{0x23, 0x00}, //##Second_8-bits_of_coefficients_A2 +{0x24, 0x00}, //##Third_8-bits_of_coefficients_A2 +{0x25, 0x00}, //##Fourth_8-bits_of_coefficients_A2 +{0x26, 0x00}, //##First_4-bits_of_coefficients_B1 +{0x27, 0x00}, //##Second_8-bits_of_coefficients_B1 +{0x28, 0x00}, //##Third_8-bits_of_coefficients_B1 +{0x29, 0x00}, //##Fourth_8-bits_of_coefficients_B1 +{0x2A, 0x00}, //##First_4-bits_of_coefficients_B2 +{0x2B, 0x00}, //##Second_8-bits_of_coefficients_B2 +{0x2C, 0x00}, //##Third_8-bits_of_coefficients_B2 +{0x2D, 0x00}, //##Fourth-bits_of_coefficients_B2 +{0x2E, 0x00}, //##First_4-bits_of_coefficients_A0 +{0x2F, 0x80}, //##Second_8-bits_of_coefficients_A0 +{0x30, 0x00}, //##Third_8-bits_of_coefficients_A0 +{0x31, 0x00}, //##Fourth_8-bits_of_coefficients_A0 +{0x32, 0x00}, //##Coefficient_RAM_R/W_control +{0x33, 0x02}, //##State_Control_8 +{0x34, 0x00}, //##Reserve +{0x35, 0x00}, //##Volume_Fine_tune +{0x36, 0x00}, //##Volume_Fine_tune +{0x37, 0xA0}, //##Device_ID_register +{0x38, 0x00}, //##Level_Meter_Clear +{0x39, 0x00}, //##Power_Meter_Clear +{0x3A, 0x00}, //##First_8bits_of_C1_Level_Meter +{0x3B, 0x00}, //##Second_8bits_of_C1_Level_Meter +{0x3C, 0x00}, //##Third_8bits_of_C1_Level_Meter +{0x3D, 0x00}, //##Fourth_8bits_of_C1_Level_Meter +{0x3E, 0x00}, //##First_8bits_of_C2_Level_Meter +{0x3F, 0x00}, //##Second_8bits_of_C2_Level_Meter +{0x40, 0x00}, //##Third_8bits_of_C2_Level_Meter +{0x41, 0x00}, //##Fourth_8bits_of_C2_Level_Meter +{0x42, 0x00}, //##CHK_stat +{0x43, 0x00}, //##First_4_bits_of_BEQ_CHK_val +{0x44, 0x00}, //##Second_8_bits_of_BEQ_CHK_val +{0x45, 0x00}, //##Third_4_bits_of_BEQ_CHK_val +{0x46, 0x00}, //##Bottom_4_bits_of_BEQ_CHK_val +{0x47, 0x00}, //##First_4_bits_of_BEQ_CHK_result +{0x48, 0x00}, //##Second_4_bits_of_BEQ_CHK_result +{0x49, 0x00}, //##Third_4_bits_of_BEQ_CHK_result +{0x4A, 0x00}, //##Bottom_4_bits_of_BEQ_CHK_result +{0x4B, 0x10}, //##digital_DC_control +{0x4C, 0x20}, //##digital_DC_judge_threshold +{0x4D, 0xFF}, //##ERROR_register +{0x4E, 0xFF}, //##ERROR_latch_register +{0x4F, 0x00}, //##ERROR_clear_register +{0x50, 0x01}, //##ERROR_register_2 +{0x51, 0x01}, //##ERROR_latch_register_2 +{0x52, 0x00}, //##ERROR_clear_register_2 +{0x53, 0x00}, //##Reserve +{0x54, 0x00}, //##Reserve +{0x55, 0x20}, //##clock_FS_detection +{0x56, 0x10}, //##CLK_DET +{0x57, 0x00}, //##TDM_word_width_selection +{0x58, 0x00}, //##TDM_offset +{0x59, 0x06}, //##I2S_Data_output_selection_register +{0x5A, 0x08}, //##PWM_frequency_selection +{0x5B, 0x00}, //##Mono_Key_High_Byte +{0x5C, 0x00}, //##Mono_Key_Low_Byte +{0x5D, 0x07}, //##Hi-res_Item +{0x5E, 0x00}, //##analog_gain +{0x5F, 0x00}, //##AGC_Control +{0x60, 0x00}, //##Channel1_EQ_bypass_1 +{0x61, 0x00}, //##Channel1_EQ_bypass_2 +{0x62, 0x00}, //##Channel1_EQ_bypass_3 +{0x63, 0x00}, //##Channel2_EQ_bypass_1 +{0x64, 0x00}, //##Channel2_EQ_bypass_2 +{0x65, 0x00}, //##Channel2_EQ_bypass_3 +{0x66, 0x00}, //##ATTACK_HOLD_SET +{0x67, 0x00}, //##Reserve +{0x68, 0x00}, //##Reserve +{0x69, 0x00}, //##Reserve +{0x6A, 0x00}, //##Reserve +{0x6B, 0x00}, //##Reserve +{0x6C, 0x02}, //##FS_and_PMF_read_out +{0x6D, 0x03}, //##OC_Selection +{0x6E, 0x00}, //##digital_DC_control_testmode +{0x6F, 0x32}, //##test_mode_register0 +{0x70, 0x07}, //##noise_gate_analog_gain +{0x71, 0x41}, //##Testmode_register1 +{0x72, 0x38}, //##Testmode_register2 +{0x73, 0x18}, //##dither_signal_setting +{0x74, 0x0D}, //##Error_Delay +{0x75, 0x05}, //##First_4bits_of_MBIST_User_Program_Even +{0x76, 0x55}, //##Second_8bits_of_MBIST_User_Program_Even +{0x77, 0x55}, //##Third_8bits_of_MBIST_User_Program_Even +{0x78, 0x55}, //##Fourth_8bits_of_MBIST_User_Program_Even +{0x79, 0x55}, //##Fifth_8bits_of_MBIST_User_Program_Even +{0x7A, 0x05}, //##First_8bits_of_MBIST_User_Program_Odd +{0x7B, 0x55}, //##Second_8bits_of_MBIST_User_Program_Odd +{0x7C, 0x55}, //##Third_8bits_of_MBIST_User_Program_Odd +{0x7D, 0x55}, //##Fourth_8bits_of_MBIST_User_Program_Odd +{0x7E, 0x55}, //##Fifth_8bits_of_MBIST_User_Program_Odd +{0x7F, 0x50}, //##IP_shutdown_register +{0x80, 0x00}, //##Protection_Register_Set +{0x81, 0x00}, //##MBIST_Status +{0x82, 0x00}, //##PWM_output_control +{0x83, 0x00}, //##Test_Mode_Control +{0x84, 0x00}, //##RAM1_test_register_address +{0x85, 0x00}, //##First_4bits_of_RAM1_data +{0x86, 0x00}, //##Second_8bits_of_RAM1_Data +{0x87, 0x00}, //##Third_8bits_of_RAM1_data +{0x88, 0x00}, //##Fourth_8bits_of_RAM1_Data +{0x89, 0x00}, //##Fifth_8bits_of_RAM1_Data +{0x8A, 0x00}, //##RAM1_test_r/w_control +{0x8B, 0x00}, //##RAM2_test_register_address +{0x8C, 0x00}, //##First_4bits_of_RAM2_data +{0x8D, 0x00}, //##Second_8bits_of_RAM2_Data +{0x8E, 0x00}, //##Third_8bits_of_RAM2_data +{0x8F, 0x00}, //##Fourth_8bits_of_RAM2_Data +{0x90, 0x00}, //##Fifth_8bits_of_RAM2_Data +{0x91, 0x00}, //##RAM2_test_r/w_control +{0x92, 0x00}, //##BURN_EN1 +{0x93, 0x00}, //##BURN_EN2 +{0x94, 0x00}, //##OSC_TRIM_CTRL +{0x95, 0x80}, //##PLL_CTRL +{0x96, 0x11}, //##PLL_CTRL2 +{0x97, 0x06}, //##CLKDET_read_out1 +{0x98, 0x11}, //##CLKDET_read_out2 +{0x99, 0x02}, //##CLKDET_read_out3 +{0x9A, 0x56}, //##CLKDET_read_out4 +{0x9B, 0x90}, //##CLKDET_read_out5 +{0x9C, 0x3F}, //##CLKDET_read_out6 +{0x9D, 0x00}, //##CLKDET_read_out7 +{0x9E, 0x02}, //##CLKDET_read_out8 +{0x9F, 0x02}, //##RECOUNT_CTRL +{0xA0, 0xE4}, //##RECOUNT_STABLE_CTRL +{0xA1, 0x04}, //##Auto_clock_detect_FS96k_window +{0xA2, 0x04}, //##Auto_clock_detect_FS48k_window +{0xA3, 0x04}, //##Auto_clock_detect_FS16k_window +{0xA4, 0x04}, //##Auto_clock_detect_FS8k_window +{0xA5, 0x80}, //##SYNC_LR +}; +#endif + +#ifdef AD82120B_CHANGE_EQ_MODE_EN +//###################RAM1_Table {RAM1 Address, Top Byte Of RAM1 Data , +//Middle Byte Of RAM1 Data , Botton Byte Of RAM1 Data }#################### +static unsigned char eq_mode_2_ram1_tab[][5] = { +{0x00, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ1 +{0x01, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ1 +{0x02, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ1 +{0x03, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ1 +{0x04, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ1 +{0x05, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ2 +{0x06, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ2 +{0x07, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ2 +{0x08, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ2 +{0x09, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ2 +{0x0A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ3 +{0x0B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ3 +{0x0C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ3 +{0x0D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ3 +{0x0E, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ3 +{0x0F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ4 +{0x10, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ4 +{0x11, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ4 +{0x12, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ4 +{0x13, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ4 +{0x14, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ5 +{0x15, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ5 +{0x16, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ5 +{0x17, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ5 +{0x18, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ5 +{0x19, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ6 +{0x1A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ6 +{0x1B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ6 +{0x1C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ6 +{0x1D, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ6 +{0x1E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ7 +{0x1F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ7 +{0x20, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ7 +{0x21, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ7 +{0x22, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ7 +{0x23, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ8 +{0x24, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ8 +{0x25, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ8 +{0x26, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ8 +{0x27, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ8 +{0x28, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ9 +{0x29, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ9 +{0x2A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ9 +{0x2B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ9 +{0x2C, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ9 +{0x2D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ10 +{0x2E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ10 +{0x2F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ10 +{0x30, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ10 +{0x31, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ10 +{0x32, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ11 +{0x33, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ11 +{0x34, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ11 +{0x35, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ11 +{0x36, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ11 +{0x37, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ12 +{0x38, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ12 +{0x39, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ12 +{0x3A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ12 +{0x3B, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ12 +{0x3C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ13 +{0x3D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ13 +{0x3E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ13 +{0x3F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ13 +{0x40, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ13 +{0x41, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ14 +{0x42, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ14 +{0x43, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ14 +{0x44, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ14 +{0x45, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ14 +{0x46, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ15 +{0x47, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ15 +{0x48, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ15 +{0x49, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ15 +{0x4A, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ15 +{0x4B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ16 +{0x4C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ16 +{0x4D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ16 +{0x4E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ16 +{0x4F, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ16 +{0x50, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ17 +{0x51, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ17 +{0x52, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ17 +{0x53, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ17 +{0x54, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ17 +{0x55, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ18 +{0x56, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ18 +{0x57, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ18 +{0x58, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ18 +{0x59, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ18 +{0x5A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ19 +{0x5B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ19 +{0x5C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ19 +{0x5D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ19 +{0x5E, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ19 +{0x5F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ20 +{0x60, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ20 +{0x61, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ20 +{0x62, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ20 +{0x63, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ20 +{0x64, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ21 +{0x65, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ21 +{0x66, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ21 +{0x67, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ21 +{0x68, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ21 +{0x69, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ22 +{0x6A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ22 +{0x6B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ22 +{0x6C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ22 +{0x6D, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ22 +{0x6E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ23 +{0x6F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ23 +{0x70, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ23 +{0x71, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ23 +{0x72, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ23 +{0x73, 0x07, 0xFF, 0xFF, 0xFF}, //##Channel_1_Mixer1 +{0x74, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_Mixer2 +{0x75, 0x00, 0x7E, 0x88, 0xE0}, //##Channel_1_Prescale +{0x76, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_Postscale +{0x77, 0x02, 0x00, 0x00, 0x00}, //##CH1.2_Power_Clipping +{0x78, 0x00, 0x00, 0x01, 0xA0}, //####Noise_Gate_Attack_Level +{0x79, 0x00, 0x00, 0x05, 0x30}, //##Noise_Gate_Release_Level +{0x7A, 0x00, 0x01, 0x00, 0x00}, //##DRC1_Energy_Coefficient +{0x7B, 0x00, 0x01, 0x00, 0x00}, //##DRC2_Energy_Coefficient +{0x7C, 0x00, 0x01, 0x00, 0x00}, //##DRC3_Energy_Coefficient +{0x7D, 0x00, 0x01, 0x00, 0x00}, //##DRC4_Energy_Coefficient +{0x7E, 0x00, 0x00, 0x00, 0x00}, //##DRC1_Power_Meter +{0x7F, 0x00, 0x00, 0x00, 0x00}, //##DRC3_Power_Meter +{0x80, 0x00, 0x00, 0x00, 0x00}, //##DRC5_Power_Meter +{0x81, 0x00, 0x00, 0x00, 0x00}, //##DRC7_Power_Meter +{0x82, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN1 +{0x83, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN2 +{0x84, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN3 +{0x85, 0x0E, 0x01, 0xC0, 0x70}, //##DRC1_FF_threshold +{0x86, 0x02, 0x00, 0x00, 0x00}, //##DRC1_FF_slope +{0x87, 0x00, 0x00, 0x40, 0x00}, //##DRC1_FF_aa +{0x88, 0x00, 0x00, 0x40, 0x00}, //##DRC1_FF_da +{0x89, 0x0E, 0x01, 0xC0, 0x70}, //##DRC2_FF_threshold +{0x8A, 0x02, 0x00, 0x00, 0x00}, //##DRC2_FF_slope +{0x8B, 0x00, 0x00, 0x40, 0x00}, //##DRC2_FF_aa +{0x8C, 0x00, 0x00, 0x40, 0x00}, //##DRC2_FF_da +{0x8D, 0x0E, 0x01, 0xC0, 0x70}, //##DRC3_FF_threshold +{0x8E, 0x02, 0x00, 0x00, 0x00}, //##DRC3_FF_slope +{0x8F, 0x00, 0x00, 0x40, 0x00}, //##DRC3_FF_aa +{0x90, 0x00, 0x00, 0x40, 0x00}, //##DRC3_FF_da +{0x91, 0x0E, 0x01, 0xC0, 0x70}, //##DRC4_FF_threshold +{0x92, 0x02, 0x00, 0x00, 0x00}, //##DRC4_FF_slope +{0x93, 0x00, 0x00, 0x40, 0x00}, //##DRC4_FF_aa +{0x94, 0x00, 0x00, 0x40, 0x00}, //##DRC4_FF_da +{0x95, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x96, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x97, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x98, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x99, 0x00, 0x80, 0x00, 0x00}, //##I2SO_LCH_GAIN +{0x9A, 0x02, 0x00, 0x00, 0x00}, //##SRS_Gain +{0x9B, 0x01, 0xD7, 0xE6, 0xE0}, //##Compensate_A0 +{0x9C, 0x00, 0x2E, 0x77, 0x40}, //##Compensate_A1 +{0x9D, 0x0F, 0xF9, 0xA1, 0xE0}, //##Compensate_B1 +{0x9E, 0x01, 0x91, 0x2B, 0xE0}, //##QT_AT +{0x9F, 0x01, 0x1B, 0x5A, 0xB9}, //##QT_RT +{0xA0, 0x00, 0x5F, 0xCA, 0xCA}, //##QT_Region_T +{0xA1, 0x00, 0x00, 0x00, 0x00}, //##QT_Region_B +}; + +#ifdef CONFIG_SND_SOC_AD82120B_2CHANNEL +//###################RAM2_Table {RAM2 Address, Top Byte Of RAM2 Data , +//Middle Byte Of RAM2 Data , Botton Byte Of RAM2 Data }#################### +static unsigned char eq_mode_2_ram2_tab[][5] = { +{0x00, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ1 +{0x01, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ1 +{0x02, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ1 +{0x03, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ1 +{0x04, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ1 +{0x05, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ2 +{0x06, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ2 +{0x07, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ2 +{0x08, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ2 +{0x09, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ2 +{0x0A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ3 +{0x0B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ3 +{0x0C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ3 +{0x0D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ3 +{0x0E, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ3 +{0x0F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ4 +{0x10, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ4 +{0x11, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ4 +{0x12, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ4 +{0x13, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ4 +{0x14, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ5 +{0x15, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ5 +{0x16, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ5 +{0x17, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ5 +{0x18, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ5 +{0x19, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ6 +{0x1A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ6 +{0x1B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ6 +{0x1C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ6 +{0x1D, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ6 +{0x1E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ7 +{0x1F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ7 +{0x20, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ7 +{0x21, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ7 +{0x22, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ7 +{0x23, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ8 +{0x24, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ8 +{0x25, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ8 +{0x26, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ8 +{0x27, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ8 +{0x28, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ9 +{0x29, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ9 +{0x2A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ9 +{0x2B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ9 +{0x2C, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ9 +{0x2D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ10 +{0x2E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ10 +{0x2F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ10 +{0x30, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ10 +{0x31, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ10 +{0x32, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ11 +{0x33, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ11 +{0x34, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ11 +{0x35, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ11 +{0x36, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ11 +{0x37, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ12 +{0x38, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ12 +{0x39, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ12 +{0x3A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ12 +{0x3B, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ12 +{0x3C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ13 +{0x3D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ13 +{0x3E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ13 +{0x3F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ13 +{0x40, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ13 +{0x41, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ14 +{0x42, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ14 +{0x43, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ14 +{0x44, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ14 +{0x45, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ14 +{0x46, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ15 +{0x47, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ15 +{0x48, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ15 +{0x49, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ15 +{0x4A, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ15 +{0x4B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ16 +{0x4C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ16 +{0x4D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ16 +{0x4E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ16 +{0x4F, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ16 +{0x50, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ17 +{0x51, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ17 +{0x52, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ17 +{0x53, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ17 +{0x54, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ17 +{0x55, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ18 +{0x56, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ18 +{0x57, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ18 +{0x58, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ18 +{0x59, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ18 +{0x5A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ19 +{0x5B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ19 +{0x5C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ19 +{0x5D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ19 +{0x5E, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ19 +{0x5F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ20 +{0x60, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ20 +{0x61, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ20 +{0x62, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ20 +{0x63, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ20 +{0x64, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ21 +{0x65, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ21 +{0x66, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ21 +{0x67, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ21 +{0x68, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ21 +{0x69, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ22 +{0x6A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ22 +{0x6B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ22 +{0x6C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ22 +{0x6D, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ22 +{0x6E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ23 +{0x6F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ23 +{0x70, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ23 +{0x71, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ23 +{0x72, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ23 +{0x73, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_Mixer1 +{0x74, 0x07, 0xFF, 0xFF, 0xFF}, //##Channel_2_Mixer2 +{0x75, 0x00, 0x80, 0x00, 0x00}, //##Channel_2_Prescale +{0x76, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_Postscale +{0x77, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x78, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x79, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7A, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7B, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7C, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7D, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x7E, 0x00, 0x00, 0x00, 0x00}, //##DRC2_Power_Meter +{0x7F, 0x00, 0x00, 0x00, 0x00}, //##DRC4_Power_Meter +{0x80, 0x00, 0x00, 0x00, 0x00}, //##DRC6_Power_Meter +{0x81, 0x00, 0x00, 0x00, 0x00}, //##DRC8_Power_Meter +{0x82, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN1 +{0x83, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN2 +{0x84, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN3 +{0x85, 0x00, 0x02, 0x00, 0x00}, //##DPEQ_Energy_Coefficient +{0x86, 0x0D, 0x2D, 0x26, 0x00}, //##DPEQ_UP_TH +{0x87, 0x0B, 0x83, 0xF1, 0x10}, //##DPEQ_Low_TH +{0x88, 0x00, 0x26, 0x87, 0xF0}, //##DBE_1_div_(Upper-Lower) +{0x89, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8A, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8B, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8C, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8D, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8E, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x8F, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x90, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x91, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x92, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x93, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x94, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x95, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x96, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x97, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x98, 0x00, 0x00, 0x00, 0x00}, //##Reserve +{0x99, 0x00, 0x80, 0x00, 0x00}, //##I2SO_RCH_GAIN +{0x9A, 0x00, 0x5A, 0x9D, 0xF0}, //##AGC_Attach_threshold +{0x9B, 0x00, 0x47, 0xFA, 0xD0}, //##AGC_Release_threshold +{0x9C, 0x00, 0x00, 0x08, 0x64}, //##AGC_AR_RR +{0x9D, 0x00, 0x00, 0x08, 0x64}, //##AGC_AT_RT +{0x9E, 0x00, 0x10, 0x00, 0x00}, //##AGC ALPHA +}; +#endif +#endif +