diff --git a/drivers/clk/meson/clk-cpu-dyndiv.c b/drivers/clk/meson/clk-cpu-dyndiv.c index f5a574aa8..7597f0b11 100644 --- a/drivers/clk/meson/clk-cpu-dyndiv.c +++ b/drivers/clk/meson/clk-cpu-dyndiv.c @@ -150,7 +150,7 @@ static int meson_clk_cpu_dyn_set_rate(struct clk_hw *hw, unsigned long rate, nrate = table->rate; /* For set more than 1G, need to set additional parent frequency */ - if (!strcmp(clk_hw_get_name(hw), "dsu_dyn_clk") && nrate > 1000000000) { + if (nrate > 1000000000 && !strcmp(clk_hw_get_name(hw), "dsu_dyn_clk")) { if (clk_get_rate(hw->clk) > 1000000000) { /* switch dsu to fix div2 */ if (data->smc_id) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 568bb00fd..b21d56722 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -769,18 +769,15 @@ static int meson_secure_pll_v2_set_rate(struct clk_hw *hw, unsigned long rate, struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); struct arm_smccc_res res; - unsigned int enabled, m, n, ret = 0; - unsigned long old_rate; -#if defined CONFIG_AMLOGIC_MODIFY && defined CONFIG_ARM + unsigned int m, n, ret = 0; +#ifdef CONFIG_ARM unsigned int od; #endif if (parent_rate == 0 || rate == 0) return -EINVAL; - old_rate = rate; - -#if defined CONFIG_AMLOGIC_MODIFY && defined CONFIG_ARM +#ifdef CONFIG_ARM ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll, &od); #else ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll); @@ -788,11 +785,10 @@ static int meson_secure_pll_v2_set_rate(struct clk_hw *hw, unsigned long rate, if (ret) return ret; - enabled = meson_parm_read(clk->map, &pll->en); - if (enabled) + if (meson_parm_read(clk->map, &pll->en)) meson_secure_pll_v2_disable(hw); - /*Send m,n for arm64 */ -#if defined CONFIG_AMLOGIC_MODIFY && defined CONFIG_ARM + +#ifdef CONFIG_ARM arm_smccc_smc(pll->smc_id, pll->secid, m, n, od, 0, 0, 0, &res); #else @@ -819,9 +815,9 @@ static int meson_secure_pll_v2_enable(struct clk_hw *hw) /* If PLL is not enabled because setting the same rate, * Enable it again, CCF will return when set the same rate */ - n = meson_parm_read(clk->map, &pll->n); m = meson_parm_read(clk->map, &pll->m); + /* od is required in arm64 and arm */ od = meson_parm_read(clk->map, &pll->od); arm_smccc_smc(pll->smc_id, pll->secid, @@ -849,12 +845,11 @@ static int meson_clk_pll_v3_set_rate(struct clk_hw *hw, unsigned long rate, struct parm *pn = &pll->n; struct parm *pth = &pll->th; struct parm *pfrac = &pll->frac; - unsigned int enabled, m, n, frac; - unsigned long old_rate; + unsigned int m, n, frac; unsigned int val; const struct reg_sequence *init_regs = pll->init_regs; int i, ret = 0, retry = 10; -#if defined CONFIG_AMLOGIC_MODIFY && defined CONFIG_ARM +#ifdef CONFIG_ARM unsigned int od; struct parm *pod = &pll->od; #endif @@ -862,10 +857,8 @@ static int meson_clk_pll_v3_set_rate(struct clk_hw *hw, unsigned long rate, if (parent_rate == 0 || rate == 0) return -EINVAL; - old_rate = rate; - /* calculate M, N, OD*/ -#if defined CONFIG_AMLOGIC_MODIFY && defined CONFIG_ARM +#ifdef CONFIG_ARM ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll, &od); #else ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll); @@ -875,7 +868,7 @@ static int meson_clk_pll_v3_set_rate(struct clk_hw *hw, unsigned long rate, /* calute frac */ if (MESON_PARM_APPLICABLE(&pll->frac)) { -#if defined CONFIG_AMLOGIC_MODIFY && defined CONFIG_ARM +#ifdef CONFIG_ARM frac = __pll_params_with_frac(rate, parent_rate, m, n, od, pll); #else frac = __pll_params_with_frac(rate, parent_rate, m, n, pll); @@ -886,7 +879,7 @@ static int meson_clk_pll_v3_set_rate(struct clk_hw *hw, unsigned long rate, */ if (meson_parm_read(clk->map, &pll->m) == m && meson_parm_read(clk->map, &pll->n) == n && -#if defined CONFIG_ARM +#ifdef CONFIG_ARM meson_parm_read(clk->map, &pll->od) == od && #endif meson_parm_read(clk->map, &pll->en)) { @@ -901,8 +894,7 @@ static int meson_clk_pll_v3_set_rate(struct clk_hw *hw, unsigned long rate, } } - enabled = meson_parm_read(clk->map, &pll->en); - if (enabled) + if (meson_parm_read(clk->map, &pll->en)) meson_clk_pll_disable(hw); do { @@ -912,7 +904,7 @@ static int meson_clk_pll_v3_set_rate(struct clk_hw *hw, unsigned long rate, val = init_regs[i].def; if (MESON_PARM_APPLICABLE(&pll->th)) { val &= CLRPMASK(pth->width, pth->shift); -#if defined CONFIG_ARM +#ifdef CONFIG_ARM if (__pll_params_to_rate(parent_rate, m, n, frac, pll, 0) >= MESON_PLL_THRESHOLD_RATE) val |= 1 << pth->shift; @@ -926,7 +918,7 @@ static int meson_clk_pll_v3_set_rate(struct clk_hw *hw, unsigned long rate, val &= CLRPMASK(pm->width, pm->shift); val |= n << pn->shift; val |= m << pm->shift; -#if defined CONFIG_AMLOGIC_MODIFY && defined CONFIG_ARM +#ifdef CONFIG_ARM val &= CLRPMASK(pod->width, pod->shift); val |= od << pod->shift; #endif @@ -977,7 +969,9 @@ static int meson_clk_pll_v3_enable(struct clk_hw *hw) } const struct clk_ops meson_clk_pll_v3_ops = { - .init = meson_clk_pll_init, + /* walk the init regs each time when set a new rate, + * init callback is not useful for v3 ops + */ .recalc_rate = meson_clk_pll_recalc_rate, .round_rate = meson_clk_pll_round_rate, .set_rate = meson_clk_pll_v3_set_rate, diff --git a/drivers/clk/meson/t3x.c b/drivers/clk/meson/t3x.c index 4438eecca..d7819d6b9 100644 --- a/drivers/clk/meson/t3x.c +++ b/drivers/clk/meson/t3x.c @@ -37,7 +37,6 @@ static const struct pll_params_table t3x_sys_pll_params_table[] = { PLL_PARAMS(75, 1, 0), /*DCO=1800M OD=1800M*/ PLL_PARAMS(79, 1, 0), /*DCO=1896M OD=1896M*/ PLL_PARAMS(167, 2, 0), /*DCO=2004M OD=2004M*/ - PLL_PARAMS(84, 1, 0), /*DCO=2016M OD=2016M*/ { /* sentinel */ } }; #else @@ -85,14 +84,12 @@ static struct clk_regmap t3x_sys_pll_dco = { .shift = 16, .width = 5, }, -#ifdef CONFIG_ARM - /* od for 32bit */ + /* od is required when setting the same rate during STR */ .od = { .reg_off = CLKCTRL_SYS0PLL_CTRL0, .shift = 12, .width = 3, }, -#endif .table = t3x_sys_pll_params_table, .l = { .reg_off = CLKCTRL_SYS0PLL_CTRL0, @@ -119,7 +116,7 @@ static struct clk_regmap t3x_sys_pll_dco = { * This clock feeds the CPU, avoid disabling it * Register has the risk of being directly operated */ - .flags = CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE, + .flags = CLK_IS_CRITICAL }, }; @@ -988,9 +985,6 @@ static struct clk_regmap t3x_pcie_hcsl = { /* a55 cpu_clk, get the table from ucode */ static const struct cpu_dyn_table t3x_cpu_dyn_table[] = { - CPU_LOW_PARAMS(100000000, 1, 1, 9), - CPU_LOW_PARAMS(250000000, 1, 1, 3), - CPU_LOW_PARAMS(333333333, 2, 1, 1), CPU_LOW_PARAMS(500000000, 1, 1, 1), CPU_LOW_PARAMS(666666666, 2, 0, 0), CPU_LOW_PARAMS(1000000000, 1, 0, 0) @@ -1023,7 +1017,6 @@ static struct clk_regmap t3x_cpu_clk = { .data = &(struct clk_regmap_mux_data){ .mask = 0x1, .shift = 11, - .flags = CLK_MUX_ROUND_CLOSEST, .smc_id = SECURE_CPU_CLK, .secid = SECID_CPU_CLK_SEL, .secid_rd = SECID_CPU_CLK_RD @@ -1036,11 +1029,7 @@ static struct clk_regmap t3x_cpu_clk = { &t3x_sys_pll.hw, }, .num_parents = 2, - /* - * This clock feeds the CPU, avoid disabling it - * Register has the risk of being directly operated - */ - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .flags = CLK_SET_RATE_PARENT }, }; @@ -1076,7 +1065,7 @@ static struct clk_regmap t3x_a76_clk = { &t3x_sys1_pll.hw, }, .num_parents = 2, - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .flags = CLK_SET_RATE_PARENT }, }; @@ -1158,14 +1147,6 @@ static int t3x_sys_pll_notifier_cb(struct notifier_block *nb, * \- sys_pll * \- sys_pll_dco */ - - /* - * Configure cpu_clk to use cpu_clk_dyn - * Make sure cpu clk is 1G, cpu_clk_dyn may equal 24M - */ - if (clk_set_rate(nb_data->cpu_dyn_clk->clk, 1000000000)) - pr_err("%s: set CPU dyn clock to 1G failed\n", __func__); - clk_hw_set_parent(nb_data->cpu_clk, nb_data->cpu_dyn_clk); @@ -1179,9 +1160,6 @@ static int t3x_sys_pll_notifier_cb(struct notifier_block *nb, * \- xtal/fclk_div2/fclk_div3 * \- xtal/fclk_div2/fclk_div3 */ - - udelay(5); - return NOTIFY_OK; case POST_RATE_CHANGE: @@ -1193,9 +1171,6 @@ static int t3x_sys_pll_notifier_cb(struct notifier_block *nb, /* Configure cpu_clk to use sys_pll */ clk_hw_set_parent(nb_data->cpu_clk, nb_data->sys_pll); - - udelay(5); - /* new path : * cpu_clk * \- sys_pll @@ -1209,19 +1184,21 @@ static int t3x_sys_pll_notifier_cb(struct notifier_block *nb, } } -static struct t3x_sys_pll_nb_data t3x_sys_pll_nb_data = { - .sys_pll = &t3x_sys_pll.hw, - .cpu_clk = &t3x_cpu_clk.hw, - .cpu_dyn_clk = &t3x_cpu_dyn_clk.hw, - .nb.notifier_call = t3x_sys_pll_notifier_cb, -}; - -static struct t3x_sys_pll_nb_data t3x_sys1_pll_nb_data = { - .sys_pll = &t3x_sys1_pll.hw, - .cpu_clk = &t3x_a76_clk.hw, - .cpu_dyn_clk = &t3x_a76_dyn_clk.hw, - .nb.notifier_call = t3x_sys_pll_notifier_cb, -}; +/* + *static struct t3x_sys_pll_nb_data t3x_sys_pll_nb_data = { + * .sys_pll = &t3x_sys_pll.hw, + * .cpu_clk = &t3x_cpu_clk.hw, + * .cpu_dyn_clk = &t3x_cpu_dyn_clk.hw, + * .nb.notifier_call = t3x_sys_pll_notifier_cb, + *}; + * + *static struct t3x_sys_pll_nb_data t3x_sys1_pll_nb_data = { + * .sys_pll = &t3x_sys1_pll.hw, + * .cpu_clk = &t3x_a76_clk.hw, + * .cpu_dyn_clk = &t3x_a76_dyn_clk.hw, + * .nb.notifier_call = t3x_sys_pll_notifier_cb, + *}; + */ static struct t3x_sys_pll_nb_data t3x_sys3_pll_nb_data = { .sys_pll = &t3x_sys3_pll.hw, @@ -7136,20 +7113,28 @@ static int meson_t3x_dvfs_setup(struct platform_device *pdev) { int ret; + /* avoid cpu/dsu run at 24M in dvfs, remove it here. + * cpu or a76 do it in dvfs init + */ + if (clk_set_rate(t3x_dsu_dyn_clk.hw.clk, 1000000000)) + pr_err("%s: set dsu dyn clock to 1G failed\n", __func__); /* Setup cluster 0 clock notifier for sys_pll */ - ret = clk_notifier_register(t3x_sys_pll.hw.clk, - &t3x_sys_pll_nb_data.nb); - if (ret) { - dev_err(&pdev->dev, "failed to register sys_pll notifier\n"); - return ret; - } +/* + * ret = clk_notifier_register(t3x_sys_pll.hw.clk, + * &t3x_sys_pll_nb_data.nb); + * if (ret) { + * dev_err(&pdev->dev, "failed to register sys_pll notifier\n"); + * return ret; + * } + */ /* Setup cluster 1 clock notifier for sys1_pll */ - ret = clk_notifier_register(t3x_sys1_pll.hw.clk, - &t3x_sys1_pll_nb_data.nb); - if (ret) { - dev_err(&pdev->dev, "failed to register sys1_pll notifier\n"); - return ret; - } + /* ret = clk_notifier_register(t3x_sys1_pll.hw.clk, + * &t3x_sys1_pll_nb_data.nb); + * if (ret) { + * dev_err(&pdev->dev, "failed to register sys1_pll notifier\n"); + * return ret; + * } + */ /* Setup DSU clock notifier for sys3_pll */ ret = clk_notifier_register(t3x_sys3_pll.hw.clk, &t3x_sys3_pll_nb_data.nb);