diff --git a/arch/arm64/boot/dts/amlogic/t5m_reva_t963d4_ay309_2g.dts b/arch/arm64/boot/dts/amlogic/t5m_reva_t963d4_ay309_2g.dts index cdc20093b..265062941 100644 --- a/arch/arm64/boot/dts/amlogic/t5m_reva_t963d4_ay309_2g.dts +++ b/arch/arm64/boot/dts/amlogic/t5m_reva_t963d4_ay309_2g.dts @@ -520,7 +520,7 @@ * bit 0: for 4k * bit 1: for 1080p ***************************************************/ - alloc_sct = <2>; + alloc_sct = <1>; /*************************************************** * hf: default is 0 (T7/T3/SC2/S4 new path) * 0:not enable; diff --git a/arch/arm64/boot/dts/amlogic/t5m_t963d4_ay309_2g.dts b/arch/arm64/boot/dts/amlogic/t5m_t963d4_ay309_2g.dts index 5b6e90a5f..f4fe7f3c1 100644 --- a/arch/arm64/boot/dts/amlogic/t5m_t963d4_ay309_2g.dts +++ b/arch/arm64/boot/dts/amlogic/t5m_t963d4_ay309_2g.dts @@ -521,7 +521,7 @@ * bit 0: for 4k * bit 1: for 1080p ***************************************************/ - alloc_sct = <2>; + alloc_sct = <1>; /*************************************************** * hf: default is 0 (T7/T3/SC2/S4 new path) * 0:not enable; diff --git a/drivers/media/deinterlace/deinterlace.c b/drivers/media/deinterlace/deinterlace.c index 43a14b28c..8ed531721 100644 --- a/drivers/media/deinterlace/deinterlace.c +++ b/drivers/media/deinterlace/deinterlace.c @@ -2964,6 +2964,7 @@ static void di_uninit_buf(unsigned int disable_mirror) pr_dbg("%s keep cur di_buf %d (", __func__, keep_buf->index); for (i = 0; i < USED_LOCAL_BUF_MAX; i++) { + /*coverity[var_deref_op] null pointer has been judged*/ if (!IS_ERR_OR_NULL(keep_buf->di_buf_dup_p[i])) pr_dbg("%d\t", keep_buf->di_buf_dup_p[i]->index); @@ -3837,6 +3838,7 @@ static void pre_de_done_buf_config(void) if (di_pre_stru.source_change_flag) { /* add dummy buf, will not be displayed */ + /*coverity[var_deref_model] post_wr_buf has been judged*/ add_dummy_vframe_type_pre(post_wr_buf); } di_pre_stru.di_wr_buf->seq = @@ -3999,6 +4001,7 @@ static struct di_buf_s *get_free_linked_buf(int idx) queue_out(di_buf_linked); } } + /*coverity[FORWARD_NULL] di_buf has been judged empty*/ if (IS_ERR_OR_NULL(di_buf)) return NULL; di_buf->di_wr_linked_buf = di_buf_linked; @@ -6930,8 +6933,13 @@ static void di_pre_size_change(unsigned short width, { unsigned int blkhsize = 0; int pps_w = 0, pps_h = 0; + struct nr_cfg_s cfg_data; + struct nr_cfg_s *cfg = &cfg_data; - di_nr_opl()->nr_all_config(width, height, vf_type); + cfg->width = width; + cfg->height = height; + cfg->linkflag = 0; + di_nr_opl()->nr_all_config(vf_type, cfg); #ifdef DET3D det3d_config(det3d_en ? 1 : 0); #endif @@ -8296,6 +8304,7 @@ static long di_ioctl(struct file *file, unsigned int cmd, unsigned long arg) switch (cmd) { case AMDI_IOC_SET_PQ_PARM: mm_size = sizeof(struct am_pq_parm_s); + /*coverity[TAINTED_SCALAR] not a tainted data*/ if (copy_from_user(&tmp_pq_s, argp, mm_size)) { pr_err("[DI] set pq parm errors\n"); return -EFAULT; diff --git a/drivers/media/deinterlace/deinterlace_mtn.c b/drivers/media/deinterlace/deinterlace_mtn.c index ab5386467..8b3d74eeb 100644 --- a/drivers/media/deinterlace/deinterlace_mtn.c +++ b/drivers/media/deinterlace/deinterlace_mtn.c @@ -106,6 +106,18 @@ static int combing_dejaggy_setting[6] = {1, 1, 1, 2, 3, 3}; module_param_array(combing_dejaggy_setting, uint, &num_dejaggy_setting, 0664); static struct combing_param_s cmb_param; +/*from T3 /t5db adaptive_combing_new from vlsi yanling*/ +static int combing_debug_print; +module_param_named(combing_debug_print, combing_debug_print, int, 0664); +static int roku_th_test = 10000; +module_param_named(roku_th_test, roku_th_test, int, 0664); +static int th = 200; +module_param_named(th, th, int, 0664); +static int th_cont = 10; +module_param_named(th_cont, th_cont, int, 0664); +static int change_th = 26; +module_param_named(change_th, change_th, int, 0664); +/*end*/ static unsigned int combing_setting_masks[MAX_NUM_DI_REG] = { 0x0fffffff, @@ -200,7 +212,8 @@ static unsigned int combing_bias_motion_setting[MAX_NUM_DI_REG] = { /*idea from mingliang.dong & vlsi zheng.bao begin*/ 0x0001FF12, /* 0x0001ff0c */ 0x00200204, /* 0x00400204 */ - 0x00012002, /* 0x00016404 */ + /* change 0x00012002 to 0x00016404(idea from VLSI yanling.liu)*/ + 0x00016404, /*22-12-09*/ /*idea from mingliang.dong & vlsi zheng.bao end*/ 0x00000142 }; @@ -221,7 +234,8 @@ static unsigned int combing_very_motion_setting[MAX_NUM_DI_REG] = { 0x60000404, /* 0x40020a04*/ 0x0001FF12, /* 0x0001ff0c */ 0x00200204, /* 0x00400204 */ - 0x00012002, /* 0x00016404 */ + /* change 0x00012002 to 0x00016404(idea from VLSI yanling.liu)*/ + 0x00016404, /*22-12-09*/ /*idea from mingliang.dong & vlsi zheng.bao end*/ 0x00000131 }; @@ -247,7 +261,8 @@ static const unsigned int combing_bias_p_ori[] = { /*idea from mingliang.dong & vlsi zheng.bao begin*/ 0x0001FF12, /* 0x0001ff0c */ 0x00200204, /* 0x00400204 */ - 0x00012002, /* 0x00016404 */ + /* change 0x00012002 to 0x00016404(idea from VLSI yanling.liu)*/ + 0x00016404, /*22-12-09*/ /*idea from mingliang.dong & vlsi zheng.bao end*/ 0x00000142 }; @@ -268,7 +283,8 @@ static const unsigned int combing_very_p_ori[] = { 0x60000404, /* 0x40020a04*/ 0x0001FF12, /* 0x0001ff0c */ 0x00200204, /* 0x00400204 */ - 0x00012002, /* 0x00016404 */ + /* change 0x00012002 to 0x00016404(idea from VLSI yanling.liu)*/ + 0x00016404, /*22-12-09*/ /*idea from mingliang.dong & vlsi zheng.bao end*/ 0x00000131 }; @@ -351,7 +367,7 @@ static unsigned int combing_very_p_480i[] = { 0x0A0A0201, /* 6 */ 0x1A1A2662, /* 7 */ 0x0D200302, /* 8 */ - 0x02020606, /* 9 */ + 0x04040606, /* 9 */ 0x05080344, /* 10 */ /*idea from mingliang.dong & vlsi zheng.bao begin*/ 0x60000404, /* 0x40020a04*/ @@ -1040,6 +1056,84 @@ int adaptive_combing_fixing( return 0; } +void adaptive_combing_new(unsigned int field_diff, + unsigned int frame_diff) +{ + static int cont_change; + static int glb_mot_cont; + + static int glb_mot[5] = {0, 0, 0, 0, 0}; + + glb_mot[1] = glb_mot[0]; + glb_mot[0] = frame_diff; + + if (glb_mot[1] - glb_mot[0] > glb_mot[0] * 10 && + glb_mot[1] > roku_th_test){ + cont_change = 1; + if (combing_debug_print) + pr_info("A mot[0]=0x%x,glb_mot[1]=0x%x,change=0x%x\n\n", + glb_mot[0], glb_mot[1], cont_change); + } + if (cont_change > 0) { + cont_change = cont_change + 1; + if (combing_debug_print) + pr_info("B mot[0]=0x%x,glb_mot[1]=0x%x,change=0x%x\n\n", + glb_mot[0], glb_mot[1], cont_change); + } + if (cont_change > change_th) { + cont_change = 0; + if (combing_debug_print) + pr_info("c mot[0]=0x%x,glb_mot[1]=0x%x,change=0x%x\n\n", + glb_mot[0], glb_mot[1], cont_change); + } + if (glb_mot[0] > th) { + glb_mot_cont = MIN(20, glb_mot_cont + 1); + if (combing_debug_print) + pr_info("d glb_mot[0]=0x%x,glb_mot_cont=0x%x\n\n", + glb_mot[0], glb_mot_cont); + + } else { + if (combing_debug_print) + pr_info("e glb_mot[0]=0x%x,glb_mot_cont=0x%x\n\n", + glb_mot[0], glb_mot_cont); + glb_mot_cont = 0; + } + if ((glb_mot_cont < th_cont || glb_mot[0] < th) || cont_change > 0) { + DI_Wr(0x1741, 0x1A1A3A62); + DI_Wr(0x1742, 0x15200101); + DI_Wr(0x1743, 0x01200440); + DI_Wr(0x1744, 0x74200D0D); + DI_Wr(0x17ad, 0x02020606); + DI_Wr(0x17ae, 0x05080304); + DI_Wr(0x17a9, 0x0D5A1520); + DI_Wr(0x17aa, 0x0A0A0201); + DI_Wr(0x17ab, 0x1A1A2662); + DI_Wr(0x17ac, 0x0D200302); + DI_Wr(0x17af, 0x40020a04); + //pr_info("F TEST\n"); + } else { + DI_Wr(0x1741, 0x0A0A1A22); + DI_Wr(0x1742, 0x0a100101); + DI_Wr(0x1743, 0x01020420); + DI_Wr(0x1744, 0x32210404); + DI_Wr(0x17ad, 0x04040606); + DI_Wr(0x17ae, 0x02030202); + DI_Wr(0x17a9, 0x0a100505); + DI_Wr(0x17aa, 0x04040101); + DI_Wr(0x17ab, 0x0a0a0a0a); + DI_Wr(0x17ac, 0x0f100101); + DI_Wr(0x17af, 0x60020a60); + //pr_info("G TEST\n"); + } + + if (combing_debug_print) { + pr_info("f cont=0x%x,change=0x%x\n\n", + glb_mot_cont, cont_change); + pr_info("0x17ad=0x%x,0x17ae=0x%x\n\n", + Rd(DI_MTN_1_CTRL10), Rd(DI_MTN_1_CTRL11)); + } +} + #ifdef DEBUG_SUPPORT module_param_named(cmb_adpset_cnt, cmb_adpset_cnt, int, 0644); #endif @@ -1048,6 +1142,7 @@ static const struct mtn_op_s di_ops_mtn = { .adpative_combing_exit = adpative_combing_exit, .fix_tl1_1080i_patch_sel = fix_tl1_1080i_patch_sel, .adaptive_combing_fixing = adaptive_combing_fixing, + .adaptive_combing_new = adaptive_combing_new, .adpative_combing_config = adpative_combing_config, .com_patch_pre_sw_set = com_patch_pre_sw_set, /*.module_para = dim_seq_file_module_para_mtn,*/ diff --git a/drivers/media/deinterlace/deinterlace_mtn.h b/drivers/media/deinterlace/deinterlace_mtn.h index 4c25b9892..0c62c091e 100644 --- a/drivers/media/deinterlace/deinterlace_mtn.h +++ b/drivers/media/deinterlace/deinterlace_mtn.h @@ -46,6 +46,7 @@ int adaptive_combing_fixing( struct combing_status_s *cmb_status, unsigned int field_diff, unsigned int frame_diff, int bit_mode); +void adaptive_combing_new(unsigned int field_diff, unsigned int frame_diff); void adpative_combing_exit(void); extern void mtn_int_combing_glbmot(void); void com_patch_pre_sw_set(unsigned int mode); diff --git a/drivers/media/deinterlace/di_pqa.h b/drivers/media/deinterlace/di_pqa.h index 091cc8c98..9cd53e270 100644 --- a/drivers/media/deinterlace/di_pqa.h +++ b/drivers/media/deinterlace/di_pqa.h @@ -92,14 +92,19 @@ bool di_attach_ops_3d(const struct detect3d_op_s **ops); /************************** * nr_drv *************************/ +struct nr_cfg_s { + unsigned short width; + unsigned short height; + unsigned int linkflag; +}; + struct nr_op_s { void (*nr_hw_init)(void); void (*nr_gate_control)(bool gate); void (*nr_drv_init)(struct device *dev); void (*nr_drv_uninit)(struct device *dev); void (*nr_process_in_irq)(void); - void (*nr_all_config)(unsigned short ncol, unsigned short nrow, - unsigned short type); + void (*nr_all_config)(unsigned short type, struct nr_cfg_s *cfg); bool (*set_nr_ctrl_reg_table)(unsigned int addr, unsigned int value); void (*cue_int)(struct vframe_s *vf); void (*adaptive_cue_adjust)(unsigned int frame_diff, @@ -119,9 +124,9 @@ struct nr_opr_s { void (*nr_drv_init)(struct device *dev); void (*nr_drv_uninit)(struct device *dev); void (*nr_process_in_irq)(const struct reg_acc *op); - void (*nr_all_config)(unsigned short ncol, unsigned short nrow, - unsigned short type, - const struct reg_acc *op); + void (*nr_all_config)(unsigned short type, + const struct reg_acc *op, + struct nr_cfg_s *cfg); bool (*set_nr_ctrl_reg_table)(unsigned int addr, unsigned int value); //same void (*cue_int)(struct vframe_s *vf, @@ -148,6 +153,8 @@ struct mtn_op_s { struct combing_status_s *cmb_status, unsigned int field_diff, unsigned int frame_diff, int bit_mode); + void (*adaptive_combing_new)(unsigned int field_diff, + unsigned int frame_diff); /*adpative_combing_config*/ struct combing_status_s * (*adpative_combing_config)(unsigned int width, diff --git a/drivers/media/deinterlace/film_mode_fmw/film_fw1.c b/drivers/media/deinterlace/film_mode_fmw/film_fw1.c index 6dda53dd5..5b5438aa1 100644 --- a/drivers/media/deinterlace/film_mode_fmw/film_fw1.c +++ b/drivers/media/deinterlace/film_mode_fmw/film_fw1.c @@ -87,6 +87,11 @@ UINT8 FlmVOFSftInt(struct sFlmSftPar *pPar) pPar->flm22_mcdi_min_th = 0; pPar->flm22_max_th = 80; + pPar->flm22_glb_ratio = 24; + pPar->flm22_mcdi_dcnt_th = 30; + pPar->flm22_diff02_add_th = 15000; + pPar->flm22_pd12chk_mode = 1; + pPar->flm22_diff01_ratio = 6; return 0; } @@ -488,10 +493,23 @@ int FlmVOFSftTop(UINT8 *rCmb32Spcl, unsigned short *rPstCYWnd0, ? nDIF02[HISDIFNUM - 1 - nT1] : max_dif02; } - //abc,racing,girl,hqv - pd22_diff12_chk = ((max(nDIF01[HISDIFNUM - 1], nDIF01[HISDIFNUM - 2]) < max_dif02 && (abs(nDIF01[HISDIFNUM - 1] - nDIF01[HISDIFNUM - 2]) > max_dif02 / 2) && + //abc,racing,girl,hqv + if (IS_IC(dil_get_cpuver_flag(), T5DB) || + IS_IC_EF(dil_get_cpuver_flag(), T3)) { + if (pPar->flm22_pd12chk_mode == 0) + pd22_diff12_chk = ((max(nDIF01[HISDIFNUM - 1], nDIF01[HISDIFNUM - 2]) < (max_dif02 + pPar->flm22_diff02_add_th) && (abs(nDIF01[HISDIFNUM - 1] - nDIF01[HISDIFNUM - 2]) > (max(nDIF01[HISDIFNUM - 1], nDIF01[HISDIFNUM - 2]) * pPar->flm22_diff01_ratio / 16)) && + abs(nDIF01[HISDIFNUM - 1] - nDIF01[HISDIFNUM - 2]) < pPar->flm22_diff01_th * 3 && (max(pd22_cnt_pre, pd22_cnt_cur) > max(0, pd22_cnt_th - pPar->flm22_mcdi_dcnt_th) || max(nDIF01[HISDIFNUM - 1], nDIF01[HISDIFNUM - 2]) < (max_dif02 - pPar->flm22_diff02_add_th)) && abs(pre_fld_motnum - glb_field_mot_num) < min(pre_fld_motnum, glb_field_mot_num) * pPar->flm22_glb_ratio / 8) || + (abs(nDIF01[HISDIFNUM - 1] - nDIF01[HISDIFNUM - 2]) < 190000 && abs(nDIF01[HISDIFNUM - 1] - nDIF01[HISDIFNUM - 2]) < nDIF02[HISDIFNUM - 1] * 4 / 5)) ? 1 : 0; + else + pd22_diff12_chk = ((max(nDIF01[HISDIFNUM - 1], nDIF01[HISDIFNUM - 2]) < (max_dif02 + pPar->flm22_diff02_add_th) && (abs(nDIF01[HISDIFNUM - 1] - nDIF01[HISDIFNUM - 2]) > (max(nDIF01[HISDIFNUM - 1], nDIF01[HISDIFNUM - 2]) * pPar->flm22_diff01_ratio / 16)) && + abs(nDIF01[HISDIFNUM - 1] - nDIF01[HISDIFNUM - 2]) < pPar->flm22_diff01_th * 3 && max(pd22_cnt_pre, pd22_cnt_cur) > max(0, pd22_cnt_th - pPar->flm22_mcdi_dcnt_th) && abs(pre_fld_motnum - glb_field_mot_num) < min(pre_fld_motnum, glb_field_mot_num) * pPar->flm22_glb_ratio / 8) || + (abs(nDIF01[HISDIFNUM - 1] - nDIF01[HISDIFNUM - 2]) < 190000 && abs(nDIF01[HISDIFNUM - 1] - nDIF01[HISDIFNUM - 2]) < nDIF02[HISDIFNUM - 1] * 4 / 5)) ? 1 : 0; + } else { + pd22_diff12_chk = ((max(nDIF01[HISDIFNUM - 1], nDIF01[HISDIFNUM - 2]) < max_dif02 && (abs(nDIF01[HISDIFNUM - 1] - nDIF01[HISDIFNUM - 2]) > max_dif02 / 2) && abs(nDIF01[HISDIFNUM - 1] - nDIF01[HISDIFNUM - 2]) < pPar->flm22_diff01_th * 3 && abs(pre_fld_motnum - glb_field_mot_num) < 10000) || (abs(nDIF01[HISDIFNUM - 1] - nDIF01[HISDIFNUM - 2]) < 190000 && abs(nDIF01[HISDIFNUM - 1] - nDIF01[HISDIFNUM - 2]) < nDIF02[HISDIFNUM - 1] * 4 / 5)) ? 1 : 0; + } + if ((pPar->quit_th_en >> 7) & 0x1) //for CVBS_rollingpaper pd22_diff12_chk = 1; /* --------------------------------------------------------- */ diff --git a/drivers/media/deinterlace/film_mode_fmw/film_vof_soft.h b/drivers/media/deinterlace/film_mode_fmw/film_vof_soft.h index 3ef6a537c..ddbf01efd 100644 --- a/drivers/media/deinterlace/film_mode_fmw/film_vof_soft.h +++ b/drivers/media/deinterlace/film_mode_fmw/film_vof_soft.h @@ -147,6 +147,11 @@ struct sFlmSftPar { int flm22_diff01_th; int flm22_mcdi_min_th; int flm22_max_th; + int flm22_glb_ratio; + int flm22_mcdi_dcnt_th; + int flm22_diff02_add_th; + int flm22_pd12chk_mode; + int flm22_diff01_ratio; unsigned int field_count; unsigned short width; unsigned short height; diff --git a/drivers/media/deinterlace/nr_drv.c b/drivers/media/deinterlace/nr_drv.c index ef24bbbfd..6c8c5933a 100644 --- a/drivers/media/deinterlace/nr_drv.c +++ b/drivers/media/deinterlace/nr_drv.c @@ -52,6 +52,9 @@ module_param_named(nr2_en, nr2_en, uint, 0644); static bool dynamic_dm_chk = true; module_param_named(dynamic_dm_chk, dynamic_dm_chk, bool, 0644); +static unsigned int autonr_en = 0x1; +module_param_named(autonr_en, autonr_en, uint, 0644); + static bool nr4ne_en; module_param_named(nr4ne_en, nr4ne_en, bool, 0644); @@ -136,6 +139,10 @@ int global_bs_calc_sw(int *pGbsVldCnt, *pGbsVldFlg = 1; else *pGbsVldFlg = 0; + if (dnr_pr) + pr_info("reg:nCurGbs=%d,pGbs=%d, LR/LL/RR=[%d,%d,%d],dif=%d\n", + nCurGbs, *pGbs, nGbsStatLR, nGbsStatLL, nGbsStatRR, nDif); + *pGbs = nCurGbs; @@ -180,6 +187,9 @@ int hor_blk_ofst_calc_sw(int *pHbOfVldCnt, } else if (nHbOfStatCnt[i] > nMax2) { nMax2 = nHbOfStatCnt[i]; } + if (dnr_pr) + pr_info("nHbOfStatCnt[i]= %d\n", nHbOfStatCnt[i]); + } /* i */ /* decide if offset valid */ @@ -208,9 +218,9 @@ int hor_blk_ofst_calc_sw(int *pHbOfVldCnt, * } */ if (dnr_pr) { - pr_dbg("Max1 = %5d, Max2 = %5d, MaxIdx = %5d, Rat0 = %5d,Rat1 = %5d.\n", + pr_info("Max1 = %5d, Max2 = %5d, MaxIdx = %5d, Rat0 = %5d,Rat1 = %5d.\n", nMax1, nMax2, nMaxIdx, nRat0, nRat1); - pr_dbg("CurHbOfst = %5d, HbOfVldFlg = %d, HbOfVldCnt = %d.\n", + pr_info("CurHbOfst = %5d, HbOfVldFlg = %d, HbOfVldCnt = %d.\n", nCurHbOfst, *pHbOfVldFlg, *pHbOfVldCnt); } @@ -324,8 +334,7 @@ static u32 check_dnr_dm_ctrl(u32 org_val, unsigned short width, } static void dnr_config_op(struct DNR_PARM_s *dnr_parm_p, - unsigned short width, unsigned short height, - const struct reg_acc *op) + const struct reg_acc *op, struct nr_cfg_s *cfg) { unsigned short border_offset = dnr_parm_p->dnr_stat_coef; @@ -334,14 +343,15 @@ static void dnr_config_op(struct DNR_PARM_s *dnr_parm_p, return; } - op->wr(DNR_HVSIZE, (width << 16) | height); + op->wr(DNR_HVSIZE, (cfg->width << 16) | cfg->height); op->wr(DNR_STAT_X_START_END, (((border_offset << 3) & 0x3fff) << 16) | - ((width - ((border_offset << 3) + 1)) & 0x3fff)); + ((cfg->width - ((border_offset << 3) + 1)) & 0x3fff)); op->wr(DNR_STAT_Y_START_END, (((border_offset << 3) & 0x3fff) << 16) | - ((height - ((border_offset << 3) + 1)) & 0x3fff)); + ((cfg->height - ((border_offset << 3) + 1)) & 0x3fff)); op->wr(DNR_DM_CTRL, op->rd(DNR_DM_CTRL) | (1 << 11)); + op->bwr(DNR_CTRL, cfg->linkflag ? 1 : 0, 17, 1); op->bwr(DNR_CTRL, dnr_en ? 1 : 0, 16, 1); /* dm for sd, hd will slower */ if (is_meson_tl1_cpu() || is_meson_tm2_cpu() || @@ -358,11 +368,11 @@ static void dnr_config_op(struct DNR_PARM_s *dnr_parm_p, IS_IC(dil_get_cpuver_flag(), T5D) || IS_IC(dil_get_cpuver_flag(), T5DB) || (cpu_after_eq(MESON_CPU_MAJOR_ID_SC2))) { - if (width > 1280) + if (cfg->width > 1280) op->bwr(DNR_DM_CTRL, 0, 8, 1); else op->bwr(DNR_DM_CTRL, 1, 8, 1); - if (width > 1920 || !dnr_dm_en) + if (cfg->width > 1920 || !dnr_dm_en) op->bwr(DNR_DM_CTRL, 0, 9, 1); else op->bwr(DNR_DM_CTRL, 1, 9, 1); @@ -373,7 +383,7 @@ static void dnr_config_op(struct DNR_PARM_s *dnr_parm_p, op->wr(DNR_CTRL, 0x1dd00); } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX) || is_meson_gxl_cpu()) { /*disable */ - if (width > 1280) { + if (cfg->width > 1280) { op->bwr(DNR_DM_CTRL, 0, 8, 1); /* disable dm for 1080 which will cause pre timeout*/ op->bwr(DNR_DM_CTRL, 0, 9, 1); @@ -382,7 +392,7 @@ static void dnr_config_op(struct DNR_PARM_s *dnr_parm_p, op->bwr(DNR_DM_CTRL, dnr_dm_en, 9, 1); } } else { - if (width >= 1920) + if (cfg->width >= 1920) op->bwr(DNR_DM_CTRL, 0, 9, 1); else op->bwr(DNR_DM_CTRL, dnr_dm_en, 9, 1); @@ -543,16 +553,15 @@ static void cue_config_op(struct CUE_PARM_s *pcue_parm, unsigned short field_typ } } -static void nr_all_config_op(unsigned short width, unsigned short height, - unsigned short field_type, - const struct reg_acc *op) +static void nr_all_config_op(unsigned short field_type, + const struct reg_acc *op, struct nr_cfg_s *cfg) { - nr_param.width = width; - nr_param.height = height; + nr_param.width = cfg->width; + nr_param.height = cfg->height; nr_param.frame_count = 0; nr_param.prog_flag = field_type?false:true; - nr2_config_op(width, height, op); - dnr_config_op(nr_param.pdnr_parm, width, height, op); + nr2_config_op(cfg->width, cfg->height, op); + dnr_config_op(nr_param.pdnr_parm, op, cfg); if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX)) cue_config_op(nr_param.pcue_parm, field_type, op); @@ -563,11 +572,11 @@ static void nr_all_config_op(unsigned short width, unsigned short height, IS_IC(dil_get_cpuver_flag(), T5D) || IS_IC(dil_get_cpuver_flag(), T5DB) || cpu_after_eq(MESON_CPU_MAJOR_ID_SC2)) { - linebuffer_config_op(width, op); - nr4_config_op(nr_param.pnr4_parm, width, height, op); + linebuffer_config_op(cfg->width, op); + nr4_config_op(nr_param.pnr4_parm, cfg->width, cfg->height, op); } if (is_meson_txhd_cpu()) - linebuffer_config_op(width, op); + linebuffer_config_op(cfg->width, op); } bool secam_cfr_en = true; @@ -807,6 +816,100 @@ static void noise_meter_process_op(struct NR4_PARM_s *nr4_param_p, nr4_param_p->sw_nr4_field_sad[1] = field_sad; } +//auto global tnr +//function : update reg_MATNR_mtn_lp/hp_Ygain, +// reg_MATNR_mtn_lp/hp_Cgain by motion_info and apl +//input : diff_sum, apl +//output : mtn_lp/hp_Ygain, mtn_lp/hp_Cgain +static void autonr_process_op(struct AUTONR_PARM_S *autonr_param_p, + unsigned short input_width, + unsigned short input_height, + const struct reg_acc *op) +{ + unsigned int idx; + u64 motion_sum; + int apl_idx; //3bit + u64 diff_sum; + + diff_sum = op->rd(DIPD_RO_COMB_0); + + //diff_sum norm + /*coverity[SIGN_EXTENSION] misjudgment*/ + motion_sum = div64_u64(diff_sum * (1920 * 1080), + (input_height * input_width)); + if (autonr_en & 0x10) + pr_info("%s start#### diff_sum=0x%llx,motion_sum=0x%llx\n", __func__, + diff_sum, motion_sum); + + motion_sum = motion_sum >> 12; + if (autonr_en & 0x10) + pr_info("%s motion_sum=0x%llx\n", __func__, motion_sum); + + //get mtn gain + apl_idx = get_lum_ave(); + if (autonr_en & 0x10) + pr_info("%s lum_ave=%d\n", __func__, apl_idx); + + if (apl_idx <= 0) { + apl_idx = 0; + } else { + apl_idx = apl_idx >> 5; + if (apl_idx >= 7) + apl_idx = 7; + } + if (autonr_en & 0x10) + pr_info("%s apl_idx=%d\n", __func__, apl_idx); + //apl control + motion_sum = (motion_sum * autonr_param_p->apl_gain[apl_idx] + 16) >> 5; + if (autonr_en & 0x10) + pr_info("%s end#### motion_sum=0x%llx\n", __func__, motion_sum); + + if (motion_sum <= autonr_param_p->motion_th[0]) + idx = 0; + else if (motion_sum <= autonr_param_p->motion_th[1]) + idx = 1; + else if (motion_sum <= autonr_param_p->motion_th[2]) + idx = 2; + else if (motion_sum <= autonr_param_p->motion_th[3]) + idx = 3; + else if (motion_sum <= autonr_param_p->motion_th[4]) + idx = 4; + else if (motion_sum <= autonr_param_p->motion_th[5]) + idx = 5; + else if (motion_sum <= autonr_param_p->motion_th[6]) + idx = 6; + else if (motion_sum <= autonr_param_p->motion_th[7]) + idx = 7; + else if (motion_sum <= autonr_param_p->motion_th[8]) + idx = 8; + else if (motion_sum <= autonr_param_p->motion_th[9]) + idx = 9; + else if (motion_sum <= autonr_param_p->motion_th[10]) + idx = 10; + else if (motion_sum <= autonr_param_p->motion_th[11]) + idx = 11; + else if (motion_sum <= autonr_param_p->motion_th[12]) + idx = 12; + else if (motion_sum <= autonr_param_p->motion_th[13]) + idx = 13; + else if (motion_sum <= autonr_param_p->motion_th[14]) + idx = 14; + else + idx = 15; + + op->bwr(NR2_MATNR_MTN_GAIN, + autonr_param_p->motion_lp_ygain[idx], 0, 8); + op->bwr(NR2_MATNR_MTN_GAIN, + autonr_param_p->motion_lp_cgain[idx], 8, 8); + op->bwr(NR2_MATNR_MTN_GAIN, + autonr_param_p->motion_hp_ygain[idx], 16, 8); + op->bwr(NR2_MATNR_MTN_GAIN, + autonr_param_p->motion_hp_cgain[idx], 24, 8); + if (autonr_en & 0x10) + pr_info("%s idx=%d.h=%d,GAIN=%d\n", __func__, + idx, input_height, op->rd(NR2_MATNR_MTN_GAIN)); +} + //sort from largest to smallest static void sort(int *data, int datanum) { @@ -1086,7 +1189,9 @@ static void luma_enhancement_process_op(struct NR4_PARM_s *nr4_param_p, } static void dnr_process_op(struct DNR_PARM_s *pdnrprm, - const struct reg_acc *op) + const struct reg_acc *op, + unsigned short nexsizein, + unsigned short neysizein) { static int ro_gbs_stat_lr = 0, ro_gbs_stat_ll = 0, ro_gbs_stat_rr = 0, ro_gbs_stat_dif = 0, ro_gbs_stat_cnt = 0; @@ -1095,6 +1200,7 @@ static void dnr_process_op(struct DNR_PARM_s *pdnrprm, */ #ifdef DNR_HV_SHIFT int ro_hbof_stat_cnt[32], ro_vbof_stat_cnt[32], i = 0; + int nCol, nRow; #endif int ll, lr; @@ -1103,10 +1209,7 @@ static void dnr_process_op(struct DNR_PARM_s *pdnrprm, return; } - if (is_meson_tl1_cpu() || is_meson_tm2_cpu() || - IS_IC(dil_get_cpuver_flag(), T5) || - IS_IC(dil_get_cpuver_flag(), T5D) || - IS_IC(dil_get_cpuver_flag(), T5DB)) { + if (is_meson_tl1_cpu()) { ll = op->rd(DNR_RO_GBS_STAT_LR); lr = op->rd(DNR_RO_GBS_STAT_LL); } else { @@ -1145,22 +1248,25 @@ static void dnr_process_op(struct DNR_PARM_s *pdnrprm, pdnrprm->prm_gbs_bsdifthd, pdnrprm->prm_gbs_calcmod); #ifdef DNR_HV_SHIFT + nCol = nexsizein; + nRow = neysizein; + for (i = 0; i < 32; i++) ro_hbof_stat_cnt[i] = op->rd(DNR_RO_HBOF_STAT_CNT_0 + i); for (i = 0; i < 32; i++) ro_vbof_stat_cnt[i] = op->rd(DNR_RO_VBOF_STAT_CNT_0 + i); - hor_blk_ofst_calc_sw(&pdnrprm->sw_hbof_vld_cnt, - &pdnrprm->sw_hbof_vld_flg, - &pdnrprm->sw_hbof, - ro_hbof_stat_cnt, - 0, - nCol-1, - pdnrprm->prm_hbof_minthd, - pdnrprm->prm_hbof_ratthd0, - pdnrprm->prm_hbof_ratthd1, - pdnrprm->prm_hbof_vldcntthd, - nRow, - nCol); + hor_blk_ofst_calc_sw(&pdnrprm->sw_hbof_vld_cnt, + &pdnrprm->sw_hbof_vld_flg, + &pdnrprm->sw_hbof, + ro_hbof_stat_cnt, + 0, + nCol - 1, + pdnrprm->prm_hbof_minthd, + pdnrprm->prm_hbof_ratthd0, + pdnrprm->prm_hbof_ratthd1, + pdnrprm->prm_hbof_vldcntthd, + nRow, + nCol); ver_blk_ofst_calc_sw(&pdnrprm->sw_vbof_vld_cnt, &pdnrprm->sw_vbof_vld_flg, @@ -1193,7 +1299,7 @@ static void dnr_process_op(struct DNR_PARM_s *pdnrprm, op->wr(DNR_GBS, (pdnrprm->sw_vbof_vld_flg == 1 && pdnrprm->sw_gbs_vld_flg == 1) ? pdnrprm->sw_gbs : 0); - } else if (pdnrprm->prm_sw_gbs_ctrl == 1) { + } else if (pdnrprm->prm_sw_gbs_ctrl == 3) { op->bwr(DNR_BLK_OFFST, pdnrprm->sw_hbof_vld_flg == 1 ? pdnrprm->sw_hbof : 0, 4, 3); @@ -1205,6 +1311,10 @@ static void dnr_process_op(struct DNR_PARM_s *pdnrprm, pdnrprm->sw_vbof_vld_flg == 1 && pdnrprm->sw_gbs_vld_flg == 1) ? pdnrprm->sw_gbs : 0); } + if (dnr_pr) + pr_info("reg:nCurGbs=%d,hbof/vld=[%d,%d],sw_gbs_ctrl=%d\n", + pdnrprm->sw_gbs, pdnrprm->sw_hbof_vld_flg, + pdnrprm->sw_gbs_vld_flg, pdnrprm->prm_sw_gbs_ctrl); } static bool invert_cue_phase; @@ -1289,7 +1399,7 @@ void cue_int_op(struct vframe_s *vf, const struct reg_acc *op) cue_en = false; } if (cue_en_last != cue_en) { - di_pr_info("cue:chg1:%d->%d\n", cue_en_last, cue_en); + di_print("cue:chg1:%d->%d\n", cue_en_last, cue_en); cue_en_last = cue_en; } /*close cue when cue disable*/ @@ -1384,8 +1494,8 @@ void adaptive_cue_adjust_op(unsigned int frame_diff, unsigned int field_diff, cue_en = false; if (cue_en != cue_en_last) { - di_pr_info("cue_en:chg2:%d->%d\n", cue_en_last, cue_en); - di_pr_info("\t%d,%d,%d\n", + di_print("cue_en:chg2:%d->%d\n", cue_en_last, cue_en); + di_print("\t%d,%d,%d\n", pcue_parm->frame_count, pcue_parm->field_count1, pcue_parm->glb_mot_fieldnum); @@ -1475,7 +1585,8 @@ static void nr_process_in_irq_op(const struct reg_acc *op) cue_glb_mot_check_en) cue_process_irq_op(op); if (dnr_en) - dnr_process_op(&dnr_param, op); + dnr_process_op(&dnr_param, op, nr_param.width, + nr_param.height); if (is_meson_txlx_cpu() || is_meson_g12a_cpu() || is_meson_g12a_cpu() || is_meson_tl1_cpu() || is_meson_sm1_cpu() || is_meson_tm2_cpu() || @@ -1490,6 +1601,10 @@ static void nr_process_in_irq_op(const struct reg_acc *op) if (IS_IC(dil_get_cpuver_flag(), T3) && nr4ne_en) noise_meter2_process(nr_param.pnr4_neparm, nr_param.width, nr_param.height); + if (((IS_IC_EF(dil_get_cpuver_flag(), T3)) || + IS_IC(dil_get_cpuver_flag(), T5DB)) && autonr_en) + autonr_process_op(nr_param.pautonr_parm, + nr_param.width, nr_param.height, op); } static dnr_param_t dnr_params[] = { @@ -1711,6 +1826,386 @@ static void nr4_param_init(struct NR4_PARM_s *nr4_parm_p) nr4_parm_p->sw_dm_scene_change_en = 0; } +static autonr_param_t autonr_params[AUTONR_PARAMS_NUM]; +static void autonr_params_init_th(struct AUTONR_PARM_S *autonr_parm_p) +{ + autonr_params[0].name = "motion_th[0]"; + autonr_params[0].addr = &autonr_parm_p->motion_th[0]; + autonr_params[1].name = "motion_th[1]"; + autonr_params[1].addr = &autonr_parm_p->motion_th[1]; + autonr_params[2].name = "motion_th[2]"; + autonr_params[2].addr = &autonr_parm_p->motion_th[2]; + autonr_params[3].name = "motion_th[3]"; + autonr_params[3].addr = &autonr_parm_p->motion_th[3]; + autonr_params[4].name = "motion_th[4]"; + autonr_params[4].addr = &autonr_parm_p->motion_th[4]; + autonr_params[5].name = "motion_th[5]"; + autonr_params[5].addr = &autonr_parm_p->motion_th[5]; + autonr_params[6].name = "motion_th[6]"; + autonr_params[6].addr = &autonr_parm_p->motion_th[6]; + autonr_params[7].name = "motion_th[7]"; + autonr_params[7].addr = &autonr_parm_p->motion_th[7]; + autonr_params[8].name = "motion_th[8]"; + autonr_params[8].addr = &autonr_parm_p->motion_th[8]; + autonr_params[9].name = "motion_th[9]"; + autonr_params[9].addr = &autonr_parm_p->motion_th[9]; + autonr_params[10].name = "motion_th[10]"; + autonr_params[10].addr = &autonr_parm_p->motion_th[10]; + autonr_params[11].name = "motion_th[11]"; + autonr_params[11].addr = &autonr_parm_p->motion_th[11]; + autonr_params[12].name = "motion_th[12]"; + autonr_params[12].addr = &autonr_parm_p->motion_th[12]; + autonr_params[13].name = "motion_th[13]"; + autonr_params[13].addr = &autonr_parm_p->motion_th[13]; + autonr_params[14].name = "motion_th[14]"; + autonr_params[14].addr = &autonr_parm_p->motion_th[14]; +}; + +static void autonr_params_init_lp_ygain(struct AUTONR_PARM_S *autonr_parm_p) +{ + autonr_params[15].name = "motion_lp_ygain[0]"; + autonr_params[15].addr = &autonr_parm_p->motion_lp_ygain[0]; + autonr_params[16].name = "motion_lp_ygain[1]"; + autonr_params[16].addr = &autonr_parm_p->motion_lp_ygain[1]; + autonr_params[17].name = "motion_lp_ygain[2]"; + autonr_params[17].addr = &autonr_parm_p->motion_lp_ygain[2]; + autonr_params[18].name = "motion_lp_ygain[3]"; + autonr_params[18].addr = &autonr_parm_p->motion_lp_ygain[3]; + autonr_params[19].name = "motion_lp_ygain[4]"; + autonr_params[19].addr = &autonr_parm_p->motion_lp_ygain[4]; + autonr_params[20].name = "motion_lp_ygain[5]"; + autonr_params[20].addr = &autonr_parm_p->motion_lp_ygain[5]; + autonr_params[21].name = "motion_lp_ygain[6]"; + autonr_params[21].addr = &autonr_parm_p->motion_lp_ygain[6]; + autonr_params[22].name = "motion_lp_ygain[7]"; + autonr_params[22].addr = &autonr_parm_p->motion_lp_ygain[7]; + autonr_params[23].name = "motion_lp_ygain[8]"; + autonr_params[23].addr = &autonr_parm_p->motion_lp_ygain[8]; + autonr_params[24].name = "motion_lp_ygain[9]"; + autonr_params[24].addr = &autonr_parm_p->motion_lp_ygain[9]; + autonr_params[25].name = "motion_lp_ygain[10]"; + autonr_params[25].addr = &autonr_parm_p->motion_lp_ygain[10]; + autonr_params[26].name = "motion_lp_ygain[11]"; + autonr_params[26].addr = &autonr_parm_p->motion_lp_ygain[11]; + autonr_params[27].name = "motion_lp_ygain[12]"; + autonr_params[27].addr = &autonr_parm_p->motion_lp_ygain[12]; + autonr_params[28].name = "motion_lp_ygain[13]"; + autonr_params[28].addr = &autonr_parm_p->motion_lp_ygain[13]; + autonr_params[29].name = "motion_lp_ygain[14]"; + autonr_params[29].addr = &autonr_parm_p->motion_lp_ygain[14]; + autonr_params[30].name = "motion_lp_ygain[15]"; + autonr_params[30].addr = &autonr_parm_p->motion_lp_ygain[15]; +}; + +static void autonr_params_init_hp_ygain(struct AUTONR_PARM_S *autonr_parm_p) +{ + autonr_params[31].name = "motion_hp_ygain[0]"; + autonr_params[31].addr = &autonr_parm_p->motion_hp_ygain[0]; + autonr_params[32].name = "motion_hp_ygain[1]"; + autonr_params[32].addr = &autonr_parm_p->motion_hp_ygain[1]; + autonr_params[33].name = "motion_hp_ygain[2]"; + autonr_params[33].addr = &autonr_parm_p->motion_hp_ygain[2]; + autonr_params[34].name = "motion_hp_ygain[3]"; + autonr_params[34].addr = &autonr_parm_p->motion_hp_ygain[3]; + autonr_params[35].name = "motion_hp_ygain[4]"; + autonr_params[35].addr = &autonr_parm_p->motion_hp_ygain[4]; + autonr_params[36].name = "motion_hp_ygain[5]"; + autonr_params[36].addr = &autonr_parm_p->motion_hp_ygain[5]; + autonr_params[37].name = "motion_hp_ygain[6]"; + autonr_params[37].addr = &autonr_parm_p->motion_hp_ygain[6]; + autonr_params[38].name = "motion_hp_ygain[7]"; + autonr_params[38].addr = &autonr_parm_p->motion_hp_ygain[7]; + autonr_params[39].name = "motion_hp_ygain[8]"; + autonr_params[39].addr = &autonr_parm_p->motion_hp_ygain[8]; + autonr_params[40].name = "motion_hp_ygain[9]"; + autonr_params[40].addr = &autonr_parm_p->motion_hp_ygain[9]; + autonr_params[41].name = "motion_hp_ygain[10]"; + autonr_params[41].addr = &autonr_parm_p->motion_hp_ygain[10]; + autonr_params[42].name = "motion_hp_ygain[11]"; + autonr_params[42].addr = &autonr_parm_p->motion_hp_ygain[11]; + autonr_params[43].name = "motion_hp_ygain[12]"; + autonr_params[43].addr = &autonr_parm_p->motion_hp_ygain[12]; + autonr_params[44].name = "motion_hp_ygain[13]"; + autonr_params[44].addr = &autonr_parm_p->motion_hp_ygain[13]; + autonr_params[45].name = "motion_hp_ygain[14]"; + autonr_params[45].addr = &autonr_parm_p->motion_hp_ygain[14]; + autonr_params[46].name = "motion_hp_ygain[15]"; + autonr_params[46].addr = &autonr_parm_p->motion_hp_ygain[15]; +}; + +static void autonr_params_init_lp_cgain(struct AUTONR_PARM_S *autonr_parm_p) +{ + autonr_params[47].name = "motion_lp_cgain[0]"; + autonr_params[47].addr = &autonr_parm_p->motion_lp_cgain[0]; + autonr_params[48].name = "motion_lp_cgain[1]"; + autonr_params[48].addr = &autonr_parm_p->motion_lp_cgain[1]; + autonr_params[49].name = "motion_lp_cgain[2]"; + autonr_params[49].addr = &autonr_parm_p->motion_lp_cgain[2]; + autonr_params[50].name = "motion_lp_cgain[3]"; + autonr_params[50].addr = &autonr_parm_p->motion_lp_cgain[3]; + autonr_params[51].name = "motion_lp_cgain[4]"; + autonr_params[51].addr = &autonr_parm_p->motion_lp_cgain[4]; + autonr_params[52].name = "motion_lp_cgain[5]"; + autonr_params[52].addr = &autonr_parm_p->motion_lp_cgain[5]; + autonr_params[53].name = "motion_lp_cgain[6]"; + autonr_params[53].addr = &autonr_parm_p->motion_lp_cgain[6]; + autonr_params[54].name = "motion_lp_cgain[7]"; + autonr_params[54].addr = &autonr_parm_p->motion_lp_cgain[7]; + autonr_params[55].name = "motion_lp_cgain[8]"; + autonr_params[55].addr = &autonr_parm_p->motion_lp_cgain[8]; + autonr_params[56].name = "motion_lp_cgain[9]"; + autonr_params[56].addr = &autonr_parm_p->motion_lp_cgain[9]; + autonr_params[57].name = "motion_lp_cgain[10]"; + autonr_params[57].addr = &autonr_parm_p->motion_lp_cgain[10]; + autonr_params[58].name = "motion_lp_cgain[11]"; + autonr_params[58].addr = &autonr_parm_p->motion_lp_cgain[11]; + autonr_params[59].name = "motion_lp_cgain[12]"; + autonr_params[59].addr = &autonr_parm_p->motion_lp_cgain[12]; + autonr_params[60].name = "motion_lp_cgain[13]"; + autonr_params[60].addr = &autonr_parm_p->motion_lp_cgain[13]; + autonr_params[61].name = "motion_lp_cgain[14]"; + autonr_params[61].addr = &autonr_parm_p->motion_lp_cgain[14]; + autonr_params[62].name = "motion_lp_cgain[15]"; + autonr_params[62].addr = &autonr_parm_p->motion_lp_cgain[15]; +}; + +static void autonr_params_init_hp_cgain(struct AUTONR_PARM_S *autonr_parm_p) +{ + autonr_params[63].name = "motion_hp_cgain[0]"; + autonr_params[63].addr = &autonr_parm_p->motion_hp_cgain[0]; + autonr_params[64].name = "motion_hp_cgain[1]"; + autonr_params[64].addr = &autonr_parm_p->motion_hp_cgain[1]; + autonr_params[65].name = "motion_hp_cgain[2]"; + autonr_params[65].addr = &autonr_parm_p->motion_hp_cgain[2]; + autonr_params[66].name = "motion_hp_cgain[3]"; + autonr_params[66].addr = &autonr_parm_p->motion_hp_cgain[3]; + autonr_params[67].name = "motion_hp_cgain[4]"; + autonr_params[67].addr = &autonr_parm_p->motion_hp_cgain[4]; + autonr_params[68].name = "motion_hp_cgain[5]"; + autonr_params[68].addr = &autonr_parm_p->motion_hp_cgain[5]; + autonr_params[69].name = "motion_hp_cgain[6]"; + autonr_params[69].addr = &autonr_parm_p->motion_hp_cgain[6]; + autonr_params[70].name = "motion_hp_cgain[7]"; + autonr_params[70].addr = &autonr_parm_p->motion_hp_cgain[7]; + autonr_params[71].name = "motion_hp_cgain[8]"; + autonr_params[71].addr = &autonr_parm_p->motion_hp_cgain[8]; + autonr_params[72].name = "motion_hp_cgain[9]"; + autonr_params[72].addr = &autonr_parm_p->motion_hp_cgain[9]; + autonr_params[73].name = "motion_hp_cgain[10]"; + autonr_params[73].addr = &autonr_parm_p->motion_hp_cgain[10]; + autonr_params[74].name = "motion_hp_cgain[11]"; + autonr_params[74].addr = &autonr_parm_p->motion_hp_cgain[11]; + autonr_params[75].name = "motion_hp_cgain[12]"; + autonr_params[75].addr = &autonr_parm_p->motion_hp_cgain[12]; + autonr_params[76].name = "motion_hp_cgain[13]"; + autonr_params[76].addr = &autonr_parm_p->motion_hp_cgain[13]; + autonr_params[77].name = "motion_hp_cgain[14]"; + autonr_params[77].addr = &autonr_parm_p->motion_hp_cgain[14]; + autonr_params[78].name = "motion_hp_cgain[15]"; + autonr_params[78].addr = &autonr_parm_p->motion_hp_cgain[15]; +}; + +static void autonr_params_init_apl(struct AUTONR_PARM_S *autonr_parm_p) +{ + autonr_params[79].name = "apl_gain[0]"; + autonr_params[79].addr = &autonr_parm_p->apl_gain[0]; + autonr_params[80].name = "apl_gain[1]"; + autonr_params[80].addr = &autonr_parm_p->apl_gain[1]; + autonr_params[81].name = "apl_gain[2]"; + autonr_params[81].addr = &autonr_parm_p->apl_gain[2]; + autonr_params[82].name = "apl_gain[3]"; + autonr_params[82].addr = &autonr_parm_p->apl_gain[3]; + autonr_params[83].name = "apl_gain[4]"; + autonr_params[83].addr = &autonr_parm_p->apl_gain[4]; + autonr_params[84].name = "apl_gain[5]"; + autonr_params[84].addr = &autonr_parm_p->apl_gain[5]; + autonr_params[85].name = "apl_gain[6]"; + autonr_params[85].addr = &autonr_parm_p->apl_gain[6]; + autonr_params[86].name = "apl_gain[7]"; + autonr_params[86].addr = &autonr_parm_p->apl_gain[7]; +}; + +static ssize_t autonr_param_store(struct device *dev, + struct device_attribute *attr, + const char *buff, size_t count) +{ + long i = 0, value = 0; + char *parm[17] = {NULL}, *buf_orig; + + buf_orig = kstrdup(buff, GFP_KERNEL); + parse_cmd_params(buf_orig, (char **)(&parm)); + + if (!strcmp(parm[0], "motion_th")) { + for (i = 0; i < 15; i++) { + if (parm[i + 1]) { + if (kstrtol(parm[i + 1], 10, &value) < 0) + pr_err("DI: input value error.\n"); + *autonr_params[i].addr = value; + } + if (autonr_en & 0x20) + pr_info("%lx ,%x\n", i, *autonr_params[i].addr); + } + } else if (!strcmp(parm[0], "motion_lp_ygain")) { + for (i = 0; i < 16; i++) { + if (parm[i + 1]) { + if (kstrtol(parm[i + 1], 10, &value) < 0) + pr_err("DI: input value error.\n"); + *autonr_params[i + 15].addr = value; + } + if (autonr_en & 0x20) + pr_info("%lx,%x\n", i + 15, + *autonr_params[i + 15].addr); + } + } else if (!strcmp(parm[0], "motion_hp_ygain")) { + for (i = 0; i < 16; i++) { + if (parm[i + 1]) { + if (kstrtol(parm[i + 1], 10, &value) < 0) + pr_err("DI: input value error.\n"); + *autonr_params[i + 31].addr = value; + } + if (autonr_en & 0x20) + pr_info("%lx,%x\n", i + 31, + *autonr_params[i + 31].addr); + } + } else if (!strcmp(parm[0], "motion_lp_cgain")) { + for (i = 0; i < 16; i++) { + if (parm[i + 1]) { + if (kstrtol(parm[i + 1], 10, &value) < 0) + pr_err("DI: input value error.\n"); + *autonr_params[i + 47].addr = value; + } + if (autonr_en & 0x20) + pr_info("%lx,%x\n", i + 47, + *autonr_params[i + 47].addr); + } + } else if (!strcmp(parm[0], "motion_hp_cgain")) { + for (i = 0; i < 16; i++) { + if (parm[i + 1]) { + if (kstrtol(parm[i + 1], 10, &value) < 0) + pr_err("DI: input value error.\n"); + *autonr_params[i + 63].addr = value; + } + if (autonr_en & 0x20) + pr_info("%lx,%x\n", i + 63, + *autonr_params[i + 63].addr); + } + } else if (!strcmp(parm[0], "apl_gain")) { + for (i = 0; i < 8; i++) { + if (parm[i + 1]) { + if (kstrtol(parm[i + 1], 10, &value) < 0) + pr_err("DI: input value error.\n"); + *autonr_params[i + 79].addr = value; + } + if (autonr_en & 0x20) + pr_info("%lx,%x\n", i + 79, + *autonr_params[i + 79].addr); + } + } else { + pr_info(" null\n"); + } + + kfree(buf_orig); + return count; +} + +static ssize_t autonr_param_show(struct device *dev, + struct device_attribute *attr, + char *buff) +{ + ssize_t len = 0; + int i = 0; + + len += sprintf(buff + len, "%s=%d", "motion_th", + *autonr_params[0].addr); + for (i = 1; i < 15; i++) { + if (IS_ERR_OR_NULL(autonr_params[i].name) || + IS_ERR_OR_NULL(autonr_params[i].addr)) + continue; + len += sprintf(buff + len, ",%d", *autonr_params[i].addr); + } + + len += sprintf(buff + len, "\n%s=%d", "motion_lp_ygain", + *autonr_params[15].addr); + for (i = 16; i < 31; i++) { + if (IS_ERR_OR_NULL(autonr_params[i].name) || + IS_ERR_OR_NULL(autonr_params[i].addr)) + continue; + len += sprintf(buff + len, ",%d", *autonr_params[i].addr); + } + + len += sprintf(buff + len, "\n%s=%d", "motion_hp_ygain", + *autonr_params[31].addr); + for (i = 32; i < 47; i++) { + if (IS_ERR_OR_NULL(autonr_params[i].name) || + IS_ERR_OR_NULL(autonr_params[i].addr)) + continue; + len += sprintf(buff + len, ",%d", *autonr_params[i].addr); + } + + len += sprintf(buff + len, "\n%s=%d", "motion_lp_cgain", + *autonr_params[47].addr); + for (i = 48; i < 63; i++) { + if (IS_ERR_OR_NULL(autonr_params[i].name) || + IS_ERR_OR_NULL(autonr_params[i].addr)) + continue; + len += sprintf(buff + len, ",%d", *autonr_params[i].addr); + } + + len += sprintf(buff + len, "\n%s=%d", "motion_hp_cgain", + *autonr_params[63].addr); + for (i = 64; i < 79; i++) { + if (IS_ERR_OR_NULL(autonr_params[i].name) || + IS_ERR_OR_NULL(autonr_params[i].addr)) + continue; + len += sprintf(buff + len, ",%d", *autonr_params[i].addr); + } + + len += sprintf(buff + len, "\n%s=%d", "apl_gain", + *autonr_params[79].addr); + for (i = 80; i < 87; i++) { + if (IS_ERR_OR_NULL(autonr_params[i].name) || + IS_ERR_OR_NULL(autonr_params[i].addr)) + continue; + len += sprintf(buff + len, ",%d", *autonr_params[i].addr); + } + len += sprintf(buff + len, "\n"); + return len; +} + +static DEVICE_ATTR(autonr_param, 0664, autonr_param_show, autonr_param_store); + +static void autonr_param_init(struct AUTONR_PARM_S *autonr_parm_p) +{ + int k = 0; + + for (k = 0; k < 16; k++) + autonr_parm_p->motion_lp_ygain[k] = 64; + for (k = 0; k < 16; k++) + autonr_parm_p->motion_hp_ygain[k] = 64; + for (k = 0; k < 16; k++) + autonr_parm_p->motion_lp_cgain[k] = 64; + for (k = 0; k < 16; k++) + autonr_parm_p->motion_hp_cgain[k] = 64; + for (k = 0; k < 8; k++) + autonr_parm_p->apl_gain[k] = 32; + + autonr_parm_p->motion_th[0] = 0; + autonr_parm_p->motion_th[1] = 1; + autonr_parm_p->motion_th[2] = 2; + autonr_parm_p->motion_th[3] = 4; + autonr_parm_p->motion_th[4] = 6; + autonr_parm_p->motion_th[5] = 8; + autonr_parm_p->motion_th[6] = 9; + autonr_parm_p->motion_th[7] = 10; + autonr_parm_p->motion_th[8] = 12; + autonr_parm_p->motion_th[9] = 14; + autonr_parm_p->motion_th[10] = 16; + autonr_parm_p->motion_th[11] = 18; + autonr_parm_p->motion_th[12] = 20; + autonr_parm_p->motion_th[13] = 34; + autonr_parm_p->motion_th[14] = 30; +} + static void nr4_neparam_init(struct NR4_NEPARM_S *nr4_neparm_p) { int k = 0; @@ -1749,7 +2244,7 @@ static void cue_param_init(struct CUE_PARM_s *cue_parm_p) } static int dnr_prm_init(DNR_PRM_t *pPrm) { - pPrm->prm_sw_gbs_ctrl = 0; + pPrm->prm_sw_gbs_ctrl = 1; /* * 0: update gbs, 1: update hoffst & gbs, * 2: update voffst & gbs, 3: update all (hoffst & voffst & gbs). @@ -1764,7 +2259,7 @@ static int dnr_prm_init(DNR_PRM_t *pPrm) pPrm->prm_gbs_difthd[0] = 25; pPrm->prm_gbs_difthd[1] = 75; pPrm->prm_gbs_difthd[2] = 125; - pPrm->prm_gbs_bsdifthd = 1; + pPrm->prm_gbs_bsdifthd = 2; pPrm->prm_gbs_calcmod = 1; /* 0:dif0, 1:dif1, 2: dif2 */ pPrm->sw_gbs = 0; @@ -1991,11 +2486,15 @@ void nr_drv_uninit(struct device *dev) vfree(nr_param.pnr4_neparm); nr_param.pnr4_neparm = NULL; } - + if (nr_param.pautonr_parm) { + vfree(nr_param.pautonr_parm); + nr_param.pautonr_parm = NULL; + } device_remove_file(dev, &dev_attr_nr4_param); device_remove_file(dev, &dev_attr_dnr_param); device_remove_file(dev, &dev_attr_nr_debug); device_remove_file(dev, &dev_attr_secam); + device_remove_file(dev, &dev_attr_autonr_param); } void nr_drv_init(struct device *dev) { @@ -2029,7 +2528,22 @@ void nr_drv_init(struct device *dev) else nr4_neparam_init(nr_param.pnr4_neparm); } - + if (((IS_IC_EF(dil_get_cpuver_flag(), T3)) || + IS_IC(dil_get_cpuver_flag(), T5DB)) && autonr_en) { + nr_param.pautonr_parm = vmalloc(sizeof(*nr_param.pautonr_parm)); + if (IS_ERR(nr_param.pautonr_parm)) { + pr_err("%s allocate autonr parm error.\n", __func__); + } else { + autonr_params_init_th(nr_param.pautonr_parm); + autonr_params_init_lp_ygain(nr_param.pautonr_parm); + autonr_params_init_hp_ygain(nr_param.pautonr_parm); + autonr_params_init_lp_cgain(nr_param.pautonr_parm); + autonr_params_init_hp_cgain(nr_param.pautonr_parm); + autonr_params_init_apl(nr_param.pautonr_parm); + autonr_param_init(nr_param.pautonr_parm); + device_create_file(dev, &dev_attr_autonr_param); + } + } dnr_prm_init(&dnr_param); nr_param.pdnr_parm = &dnr_param; device_create_file(dev, &dev_attr_dnr_param); @@ -2056,10 +2570,9 @@ static void nr_process_in_irq(void) nr_process_in_irq_op(&dio_pre_regset); } -static void nr_all_config(unsigned short ncol, unsigned short nrow, - unsigned short type) +static void nr_all_config(unsigned short type, struct nr_cfg_s *cfg) { - nr_all_config_op(ncol, nrow, type, &dio_pre_regset); + nr_all_config_op(type, &dio_pre_regset, cfg); } static void cue_int(struct vframe_s *vf) diff --git a/drivers/media/deinterlace/nr_drv.h b/drivers/media/deinterlace/nr_drv.h index ce825ff5e..609cfc97b 100644 --- a/drivers/media/deinterlace/nr_drv.h +++ b/drivers/media/deinterlace/nr_drv.h @@ -26,9 +26,13 @@ struct nr_param_s { int *addr; }; +#define AUTONR_PARAMS_NUM (90) //87 #define NR4_PARAMS_NUM (30) //25 #define dnr_param_t struct nr_param_s #define nr4_param_t struct nr_param_s +#define autonr_param_t struct nr_param_s + +#define DNR_HV_SHIFT struct DNR_PARM_s { int prm_sw_gbs_ctrl; @@ -82,6 +86,15 @@ struct NR4_PARM_s { unsigned int sw_dm_scene_change_en; }; +struct AUTONR_PARM_S { + int motion_th[15]; + int motion_lp_ygain[16]; + int motion_hp_ygain[16]; + int motion_lp_cgain[16]; + int motion_hp_cgain[16]; + int apl_gain[8]; +}; + struct NR4_NEPARM_S { int nr4_ne_spatial_th; unsigned int nr4_ne_spatial_pixel_step; @@ -138,6 +151,7 @@ struct NR_PARM_s { bool prog_flag; struct DNR_PARM_s *pdnr_parm; struct NR4_PARM_s *pnr4_parm; + struct AUTONR_PARM_S *pautonr_parm; struct NR4_NEPARM_S *pnr4_neparm; struct CUE_PARM_s *pcue_parm; struct NR_CTRL_REGS_s *pnr_regs; diff --git a/drivers/media/deinterlace/pulldown_drv.c b/drivers/media/deinterlace/pulldown_drv.c index b4d11708b..016fe0ecd 100644 --- a/drivers/media/deinterlace/pulldown_drv.c +++ b/drivers/media/deinterlace/pulldown_drv.c @@ -417,9 +417,9 @@ static struct pd_param_s pd_params[] = { &(pd_param.flm22_comlev) }, { "flm22_comlev1", &(pd_param.flm22_comlev1) }, - { "flm22_com_num", + { "flm22_comnum", &pd_param.flm22_comnum }, - { "flm22_com_th", + { "flm22_comth", &pd_param.flm22_comth }, { "flm22_dif01_avgth", &(pd_param.flm22_dif01_avgth) }, @@ -449,6 +449,16 @@ static struct pd_param_s pd_params[] = { &pd_param.flm22_mcdi_min_th }, { "flm22_max_th", &pd_param.flm22_max_th }, + { "flm22_glb_ratio", + &pd_param.flm22_glb_ratio }, + { "flm22_mcdi_dcnt_th", + &pd_param.flm22_mcdi_dcnt_th }, + { "flm22_diff02_add_th", + &pd_param.flm22_diff02_add_th }, + { "flm22_pd12chk_mode", + &pd_param.flm22_pd12chk_mode }, + { "flm22_diff01_ratio", + &pd_param.flm22_diff01_ratio }, { "", NULL } }; diff --git a/drivers/media/di_local/di_local.c b/drivers/media/di_local/di_local.c index bc1da3ffc..665034800 100644 --- a/drivers/media/di_local/di_local.c +++ b/drivers/media/di_local/di_local.c @@ -275,8 +275,10 @@ int pvpp_display(struct vframe_s *vfm, { int ret = -1; - if (dil_api && dil_api->pre_vpp_link_display) + if (dil_api && dil_api->pre_vpp_link_display) { ret = dil_api->pre_vpp_link_display(vfm, in_para, out_para); + return ret; + } PR_ERR("%s:not attach\n", __func__); return ret; } diff --git a/drivers/media/di_multi/Makefile b/drivers/media/di_multi/Makefile index 142689a57..6766b17b8 100644 --- a/drivers/media/di_multi/Makefile +++ b/drivers/media/di_multi/Makefile @@ -40,6 +40,7 @@ $(MEDIA_MODULE_NAME)-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += di_multi/di_hw_v2.o $(MEDIA_MODULE_NAME)-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += di_multi/di_hw_v3.o $(MEDIA_MODULE_NAME)-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += di_multi/di_afbc_v3.o $(MEDIA_MODULE_NAME)-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += di_multi/di_afbc_dbg.o +$(MEDIA_MODULE_NAME)-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += di_multi/tb_task.o ccflags-y += -I$(COMMON_DRIVERS_DIR)/drivers/media/common/rdma/ ccflags-y += -I$(src)/di_multi/ diff --git a/drivers/media/di_multi/dd_s4dw.c b/drivers/media/di_multi/dd_s4dw.c index 41ecee9e6..6071993d9 100644 --- a/drivers/media/di_multi/dd_s4dw.c +++ b/drivers/media/di_multi/dd_s4dw.c @@ -545,7 +545,7 @@ static void s4dw_reg_variable(struct di_ch_s *pch, struct vframe_s *vframe) ppre->bypass_flag = false; - de_devp->nrds_enable = 0; //?? + //de_devp->nrds_enable = 0; //?? //de_devp->pps_enable = dimp_get(edi_mp_pps_en); // ?? /*di pre h scaling down: sm1 tm2*/ de_devp->h_sc_down_en = 0; //?? @@ -661,7 +661,7 @@ static bool s4dw_bypass_2_ready_bynins(struct di_ch_s *pch, { void *in_ori; // struct dim_nins_s *nins =NULL; - struct di_buffer *buffer, *buffer_o; + struct di_buffer *buffer = NULL, *buffer_o; struct di_buf_s *buf_pst; if (!nins) { @@ -683,7 +683,7 @@ static bool s4dw_bypass_2_ready_bynins(struct di_ch_s *pch, if (dip_itf_is_ins_exbuf(pch)) { /* get out buffer */ buf_pst = di_que_out_to_di_buf(pch->ch_id, QUE_POST_FREE); - if (!buf_pst) { + if (!buf_pst || !buffer) { PR_ERR("%s:no post free\n", __func__); return true; } @@ -2081,7 +2081,7 @@ static void s4dw_pre_set(unsigned int channel) chan2_field_num, ppre->vdin2nr | (ppre->is_bypass_mem << 4), - ppre); + ppre, channel); //no need for s4dw dcntr_set(); diff --git a/drivers/media/di_multi/deinterlace.c b/drivers/media/di_multi/deinterlace.c index 27dd6e7a4..f1624b3f0 100644 --- a/drivers/media/di_multi/deinterlace.c +++ b/drivers/media/di_multi/deinterlace.c @@ -81,6 +81,7 @@ #include "di_pre.h" #include "di_prc.h" #include "di_task.h" +#include "tb_task.h" #include "di_vframe.h" #include "di_que.h" #include "di_api.h" @@ -114,6 +115,8 @@ static bool fg_bypass; #undef module_param_array #define module_param_array(x...) +//#define DBG_TIMER (1) + static DEFINE_SPINLOCK(di_lock2); #define di_lock_irqfiq_save(irq_flag) \ @@ -3060,7 +3063,6 @@ void dim_uninit_buf(unsigned int disable_mirror, unsigned int channel) #endif struct di_pre_stru_s *ppre = get_pre_stru(channel); struct di_post_stru_s *ppost = get_post_stru(channel); - struct di_dev_s *de_devp = get_dim_de_devp(); struct di_ch_s *pch; struct dim_mm_blk_s *blks[POST_BUF_NUM]; unsigned int blk_nub = 0; @@ -3101,10 +3103,9 @@ void dim_uninit_buf(unsigned int disable_mirror, unsigned int channel) ppost->de_post_process_done = 0; ppost->post_wr_cnt = 0; } - if (cfgeq(MEM_FLAG, EDI_MEM_M_REV) && de_devp->nrds_enable) { - dim_nr_ds_buf_uninit(cfgg(MEM_FLAG), - &de_devp->pdev->dev); - } +#ifdef DIM_TB_DETECT + dim_tb_ext_cmd(NULL, 0, channel, ECMD_TB_RELEASE); +#endif } #ifdef MARK_HIS @@ -3585,7 +3586,7 @@ void dim_pre_de_process(unsigned int channel) struct di_pre_stru_s *ppre = get_pre_stru(channel); int canvases_idex = ppre->field_count_for_cont % 2; unsigned short cur_inp_field_type = VIDTYPE_TYPEMASK; - unsigned short int_mask = 0x7f; + //unsigned short int_mask = 0x7f; struct di_dev_s *de_devp = get_dim_de_devp(); struct di_cvs_s *cvss; struct vframe_s *vf_i, *vf_mem, *vf_chan2; @@ -3887,15 +3888,15 @@ void dim_pre_de_process(unsigned int channel) dim_sc2_4k_set(sc2_pre_cfg->b.mode_4k); } } + /* if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) { if (de_devp->nrds_enable) { - dim_nr_ds_mif_config(); - dim_nr_ds_hw_ctrl(true); int_mask = 0x3f; } else { dim_nr_ds_hw_ctrl(false); } } + */ #ifndef TMP_MASK_FOR_T7 /*patch for SECAM signal format from vlsi-feijun for all IC*/ get_ops_nr()->secam_cfr_adjust(ppre->di_inp_buf->vframe->sig_fmt, @@ -3967,7 +3968,7 @@ void dim_pre_de_process(unsigned int channel) chan2_field_num, ppre->vdin2nr | (ppre->is_bypass_mem << 4), - ppre); + ppre, channel); //dimh_enable_afbc_input(ppre->di_inp_buf->vframe); @@ -4159,7 +4160,7 @@ void dim_pre_de_done_buf_config(unsigned int channel, bool flg_timeout) unsigned int pd_info = 0; struct di_pre_stru_s *ppre = get_pre_stru(channel); struct di_ch_s *pch; - //struct di_buf_s *n_buf; + //struct di_buf_s *buf_n; //bool crc_right; unsigned int afbce_used; @@ -4211,13 +4212,13 @@ void dim_pre_de_done_buf_config(unsigned int channel, bool flg_timeout) //ppre->di_wr_buf->flg_afbce_set = 0; //afbce_sw(EAFBC_ENC0, 0); #ifdef DBG_CRC - n_buf = next_buf(ppre->di_wr_buf); - if (n_buf) { - crc_right = dbg_checkcrc(n_buf); + buf_n = next_buf(ppre->di_wr_buf); + if (buf_n) { + crc_right = dbg_checkcrc(buf_n); if (!crc_right) PR_ERR("pre crc next err:b[%d]nb[%d]\n", ppre->di_wr_buf->index, - n_buf->index); + buf_n->index); } #endif } else { @@ -4268,40 +4269,52 @@ void dim_pre_de_done_buf_config(unsigned int channel, bool flg_timeout) } if (IS_ERR_OR_NULL(post_wr_buf)) return; - if (post_wr_buf && !ppre->cur_prog_flag && + if (post_wr_buf && !flg_timeout && ppre->di_inp_buf) { - dim_read_pulldown_info(&frame_motnum, - &field_motnum); - if (dimp_get(edi_mp_pulldown_enable)) { - /*pulldown_detection*/ - pd_info = get_ops_pd()->detection - (&post_wr_buf->pd_config, - ppre->mtn_status, - overturn, - ppre->di_inp_buf->vframe); - post_wr_buf->vframe->di_pulldown = pd_info; - } - post_wr_buf->vframe->di_pulldown |= 0x08; + if (!ppre->cur_prog_flag) { + dim_read_pulldown_info(&frame_motnum, + &field_motnum); + if (dimp_get(edi_mp_pulldown_enable)) { + /*pulldown_detection*/ + pd_info = get_ops_pd()->detection + (&post_wr_buf->pd_config, + ppre->mtn_status, + overturn, + ppre->di_inp_buf->vframe); + post_wr_buf->vframe->di_pulldown = pd_info; + } + post_wr_buf->vframe->di_pulldown |= 0x08; post_wr_buf->vframe->di_gmv = frame_motnum; post_wr_buf->vframe->di_cm_cnt = dim_rd_mcdi_fldcnt(); - /*if (combing_fix_en)*/ - /*if (dimp_get(eDI_MP_combing_fix_en)) {*/ - if (ppre->combing_fix_en) { - tmp_cur_lev = /*cur_lev*/ - get_ops_mtn()->adaptive_combing_fixing - (ppre->mtn_status, - field_motnum, - frame_motnum, - dimp_get(edi_mp_di_force_bit_mode)); - dimp_set(edi_mp_cur_lev, tmp_cur_lev); + /*if (combing_fix_en)*/ + /*from T3 /t5db adaptive_combing_new from vlsi yanling*/ + if (ppre->combing_fix_en) { + if ((DIM_IS_IC(T5DB) || DIM_IS_IC_EF(T3)) && + ppre->di_inp_buf->vframe->width == 1920 && + ppre->di_inp_buf->vframe->height == 1080) { + get_ops_mtn()->adaptive_combing_new + (field_motnum, + frame_motnum); + } else { + tmp_cur_lev = /*cur_lev*/ + get_ops_mtn()->adaptive_combing_fixing + (ppre->mtn_status, + field_motnum, + frame_motnum, + dimp_get(edi_mp_di_force_bit_mode)); + dimp_set(edi_mp_cur_lev, tmp_cur_lev); + } + } + if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX)) + get_ops_nr()->adaptive_cue_adjust(frame_motnum, + field_motnum); } - - if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX)) - get_ops_nr()->adaptive_cue_adjust(frame_motnum, - field_motnum); - if (!(di_dbg & DBG_M_RESET_PRE)) + /*from feijun for auto_nr t5db and eq/after t3 p mode*/ + if (!(di_dbg & DBG_M_RESET_PRE) && + (!ppre->cur_prog_flag || + DIM_IS_IC(T5DB) || DIM_IS_IC_EF(T3))) dim_pulldown_info_clear_g12a(&di_pre_regset); } if (ppre->prog_proc_type == 0x10) { @@ -4484,6 +4497,7 @@ void dim_pre_de_done_buf_config(unsigned int channel, bool flg_timeout) if (ppre->source_change_flag) { /* add dummy buf, will not be displayed */ + /*coverity[var_deref_model] post_wr_buf has been judged*/ add_dummy_vframe_type_pre(post_wr_buf, channel); } @@ -4726,6 +4740,7 @@ static struct di_buf_s *get_free_linked_buf(int idx, unsigned int channel) } } if (!IS_ERR_OR_NULL(di_buf)) + /*coverity[var_deref_op] di_buf has been judged*/ di_buf->di_wr_linked_buf = linkp; else return NULL; @@ -5008,7 +5023,7 @@ static struct di_buf_s *pp_pst_2_local(struct di_ch_s *pch) return di_buf; ch = pch->ch_id; - + /*coverity [var_deref_op] the return value is null there is no datas*/ di_buf = di_que_out_to_di_buf(ch, QUE_PRE_NO_BUF); //ary 2020-12-09 di_lock_irqfiq_save(irq_flag2); buf_pst = di_que_out_to_di_buf(ch, QUE_POST_FREE); @@ -5484,7 +5499,16 @@ unsigned char dim_pre_de_buf_config(unsigned int channel) /**************************************************/ /*mem check*/ memcpy(&ppre->vfm_cpy, vframe, sizeof(ppre->vfm_cpy)); - +#ifdef DIM_TB_DETECT + if (!is_progressive(vframe) && IS_IC_SUPPORT(TB)) { + if (pch->en_tb) + dim_nr_ds_hw_ctrl(true); + else + dim_nr_ds_hw_ctrl(false); + dim_tb_ext_cmd(vframe, ppre->field_count_for_cont, + channel, ECMD_TB_PROC); + } +#endif bypassr = is_bypass2(vframe, channel);//dim_is_bypass(vframe, channel); /*2020-12-02: here use di_buf->vframe is err*/ change_type = is_source_change(vframe, channel); @@ -5543,7 +5567,12 @@ unsigned char dim_pre_de_buf_config(unsigned int channel) } vframe = &nins->c.vfm_cp; - +#ifdef DIM_TB_DETECT + if (!is_progressive(vframe) && IS_IC_SUPPORT(TB)) { + dim_tb_ext_cmd(vframe, ppre->field_count_for_cont, + channel, ECMD_TB_ALGORITHM); + } +#endif if (vframe->type & VIDTYPE_COMPRESS) { /* backup the original vf->width/height for bypass case */ cur_dw_width = vframe->width; @@ -7014,7 +7043,6 @@ void dim_irq_pre(void) { unsigned int channel; struct di_pre_stru_s *ppre; - struct di_dev_s *de_devp = get_dim_de_devp(); struct di_hpre_s *pre = get_hw_pre(); u64 ctime; unsigned int data32 = RD(DI_INTR_CTRL); @@ -7058,7 +7086,7 @@ void dim_irq_pre(void) // (data32 & 0xfffffffb) | (intr_mode << 30)); ppre->timeout_check = false; di_unlock_irqfiq_restore(irq_flg); - PR_WARN("irq detect %d\n", (unsigned int)ctime); + PR_WARN("irq delete %d\n", (unsigned int)ctime); return; } ppre->timeout_check = false; @@ -7072,6 +7100,10 @@ void dim_irq_pre(void) } DIM_DI_WR(DI_INTR_CTRL, (data32 & 0xfffffffb) | (intr_mode << 30)); +#ifdef DIM_TB_DETECT + dim_nr_ds_hw_ctrl(false); + dbg_tb("%s:irq done\n", __func__); +#endif } /*if (ppre->pre_de_busy == 0) {*/ @@ -7111,8 +7143,8 @@ void dim_irq_pre(void) /*ppre->mcinfo_size*/0); } get_ops_nr()->nr_process_in_irq(); - if ((data32 & 0x200) && de_devp->nrds_enable) - dim_nr_ds_irq(); + //if ((data32 & 0x200) && de_devp->nrds_enable) + //dim_nr_ds_irq(); /* disable mif */ dimh_enable_di_pre_mif(false, dimp_get(edi_mp_mcpre_en)); dcntr_dis(); @@ -7176,7 +7208,7 @@ void dim_post_irq_sub(int irq) if ((data32 & 4) == 0) { if (dimp_get(edi_mp_di_dbg_mask) & 8) pr_info("irq[%d]post write undone.\n", irq); - return; + return; } if (pst->state == EDI_PST_ST_SET && pst->flg_have_set) flg_right = true; @@ -10405,7 +10437,9 @@ VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL); void di_unreg_setting(void) { /*unsigned int mirror_disable = get_blackout_policy();*/ +#ifdef MARK_DEADCODE_HIS /* */ unsigned int mirror_disable = 0; +#endif struct di_dev_s *de_devp = get_dim_de_devp(); if (!get_hw_reg_flg()) { @@ -10484,14 +10518,25 @@ void di_unreg_setting(void) diext_clk_b_sw(false); dbg_pl("%s disable di mirror image.\n", __func__); +#ifdef MARK_DEADCODE_HIS /* */ if ((dimp_get(edi_mp_post_wr_en) && dimp_get(edi_mp_post_wr_support)) || mirror_disable) { /*diwr_set_power_control(0);*/ hpst_mem_pd_sw(0); } +#endif + if (dimp_get(edi_mp_post_wr_en) && + dimp_get(edi_mp_post_wr_support)) { + /*diwr_set_power_control(0);*/ + hpst_mem_pd_sw(0); + } + +#ifdef MARK_DEADCODE_HIS /* */ + /*mirror_disable is write dead so comment the following codes*/ if (mirror_disable) hpst_vd1_sw(0); +#endif if (cfgg(HF)) di_hf_hw_release(0xff); @@ -10588,6 +10633,9 @@ void di_unreg_variable(unsigned int channel) } pch->sumx.flg_rebuild = false; di_hf_t_release(pch); +#ifdef DIM_TB_DETECT + dim_tb_ext_cmd(NULL, 0, channel, ECMD_TB_RELEASE); +#endif sum_g_clear(channel); sum_p_clear(channel); sum_pst_g_clear(channel); @@ -10665,19 +10713,27 @@ void di_load_pq_table(void) { struct di_pq_parm_s *pos = NULL, *tmp = NULL; struct di_dev_s *de_devp = get_dim_de_devp(); +#ifdef DBG_TIMER + u64 ustime, udiff; + + ustime = cur_to_usecs(); +#endif if (de_devp->flags & DI_LOAD_REG_FLAG) { - if (atomic_read(&de_devp->pq_flag) && - atomic_dec_and_test(&de_devp->pq_flag)) { - list_for_each_entry_safe(pos, tmp, - &de_devp->pq_table_list, list) { - dimh_load_regs(pos); - list_del(&pos->list); - di_pq_parm_destroy(pos); - } - de_devp->flags &= ~DI_LOAD_REG_FLAG; - atomic_set(&de_devp->pq_flag, 1); /* to idle*/ + mutex_lock(&de_devp->lock_pq); + list_for_each_entry_safe(pos, tmp, + &de_devp->pq_table_list, list) { + dimh_load_regs(pos); + list_del(&pos->list); + di_pq_parm_destroy(pos); } + de_devp->flags &= ~DI_LOAD_REG_FLAG; + mutex_unlock(&de_devp->lock_pq); +#ifdef DBG_TIMER + udiff = cur_to_usecs(); + udiff -= ustime; + PR_INF("%s:use %u us\n", "pq h:", (unsigned int)udiff); +#endif } } @@ -10693,11 +10749,18 @@ void di_pre_size_change(unsigned short width, struct di_pre_stru_s *ppre = get_pre_stru(channel); struct di_dev_s *de_devp = get_dim_de_devp(); union hw_sc2_ctr_pre_s *sc2_pre_cfg; + struct nr_cfg_s cfg_data; + struct nr_cfg_s *cfg = &cfg_data; + struct di_ch_s *pch; + pch = get_chdata(channel); /*pr_info("%s:\n", __func__);*/ /*debug only:*/ /*di_pause(channel, true);*/ - get_ops_nr()->nr_all_config(width, height, vf_type); + cfg->width = width; + cfg->height = height; + cfg->linkflag = 0; + get_ops_nr()->nr_all_config(vf_type, cfg); #ifdef DET3D /*det3d_config*/ get_ops_3d()->det3d_config(dimp_get(edi_mp_det3d_en) ? 1 : 0); @@ -10742,8 +10805,16 @@ void di_pre_size_change(unsigned short width, if (get_reg_flag_all()) di_load_pq_table(); - if (de_devp->nrds_enable) - dim_nr_ds_init(width, height); + if ((vf_type & VIDTYPE_TYPEMASK) && + ppre->cur_source_type == VFRAME_SOURCE_TYPE_OTHERS && + ((width * height) <= (1920 * 1088))) { +#ifdef DIM_TB_DETECT + if (cfgg(TB) && de_devp->tb_flag_int) + dim_nr_ds_hw_init(width, height, channel); +#endif + } else { + //de_devp->nrds_enable = 0; + } if (ppre->used_pps) dimp_set(edi_mp_pps_position, 1); if ((de_devp->pps_enable || ppre->used_pps) && @@ -10786,7 +10857,7 @@ void di_pre_size_change(unsigned short width, /*dimh_int_ctr(0, 0, 0, 0, 0, 0);*/ dimh_int_ctr(1, ppre->madi_enable, dimp_get(edi_mp_det3d_en) ? 1 : 0, - de_devp->nrds_enable, + pch->en_tb, dimp_get(edi_mp_post_wr_en), ppre->mcdi_enable); #endif @@ -11113,7 +11184,16 @@ void di_reg_variable(unsigned int channel, struct vframe_s *vframe) } else { dimp_set(edi_mp_use_2_interlace_buff, 0); } - de_devp->nrds_enable = dimp_get(edi_mp_nrds_en); + +#ifdef DIM_TB_DETECT + if (cfgg(TB)) { + dim_tb_ext_cmd(vframe, 0, + channel, ECMD_TB_REG); + } else { + //de_devp->nrds_enable = 0; + } +#endif + de_devp->pps_enable = dimp_get(edi_mp_pps_en); /*di pre h scaling down: sm1 tm2*/ de_devp->h_sc_down_en = di_mp_uit_get(edi_mp_pre_hsc_down_en); @@ -11303,34 +11383,32 @@ static void di_pq_parm_destroy(struct di_pq_parm_s *pq_ptr) } /*move from ioctrl*/ -long dim_pq_load_io(unsigned long arg) +static long dim_pq_load_io_l(struct di_dev_s *de_devp, unsigned long arg) { long ret = 0, tab_flag = 0; - di_dev_t *di_devp; + //di_dev_t *di_devp; void __user *argp = (void __user *)arg; size_t mm_size = 0; struct am_pq_parm_s tmp_pq_s = {0}; struct di_pq_parm_s *di_pq_ptr = NULL; - struct di_dev_s *de_devp = get_dim_de_devp(); + //struct di_dev_s *de_devp = get_dim_de_devp(); /*unsigned int channel = 0;*/ /*fix to channel 0*/ - di_devp = de_devp; - /* check io busy or not*/ - if (atomic_read(&de_devp->pq_io) < 1 || - !atomic_dec_and_test(&de_devp->pq_io)) { - PR_ERR("%s:busy, do nothing\n", __func__); - return -EBUSY; + //di_devp = de_devp; + if (!de_devp) { + PR_ERR("pq i:no dev\n"); + return -EFAULT; } mm_size = sizeof(struct am_pq_parm_s); if (copy_from_user(&tmp_pq_s, argp, mm_size)) { - PR_ERR("set pq parm errors\n"); - atomic_set(&de_devp->pq_io, 1); /* idle */ + PR_ERR("pq i:parm\n"); + //atomic_set(&de_devp->pq_io, 1); /* idle */ return -EFAULT; } if (tmp_pq_s.table_len >= DIMTABLE_LEN_MAX) { - PR_ERR("load 0x%x wrong pq table_len.\n", + PR_ERR("pq i:0x%x table_len.\n", tmp_pq_s.table_len); - atomic_set(&de_devp->pq_io, 1); /* idle */ + //atomic_set(&de_devp->pq_io, 1); /* idle */ return -EFAULT; } tab_flag = TABLE_NAME_DI | TABLE_NAME_NR | TABLE_NAME_MCDI | @@ -11338,62 +11416,81 @@ long dim_pq_load_io(unsigned long arg) tab_flag |= TABLE_NAME_SMOOTHPLUS; if (tmp_pq_s.table_name & tab_flag) { - PR_INF("load 0x%x pq len %u %s.\n", + PR_INF("pq i:0x%x:%u:%s.\n", tmp_pq_s.table_name, tmp_pq_s.table_len, (!dim_dbg_is_force_later() && get_reg_flag_all()) ? "directly" : "later"); } else { - PR_ERR("load 0x%x wrong pq table.\n", + PR_ERR("pq i:0x%x name.\n", tmp_pq_s.table_name); - atomic_set(&de_devp->pq_io, 1); /* idle */ + //atomic_set(&de_devp->pq_io, 1); /* idle */ return -EFAULT; } di_pq_ptr = di_pq_parm_create(&tmp_pq_s); if (!di_pq_ptr) { - PR_ERR("allocat pq parm struct error.\n"); - atomic_set(&de_devp->pq_io, 1); /* idle */ + PR_ERR("pq i:allocate\n"); + //atomic_set(&de_devp->pq_io, 1); /* idle */ return -EFAULT; } argp = (void __user *)tmp_pq_s.table_ptr; mm_size = tmp_pq_s.table_len * sizeof(struct am_reg_s); if (copy_from_user(di_pq_ptr->regs, argp, mm_size)) { - PR_ERR("user copy pq table errors\n"); - atomic_set(&de_devp->pq_io, 1); /* idle */ + PR_ERR("pq i:copy\n"); + //atomic_set(&de_devp->pq_io, 1); /* idle */ return -EFAULT; } +#ifdef HIS_CODE if (!dim_dbg_is_force_later() && get_reg_flag_all()) { dimh_load_regs(di_pq_ptr); di_pq_parm_destroy(di_pq_ptr); atomic_set(&de_devp->pq_io, 1); /* idle */ return ret; } - if (atomic_read(&de_devp->pq_flag) && - atomic_dec_and_test(&de_devp->pq_flag)) { - if (di_devp->flags & DI_LOAD_REG_FLAG) { - struct di_pq_parm_s *pos = NULL, *tmp = NULL; +#endif + if (de_devp->flags & DI_LOAD_REG_FLAG) { + struct di_pq_parm_s *pos = NULL, *tmp = NULL; - list_for_each_entry_safe(pos, tmp, - &di_devp->pq_table_list, - list) { - if (di_pq_ptr->pq_parm.table_name == - pos->pq_parm.table_name) { - PR_INF("remove 0x%x table.\n", - pos->pq_parm.table_name); - list_del(&pos->list); - di_pq_parm_destroy(pos); - } + list_for_each_entry_safe(pos, tmp, + &de_devp->pq_table_list, + list) { + if (di_pq_ptr->pq_parm.table_name == + pos->pq_parm.table_name) { + PR_INF("pq i:rm 0x%x\n", + pos->pq_parm.table_name); + list_del(&pos->list); + di_pq_parm_destroy(pos); } } - list_add_tail(&di_pq_ptr->list, - &di_devp->pq_table_list); - di_devp->flags |= DI_LOAD_REG_FLAG; - atomic_set(&de_devp->pq_flag, 1);/* to idle */ - } else { - PR_ERR("please retry table name 0x%x.\n", - di_pq_ptr->pq_parm.table_name); - di_pq_parm_destroy(di_pq_ptr); - ret = -EBUSY; } - atomic_set(&de_devp->pq_io, 1); /* idle */ + list_add_tail(&di_pq_ptr->list, + &de_devp->pq_table_list); + de_devp->flags |= DI_LOAD_REG_FLAG; + + return ret; +} + +long dim_pq_load_io(unsigned long arg) +{ + struct di_dev_s *de_devp = get_dim_de_devp(); + long ret; +#ifdef DBG_TIMER + u64 ustime, udiff; + + ustime = cur_to_usecs(); +#endif + + if (!de_devp) { + PR_ERR("%s:no dev\n", __func__); + return -EFAULT; + } + mutex_lock(&de_devp->lock_pq); + ret = dim_pq_load_io_l(de_devp, arg); + mutex_unlock(&de_devp->lock_pq); +#ifdef DBG_TIMER + udiff = cur_to_usecs(); + udiff -= ustime; + PR_INF("%s:use %u us\n", "pq i", (unsigned int)udiff); +#endif + return ret; } diff --git a/drivers/media/di_multi/deinterlace.h b/drivers/media/di_multi/deinterlace.h index 5b1d310f8..24bf8a9ba 100644 --- a/drivers/media/di_multi/deinterlace.h +++ b/drivers/media/di_multi/deinterlace.h @@ -38,7 +38,7 @@ ***********************************************/ #define DIM_OUT_NV21 (1) //#define TEST_PIP (1) - +//#define DBG_POST_SETTING (1) /************************************************ * vframe use ud meta data ************************************************/ @@ -49,10 +49,18 @@ ************************************************/ #define DIM_HAVE_HDR (1) +/************************************************ + * function:decontour use detect border + * char aml_ldim_get_bbd_state(void) in + * include/linux/amlogic/media/vout/lcd/aml_ldim.h + ************************************************/ +//#define DIM_DCT_BORDER_DETECT (1) +#define DIM_DCT_BORDER_DBG (1) +//#define DIM_DCT_BORDER_SIMULATION (1) /************************************************ * pre-vpp link ************************************************/ -#define VPP_LINK_USED_FUNC (1) +//#define VPP_LINK_USED_FUNC (1) /************************************************ * game mode @@ -65,6 +73,7 @@ ************************************************/ //#define DIM_EXT_NO_HF (1) +//#define DIM_TB_DETECT /*trigger_pre_di_process param*/ #define TRIGGER_PRE_BY_PUT 'p' #define TRIGGER_PRE_BY_DE_IRQ 'i' @@ -466,8 +475,11 @@ struct di_dev_s { unsigned long clkb_max_rate; unsigned long clkb_min_rate; struct list_head pq_table_list; +#ifdef HIS_CODE atomic_t pq_flag; /* 1: idle; 0: busy */ atomic_t pq_io; /* 1: idle; 0: busy */ +#endif + struct mutex lock_pq; /* for pq load */ unsigned char di_event; unsigned int pre_irq; unsigned int post_irq; @@ -481,7 +493,7 @@ struct di_dev_s { unsigned int nr10bit_support; /* is DI support post wr to mem for OMX */ unsigned int post_wr_support; - unsigned int nrds_enable; + //unsigned int nrds_enable; unsigned int pps_enable; unsigned int h_sc_down_en;/*sm1, tm2 ...*/ /*struct mutex cma_mutex;*/ @@ -501,6 +513,13 @@ struct di_dev_s { struct vpu_dev_s *dim_vpu_pd_vd1; struct vpu_dev_s *dim_vpu_pd_post; bool is_crc_ic; +#ifdef DIM_TB_DETECT + //unsigned int tb_detect; + unsigned int tb_detect_period; + unsigned int tb_detect_buf_len; + unsigned int tb_detect_init_mute; + unsigned int tb_flag_int; +#endif }; struct di_pre_stru_s { @@ -949,6 +968,7 @@ void dpre_vdoing(unsigned int ch); //#define DBG_CLEAR_MEM (1) #define DBG_BUFFER_EXT (1) #define DBG_VFM_CVS (1) +//#define TMP_EN_PLINK (1) //#define DBG_EXTBUFFER_ONLY_ADDR (1) //#define S4D_OLD_SETTING_KEEP (1) //#define S4D_OLD_PQ_KEEP (1) diff --git a/drivers/media/di_multi/deinterlace_dbg.c b/drivers/media/di_multi/deinterlace_dbg.c index dee91ba50..391446f73 100644 --- a/drivers/media/di_multi/deinterlace_dbg.c +++ b/drivers/media/di_multi/deinterlace_dbg.c @@ -1031,15 +1031,16 @@ int dim_state_show(struct seq_file *seq, void *v, unsigned int channel) struct div2_mm_s *mm = dim_mm_get(channel); /*mm-0705*/ struct di_ch_s *pch = get_chdata(channel); struct di_mng_s *pbm = get_bufmng(); - struct di_dev_s *de_devp = get_dim_de_devp(); +// struct di_dev_s *de_devp = get_dim_de_devp(); di_pre_stru_p = get_pre_stru(channel); di_post_stru_p = get_post_stru(channel); +#ifdef HIS_CODE if (de_devp) seq_printf(seq, "pq:io[%d],idle[%d]\n", atomic_read(&de_devp->pq_io), atomic_read(&de_devp->pq_flag)); - +#endif dump_state_flag = 1; seq_printf(seq, "%s:ch[%d]\n", __func__, channel); seq_printf(seq, "init_flag %d, dw[%d:%d:%d:%d]\n", diff --git a/drivers/media/di_multi/deinterlace_hw.c b/drivers/media/di_multi/deinterlace_hw.c index 02417df20..1bf1fd149 100644 --- a/drivers/media/di_multi/deinterlace_hw.c +++ b/drivers/media/di_multi/deinterlace_hw.c @@ -968,16 +968,18 @@ void dimh_enable_di_pre_aml(struct DI_MIF_S *di_inp_mif, unsigned char madi_en, unsigned char pre_field_num, unsigned char pre_vdin_link, - void *pre) + void *pre, unsigned int channel) { bool mem_bypass = false, chan2_disable = false; unsigned short nrwr_hsize = 0, nrwr_vsize = 0; unsigned short chan2_hsize = 0, chan2_vsize = 0; unsigned short mem_hsize = 0, mem_vsize = 0; unsigned int sc2_tfbf = 0; /* DI_PRE_CTRL bit [12:11] */ + unsigned int pd32_infor = 0; /* DI_PRE_CTRL bit [2:3] */ struct di_pre_stru_s *ppre = (struct di_pre_stru_s *)pre; static bool last_bypass; //dbg only static bool last_disable_chan2; //dbg only + struct di_ch_s *pch; if (DIM_IS_IC(T5) || DIM_IS_IC(T5DB)) { mem_bypass = (pre_vdin_link & 0xf0) ? true : false; @@ -986,6 +988,8 @@ void dimh_enable_di_pre_aml(struct DI_MIF_S *di_inp_mif, pre_vdin_link &= 0xf; + pch = get_chdata(channel); + if (DIM_IS_IC_EF(SC2)) { di_inp_mif->urgent = dimp_get(edi_mp_pre_urgent); di_inp_mif->hold_line = dimp_get(edi_mp_pre_hold_line); @@ -1068,19 +1072,28 @@ void dimh_enable_di_pre_aml(struct DI_MIF_S *di_inp_mif, DIM_RDMA_WR_BITS(DI_MTN_1_CTRL1, madi_en ? 5 : 0, 29, 3); } - if (DIM_IS_IC_EF(SC2)) - sc2_tfbf = 2; - else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) + if (DIM_IS_IC_EF(SC2)) { + if (pch->en_tb) + sc2_tfbf = 3; + else + sc2_tfbf = 2; + } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) { sc2_tfbf = 1; - else + } else { sc2_tfbf = 0; + } /* * the bit define is not same with before , * from sc2 DI_PRE_CTRL 0x1700, * bit5/6/8/9/10/11/12 * bit21/22 chan2 t/b reverse,check with vlsi feijun + * bit2/3 enable pd32 check for i/p from vlsi feijun */ + if (DIM_IS_IC_EF(T3) || DIM_IS_IC(T5DB)) + pd32_infor = 0x1; + else + pd32_infor = madi_en; if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) { if (madi_en) { @@ -1110,9 +1123,9 @@ void dimh_enable_di_pre_aml(struct DI_MIF_S *di_inp_mif, DIM_RDMA_WR(DI_PRE_CTRL, 1 | /* nr wr en */ (madi_en << 1) | /* mtn en */ - (madi_en << 2) | + (pd32_infor << 2) | /*check3:2pulldown*/ - (madi_en << 3) | + (pd32_infor << 3) | /*check2:2pulldown*/ (1 << 4) | (madi_en << 5) | @@ -1135,8 +1148,8 @@ void dimh_enable_di_pre_aml(struct DI_MIF_S *di_inp_mif, DIM_RDMA_WR(DI_PRE_CTRL, 1 | /* nr wr en */ (madi_en << 1) | /* mtn en */ - (madi_en << 2) | /* check3:2pulldown*/ - (madi_en << 3) | /* check2:2pulldown*/ + (pd32_infor << 2) | /* check3:2pulldown*/ + (pd32_infor << 3) | /* check2:2pulldown*/ (1 << 4) | (madi_en << 5) | /*hist check enable*/ /* hist check use chan2. */ @@ -1253,7 +1266,7 @@ void dimh_enable_mc_di_pre(struct DI_MC_MIF_s *di_mcinford_mif, if (is_meson_gxlx_cpu() || is_meson_txhd_cpu()) me_auto_en = false; #endif - + /*coverity[dead_error_line] False judgment, not dead code*/ ctrl_mode = (me_auto_en ? 0x1bfff7ff : 0x1bfe37ff); DIM_RDMA_WR(MCDI_CTRL_MODE, (mcdi_en ? ctrl_mode : 0)); DIM_RDMA_WR_BITS(MCDI_MOTINEN, (mcdi_en ? 3 : 0), 0, 2); @@ -4126,12 +4139,17 @@ void dim_rst_protect(bool on)/*2019-01-22 by VLSI feng.wang*/ #define PRE_ID_MASK_TL1 (0x14500) #define PRE_ID_MASK_T5 (0x28a00) //add decontour and shift 1bit +#define PRE_ID_MASK_S5 (0x50a00) //add ai color static bool di_pre_idle(void) { bool ret = false; - if (DIM_IS_IC_EF(T3) || DIM_IS_IC(T5D) || DIM_IS_IC(T5DB) || + if (DIM_IS_IC_EF(S5)) { + if ((DIM_RDMA_RD(DI_ARB_DBG_STAT_L1C1) & + PRE_ID_MASK_S5) == PRE_ID_MASK_S5) + ret = true; + } else if (DIM_IS_IC_EF(T3) || DIM_IS_IC(T5D) || DIM_IS_IC(T5DB) || DIM_IS_IC(T5)) { if ((DIM_RDMA_RD(DI_ARB_DBG_STAT_L1C1) & PRE_ID_MASK_T5) == PRE_ID_MASK_T5) @@ -4575,7 +4593,9 @@ static void di_pre_data_mif_ctrl(bool enable) if (dim_afds()) dim_afds()->inp_sw(false); } - + //test for bus-crash + //disable afbcd: + disable_afbcd_t5dvb(); } } @@ -4785,19 +4805,19 @@ void dimh_load_regs(struct di_pq_parm_s *di_pq_ptr) if (dimp_get(edi_mp_pq_load_dbg) == 1) return; if (dimp_get(edi_mp_pq_load_dbg) == 2) - pr_info("[DI]%s hw load 0x%x pq table len %u.\n", - __func__, di_pq_ptr->pq_parm.table_name, + PR_INF("pq h: 0x%x len %u.\n", + di_pq_ptr->pq_parm.table_name, di_pq_ptr->pq_parm.table_len); if (PTR_ERR_OR_ZERO(di_pq_ptr->regs)) { PR_ERR("[DI] table ptr error.\n"); return; } - PR_INF("load 0x%x pq table len %u.\n", + PR_INF("pq h: 0x%x %u.\n", di_pq_ptr->pq_parm.table_name, di_pq_ptr->pq_parm.table_len); /* check len for coverity */ if (di_pq_ptr->pq_parm.table_len >= DIMTABLE_LEN_MAX) { - PR_WARN("%s:len overflow:%d\n", __func__, + PR_WARN("%s:overflow:%d\n", "pq h", di_pq_ptr->pq_parm.table_len); return; } @@ -4811,7 +4831,7 @@ void dimh_load_regs(struct di_pq_parm_s *di_pq_ptr) value = regs_p->val; mask = regs_p->mask; if (dimp_get(edi_mp_pq_load_dbg) == 2) - pr_info("[%u][0x%x] = [0x%x]&[0x%x]\n", + PR_INF("[%u][0x%x] = [0x%x]&[0x%x]\n", i, addr, value, mask); for (j = 0; j < SKIP_CTRE_NUM; j++) { @@ -4826,7 +4846,7 @@ void dimh_load_regs(struct di_pq_parm_s *di_pq_ptr) regs_p++; if (j < SKIP_CTRE_NUM) { if (dimp_get(edi_mp_pq_load_dbg) == 3) - pr_info("%s skip [0x%x]=[0x%x].\n", + PR_INF("%s skip [0x%x]=[0x%x].\n", __func__, addr, value); continue; } @@ -4839,7 +4859,7 @@ void dimh_load_regs(struct di_pq_parm_s *di_pq_ptr) if (!ctrl_reg_flag && !save_db) DIM_DI_WR(addr, value); if (dimp_get(edi_mp_pq_load_dbg) == 2) - pr_info("[%u][0x%x] = [0x%x] %s\n", i, addr, + PR_INF("[%u][0x%x] = [0x%x] %s\n", i, addr, value, RD(addr) != value ? "fail" : "success"); } } diff --git a/drivers/media/di_multi/deinterlace_hw.h b/drivers/media/di_multi/deinterlace_hw.h index a917bbc17..fbfc620f6 100644 --- a/drivers/media/di_multi/deinterlace_hw.h +++ b/drivers/media/di_multi/deinterlace_hw.h @@ -560,7 +560,7 @@ void dimh_enable_di_pre_aml(struct DI_MIF_S *di_inp_mif, unsigned char madi_en, unsigned char pre_field_num, unsigned char pre_vdin_link, - void *ppre); + void *ppre, unsigned int channel); //void dimh_enable_afbc_input(struct vframe_s *vf); void dimh_mc_pre_mv_irq(void); @@ -1020,6 +1020,8 @@ void di_mcmif_linear_rd_cfg(struct DI_MC_MIF_s *mif, unsigned int CTRL1, unsigned int CTRL2, unsigned int BADDR); +void di_mif1_linear_wr_cfgds(unsigned long addr, unsigned int STRIDE, + unsigned int BADDR); bool dip_is_linear(void); bool dim_dbg_cfg_post_byapss(void); void dbg_reg_mem(unsigned int dbgid); @@ -1029,4 +1031,6 @@ extern const struct reg_acc di_pst_regset; void set_sc2overlap_table(unsigned int addr, unsigned int value, unsigned int start, unsigned int len); +void disable_afbcd_t5dvb(void); + #endif diff --git a/drivers/media/di_multi/di_afbc_v3.c b/drivers/media/di_multi/di_afbc_v3.c index 490cdef41..8ba91b2e7 100644 --- a/drivers/media/di_multi/di_afbc_v3.c +++ b/drivers/media/di_multi/di_afbc_v3.c @@ -4552,6 +4552,8 @@ static u32 enable_afbc_input_dvfm(void *ds_in, void *nvfm_in, pcfg, win_mem, op_in); +#ifdef MARK_DEADCODE_HIS + /*chan2_vf is write dead so comment the following codes*/ if (chan2_vf && pafd_ctr->en_set.b.chan2) /* chan2 */ enable_afbc_input_local_dvfm(chan2_vf, @@ -4559,7 +4561,7 @@ static u32 enable_afbc_input_dvfm(void *ds_in, void *nvfm_in, pcfg, NULL, op_in); - +#endif /*nr*/ if (pafd_ctr->en_set.b.enc_nr) afbce_set_dvfm(nr_vf, EAFBC_ENC0, op_in); @@ -4587,6 +4589,8 @@ static u32 enable_afbc_input_dvfm(void *ds_in, void *nvfm_in, op_in); } +#ifdef MARK_DEADCODE_HIS + /* the following codes are commented result in chan2_vf is false*/ if (pafd_ctr->en_set.b.chan2 && chan2_vf) { if (is_cfg(EAFBC_CFG_FORCE_CHAN2)) enable_afbc_input_local_dvfm @@ -4600,7 +4604,7 @@ static u32 enable_afbc_input_dvfm(void *ds_in, void *nvfm_in, pafd_ctr->fb.ch2_dec, op_in); } - +#endif /*nr*/ if (pafd_ctr->en_set.b.enc_nr) { if (is_cfg(EAFBC_CFG_FORCE_NR)) @@ -4619,9 +4623,11 @@ static u32 enable_afbc_input_dvfm(void *ds_in, void *nvfm_in, if (pafd_ctr->en_set.b.mem) afbc_update_level1_dvfm(mem_vf2, pafd_ctr->fb.mem_dec, op_in); +#ifdef MARK_DEADCODE_HIS + /*chan2_vf is NULL the follow condition cannot be true*/ if (pafd_ctr->en_set.b.chan2 && chan2_vf) afbc_update_level1_dvfm(chan2_vf, pafd_ctr->fb.ch2_dec, op_in); - +#endif /*nr*/ if (pafd_ctr->en_set.b.enc_nr) afbce_update_level1_dvfm(nr_vf, diff --git a/drivers/media/di_multi/di_data_l.h b/drivers/media/di_multi/di_data_l.h index a1c25bb02..4373dc9ed 100644 --- a/drivers/media/di_multi/di_data_l.h +++ b/drivers/media/di_multi/di_data_l.h @@ -169,6 +169,7 @@ enum EDI_CFG_TOP_IDX { EDI_CFG_SUB_V, EDI_CFG_EN_PRE_LINK, EDI_CFG_AFBCE_LOSS_EN, + EDI_CFG_TB, EDI_CFG_END, }; @@ -773,6 +774,22 @@ struct di_mtask { unsigned int err_cmd_cnt; }; +struct di_tb_task { + bool flg_init; + struct semaphore sem; + wait_queue_head_t wait_queue; + struct task_struct *thread; + unsigned int status; + + unsigned int wakeup; + unsigned int delay; + bool exit; + + struct dim_fcmd_s fcmd[DI_CHANNEL_NUB]; + unsigned int err_res; /* 0: no err; other have error */ + unsigned int err_cmd_cnt; +}; + #define MAX_KFIFO_L_CMD_NUB 32 union DI_L_CMD_BITS { @@ -822,6 +839,14 @@ enum ECMD_BLK { ECMD_BLK_RELEASE_ALL, /* ready to release */ }; +enum ECMD_TB { + ECMD_TB_NONE, + ECMD_TB_REG, + ECMD_TB_PROC, + ECMD_TB_ALGORITHM, + ECMD_TB_RELEASE, +}; + enum EDIM_BLK_TYP { EDIM_BLK_TYP_PST_TEST, EDIM_BLK_TYP_OLDI, @@ -859,6 +884,17 @@ struct mtsk_cmd_s { struct blk_flg_s flg; }; +struct tb_task_cmd_s { + unsigned int cmd : 4; + unsigned int block_mode : 1; + unsigned int hf_need : 1; // + unsigned int ch : 2; + unsigned int nub : 8; + unsigned int rev2 : 16; + struct vframe_s *in_buf_vf; + int field_count; +}; + /************************************** * QUE * keep same order as di_name_new_que @@ -1030,6 +1066,8 @@ enum EDI_MP_UI_T { edi_mp_hdr_ctrl, edi_mp_clock_low_ratio,//set low ratio of vpu clkb edi_mp_shr_cfg, + edi_mp_blend_mode, + edi_mp_tb_dump, EDI_MP_SUB_DI_E, /**************************************/ EDI_MP_SUB_NR_B, @@ -1356,6 +1394,9 @@ struct di_mm_cfg_s { unsigned int size_buf_hf; //from t3 unsigned int hf_hsize; unsigned int hf_vsize; + unsigned int size_buf_tb; //from t3 + unsigned int tb_hsize; + unsigned int tb_vsize; }; struct dim_mm_t_s { /* use for reserved and alloc all*/ @@ -2018,6 +2059,10 @@ struct di_ch_s { struct kfifo fifo32[DIM_Q_NUB]; bool flg_fifo32[DIM_Q_NUB]; unsigned int err; + bool en_tb_buf; + bool en_tb; // + unsigned char tb_owner; // + bool tb_busy;// }; struct dim_policy_s { @@ -2067,6 +2112,7 @@ struct di_mng_s { /*task:*/ struct di_task tsk; struct di_mtask mtsk; + struct di_tb_task tb_task; enum EDIM_TMODE tmode_pre[DI_CHANNEL_MAX]; /*channel state: use enum eDI_TOP_STATE */ @@ -2618,7 +2664,7 @@ struct dim_dvs_prevpp_s { atomic_t sum_wk_rq; /*debug: total cal wk */ atomic_t sum_wk_real_cnt; /*debug: real wk */ const struct vframe_operations_s *vf_ops; - struct dim_plink_dbg_s dbg; + struct dim_plink_dbg_s dbg_d; }; struct di_data_l_s { @@ -2666,6 +2712,9 @@ struct di_data_l_s { unsigned int ic_sub_ver; struct reg_t s4dw_reg[DIM_NRDIS_REG_BACK_NUB]; void *mng_hf_buf; + unsigned char tb_src_cnt;// + //unsigned char tb_owner; // + //bool tb_busy;// struct dim_dvs_prevpp_s dvs_prevpp; atomic_t state_cnt_reg; atomic_t cnt_reg_pre_link;/* pre-vpp link cnt */ @@ -2714,6 +2763,7 @@ struct di_data_l_s { #define DBG_M_HDR DI_BIT27 #define DBG_M_IC DI_BIT28 #define DBG_M_RESET_PRE DI_BIT29 +#define DBG_M_TB DI_BIT27 extern unsigned int di_dbg; @@ -2757,6 +2807,7 @@ extern unsigned int di_dbg; #define dbg_hdr(fmt, args ...) dbg_m(DBG_M_HDR, fmt, ##args) #define dbg_link(fmt, args ...) dbg_m(DBG_M_LINK, fmt, ##args) #define dbg_tst(fmt, args ...) dbg_m(DBG_M_TST, fmt, ##args) +#define dbg_tb(fmt, args ...) dbg_m(DBG_M_TB, fmt, ##args) #define dbg_bypass(fmt, args ...) dbg_m(DBG_M_BPASS, fmt, ##args) #define dbg_ic(fmt, args ...) dbg_m(DBG_M_IC, fmt, ##args) @@ -3180,6 +3231,11 @@ static inline struct di_mtask *get_mtask(void) return &get_bufmng()->mtsk; } +static inline struct di_tb_task *get_tb_task(void) +{ + return &get_bufmng()->tb_task; +} + /****************************************** * pq ops *****************************************/ @@ -3282,7 +3338,7 @@ static inline unsigned int di_get_mem_size(unsigned int ch) static inline struct dim_plink_dbg_s *di_g_plink_dbg(void) { - return &get_datal()->dvs_prevpp.dbg; + return &get_datal()->dvs_prevpp.dbg_d; } void di_tout_int(struct di_time_out_s *tout, unsigned int thd); @@ -3355,11 +3411,14 @@ static inline void p_ref_set_buf(struct di_buf_s *buf, #define IC_SUPPORT_HDR DI_BIT1 #define IC_SUPPORT_DW DI_BIT2 /* double write */ #define IC_SUPPORT_PRE_VPP_LINK DI_BIT3 +#define IC_SUPPORT_TB DI_BIT4 #define IS_IC_SUPPORT(cc) (get_datal()->mdata->support & \ IC_SUPPORT_##cc ? true : false) #define DIM_IS_ICS(T5W) (DIM_IS_IC(T3) && \ cfgg(SUB_V) == 1) + #define DIM_IS_ICS_T5M (DIM_IS_IC(T3) && \ cfgg(SUB_V) == 2) + #endif /*__DI_DATA_L_H__*/ diff --git a/drivers/media/di_multi/di_dbg.c b/drivers/media/di_multi/di_dbg.c index 8dee9632d..c845691f3 100644 --- a/drivers/media/di_multi/di_dbg.c +++ b/drivers/media/di_multi/di_dbg.c @@ -1414,6 +1414,7 @@ ssize_t seq_file_vtype_store(struct file *file, const char __user *userbuf, } #else + /*coverity[tainted_data] Misjudged buf not tainted*/ ret = kstrtouint(buf, 0, &vtype); if (ret) { pr_info("war:please enter vtype\n"); @@ -1751,7 +1752,7 @@ static ssize_t dbg_crc_store(struct file *file, const char __user *userbuf, chp = (int *)file->private_data; //pr_info("%s:ch[%d]\n", __func__, *chp); ch = *chp; - + /*coverity[tainted_data] Misjudged buf not tainted*/ ret = kstrtouint(buf, 0, &val); if (ret) { //pr_info("war:please enter val\n"); @@ -2119,6 +2120,7 @@ static ssize_t cfgtw_id_store(struct file *file, const char __user *userbuf, case 2: if (!di_cfg_top_check(index)) break; + /*coverity[tainted_data] Misjudged buf not tainted*/ pr_info("%s:%d->%d\n", di_cfg_top_get_name(index), di_cfg_top_get(index), @@ -2143,6 +2145,7 @@ static ssize_t cfgt_one_store(struct file *file, const char __user *userbuf, if (copy_from_user(buf, userbuf, count)) return -EFAULT; buf[count] = 0; + /*coverity[tainted_data] Misjudged buf not tainted*/ ret = kstrtouint(buf, 0, &val); if (ret) { pr_info("war:please enter val\n"); @@ -3199,6 +3202,7 @@ void didbg_fs_init(void) if (IS_ERR_OR_NULL(*root_ent)) return; for (i = 0; i < ARRAY_SIZE(di_debugfs_files_top); i++) { + /*coverity[var_deref_model] *root_ent has been judged*/ ent = debugfs_create_file(di_debugfs_files_top[i].name, di_debugfs_files_top[i].mode, *root_ent, NULL, diff --git a/drivers/media/di_multi/di_decont.c b/drivers/media/di_multi/di_decont.c index 26531e366..c99608954 100644 --- a/drivers/media/di_multi/di_decont.c +++ b/drivers/media/di_multi/di_decont.c @@ -35,6 +35,9 @@ #include "register.h" #include "di_prc.h" +#ifdef DIM_DCT_BORDER_DETECT +#include +#endif /************************************************ * dbg_dct * bit 0: disable dct pre //used for enable decontour @@ -45,6 +48,9 @@ * bit 6:8: pq ? * dcntr dynamic used dbg_dct BIT:6-8 * bit 12:13: demo mode (old is bit 8:9) + * bit 14: border detect simulation only use when + * DIM_DCT_BORDER_SIMULATION enable + * bit 15: border detect disable ************************************************/ /*bit 4: grid use fix */ /*bit 9:8: demo left /right */ @@ -96,6 +102,20 @@ bool dcntr_dynamic_disable(void) return false; } +bool dcntr_border_simulation_have(void) +{ + if (dbg_dct & DI_BIT14) + return true; + return false; +} + +bool dcntr_border_detect_disable(void) +{ + if (dbg_dct & DI_BIT15) + return true; + return false; +} + enum ECNTR_MIF_IDX { ECNTR_MIF_IDX_DIVR, ECNTR_MIF_IDX_GRID, @@ -1151,6 +1171,41 @@ void dcntr_dynamic_setting(struct dim_rpt_s *rpt) op->bwr(DCTR_BLENDING2 + off, pdate[0], 16, 9); } +#ifdef DIM_DCT_BORDER_DETECT +static void dct_border_tune(const struct reg_acc *op, unsigned int off) +{ + bool have_border = false; + bool simulation = false; +#ifdef DIM_DCT_BORDER_DBG + static bool last; +#endif + if (dcntr_border_detect_disable()) + return; +#ifdef DIM_DCT_BORDER_SIMULATION + simulation = true; + if (dcntr_border_simulation_have()) + have_border = true; +#else + if (aml_ldim_get_bbd_state() == 1) + have_border = true; +#endif + if (have_border) + op->bwr(DCTR_PMEM_MAP1 + off, 1, 30, 1); + else + op->bwr(DCTR_PMEM_MAP1 + off, 0, 30, 1); +#ifdef DIM_DCT_BORDER_DBG + if (last != have_border) { + PR_INF("%s:%d->%d\n", __func__, last, have_border); + last = have_border; + PR_INF("\t:reg:0x%x=0x%x:%d\n", + DCTR_PMEM_MAP1 + off, op->rd(DCTR_PMEM_MAP1 + off), + simulation); + } +#endif +} + +#endif /* DIM_DCT_BORDER_DETECT */ + void dcntr_pq_tune(struct dim_rpt_s *rpt) { const struct reg_acc *op = &di_pre_regset; @@ -1173,6 +1228,9 @@ void dcntr_pq_tune(struct dim_rpt_s *rpt) dim_print("%s:0x%x\n", __func__, rpt->dct_map_0); dcntr_dynamic_setting(rpt); +#ifdef DIM_DCT_BORDER_DETECT + dct_border_tune(op, off); +#endif } void dcntr_dis(void) diff --git a/drivers/media/di_multi/di_hw_v3.c b/drivers/media/di_multi/di_hw_v3.c index 7d174f245..c8fd9e561 100644 --- a/drivers/media/di_multi/di_hw_v3.c +++ b/drivers/media/di_multi/di_hw_v3.c @@ -562,6 +562,23 @@ static void di_mif1_linear_wr_cfg(struct DI_SIM_MIF_S *mif, dbg_ic("\treg[0x%x] = 0x%x\n", BADDR, op->rd(BADDR)); } +void di_mif1_linear_wr_cfgds(unsigned long addr, unsigned int STRIDE, + unsigned int BADDR) +{ + unsigned int stride; + const struct reg_acc *op = &di_pre_regset; + + //pr_info("%s:\n", __func__); + //di_mif1_stride(mif, &stride); + di_mif1_stride2(8, 128, &stride); + op->wr(STRIDE, (0 << 31) | stride);//stride + op->wr(BADDR, addr >> 4);//base_addr + //pr_info("\tstride[%d]\n", stride); + //pr_info("\taddr[0x%lx]\n", addr); + //pr_info("\treg[0x%x] = 0x%x\n", STRIDE, op->rd(STRIDE)); + //pr_info("\treg[0x%x] = 0x%x\n", BADDR, op->rd(BADDR)); +} + void di_mcmif_linear_rd_cfg(struct DI_MC_MIF_s *mif, unsigned int CTRL1, unsigned int CTRL2, @@ -4370,6 +4387,7 @@ void set_di_memcpy_rot(struct mem_cpy_s *cfg) if ((DIM_IS_IC_EF(T7) || DIM_IS_IC(S4)) && (!IS_ERR_OR_NULL(in_afbcd))) { + /*coverity[var_deref_op] in_afbcd has been judged*/ if (in_afbcd->index == EAFBC_DEC_IF0) { //op->bwr(AFBCDM_IF0_CTRL0,cfg->b.is_if0_4k,14,1); //reg_use_4kram @@ -4531,6 +4549,11 @@ void set_di_memcpy(struct mem_cpy_s *cfg) (1 << 30)); if ((DIM_IS_IC_EF(T7) || DIM_IS_IC(S4)) && (!IS_ERR_OR_NULL(in_afbcd))) { + /* + * IIS_ERR_OR_NULL() is a function to determine + * whether it is empty or not, but script doesn't recognize it. + */ + /* coverity[var_deref_op:SUPPRESS] */ if (in_afbcd->index == EAFBC_DEC_IF0) { //op->bwr(AFBCDM_IF0_CTRL0,cfg->b.is_if0_4k,14,1); //reg_use_4kram @@ -5777,6 +5800,13 @@ void dim_secure_pre_en(unsigned char ch) tee_config_device_state(16, 1); #endif } + if (DIM_IS_IC(S5)) { + #ifdef CONFIG_AMLOGIC_TEE + tee_write_reg_bits + (((DI_VIUB_SECURE_REG << 2) + 0xff800000), + 1, 8, 1);// HF secure Polarity + #endif + } get_datal()->is_secure_pre = 2; //dbg_mem2("%s:tvp3 pre SECURE:%d\n", __func__, ch); } else { @@ -5787,6 +5817,13 @@ void dim_secure_pre_en(unsigned char ch) tee_config_device_state(16, 0); #endif } + if (DIM_IS_IC(S5)) { + #ifdef CONFIG_AMLOGIC_TEE + tee_write_reg_bits + (((DI_VIUB_SECURE_REG << 2) + 0xff800000), + 0, 8, 1);// HF secure Polarity + #endif + } get_datal()->is_secure_pre = 1; //dbg_mem2("%s:tvp3 pre NOSECURE:%d\n", __func__, ch); } diff --git a/drivers/media/di_multi/di_interface.c b/drivers/media/di_multi/di_interface.c index 268df4d5a..05d22af66 100644 --- a/drivers/media/di_multi/di_interface.c +++ b/drivers/media/di_multi/di_interface.c @@ -588,8 +588,11 @@ enum DI_ERRORTYPE new_empty_input_buffer(int index, struct di_buffer *buffer) return DI_ERR_INDEX_OVERFLOW; } pch = get_chdata(ch); - if (pch->itf.pre_vpp_link && dpvpp_vf_ops()) + + if (pch->itf.pre_vpp_link && dpvpp_vf_ops()) { + dpvpp_patch_first_buffer(index, pch); return dpvpp_empty_input_buffer(DIM_PRE_VPP_NUB, buffer); + } pintf = &pch->itf; if (!pintf->reg) { PR_WARN("%s:ch[%d] not reg\n", __func__, ch); diff --git a/drivers/media/di_multi/di_plink_api.c b/drivers/media/di_multi/di_plink_api.c index 1bc29eec4..50cd61da6 100644 --- a/drivers/media/di_multi/di_plink_api.c +++ b/drivers/media/di_multi/di_plink_api.c @@ -4340,6 +4340,8 @@ static void dpvpph_size_change(struct dim_prevpp_ds_s *ds, bool mc_en = false;//dimp_get(edi_mp_mcpre_en) const struct reg_acc *op; unsigned int width, height, vf_type; //ori input para + struct nr_cfg_s cfg_data; + struct nr_cfg_s *cfg = &cfg_data; /*pr_info("%s:\n", __func__);*/ /*debug only:*/ @@ -4350,11 +4352,16 @@ static void dpvpph_size_change(struct dim_prevpp_ds_s *ds, height = ds->dis_c_para.win.y_size; vf_type = 0; //for p op = op_in; + cfg->width = width; + cfg->height = height; + cfg->linkflag = 1; + if (!op) op = &di_pre_regset; if (nr_op() && !(ds->en_dbg_off_nr & DI_BIT7)) - nr_op()->nr_all_config(width, height, vf_type, op); //need check if write register. + nr_op()->nr_all_config(vf_type, op, cfg); + //need check if write register. if (pulldown_en) { //dimp_get(edi_mp_pulldown_enable) /*pulldown_init(width, height);*/ @@ -4400,8 +4407,6 @@ static void dpvpph_size_change(struct dim_prevpp_ds_s *ds, // below is no use, tmp #ifdef HIS_CODE - if (de_devp->nrds_enable) - dim_nr_ds_init(width, height); if (de_devp->pps_enable && dimp_get(edi_mp_pps_position)) { pps_w = ppre->cur_width; if (vf_type & VIDTYPE_TYPEMASK) { @@ -5235,7 +5240,7 @@ static bool dpvpp_parser_nr(struct dimn_itf_s *itf, out_dvfm->vf_ext = ndvfm->c.ori_vf; out_dvfm->sum_reg_cnt = itf->sum_reg_cnt; if (ndvfm->c.set_cfg.b.en_in_cvs) { - /* configure cvs for input */ + /* config cvs for input */ cvsp = &ndvfm->c.cvspara_in; cvsp->plane_nub = in_dvfm->vfs.plane_num; cvsp->cvs_cfg = &in_dvfm->vfs.canvas0_config[0]; @@ -5243,7 +5248,7 @@ static bool dpvpp_parser_nr(struct dimn_itf_s *itf, //cvs_link(&cvspara, "in_cvs"); } if (ndvfm->c.set_cfg.b.en_wr_cvs) { - /* configure cvs for input */ + /* config cvs for input */ cvsp = &ndvfm->c.cvspara_wr; cvsp->plane_nub = out_dvfm->vfs.plane_num; cvsp->cvs_cfg = &out_dvfm->vfs.canvas0_config[0]; @@ -5252,7 +5257,7 @@ static bool dpvpp_parser_nr(struct dimn_itf_s *itf, } if (ndvfm->c.set_cfg.b.en_mem_cvs) { - /* configure cvs for input */ + /* config cvs for input */ cvsp = &ndvfm->c.cvspara_mem; cvsp->plane_nub = out_dvfm->vfs.plane_num; cvsp->cvs_cfg = &out_dvfm->vfs.canvas0_config[0]; @@ -5416,7 +5421,7 @@ static void dpvpph_display_update_all(struct dim_prevpp_ds_s *ds, ds->mif_wr.tst_not_setcontr); /* cfg cvs */ if (ndvfm->c.set_cfg.b.en_in_cvs) { - /* configure cvs for input */ + /* config cvs for input */ if (in_dvfm->vfs.canvas0Addr == (u32)-1) { cvsp = &ndvfm->c.cvspara_in; cvsp->plane_nub = in_dvfm->vfs.plane_num; @@ -5700,7 +5705,7 @@ void dpvpph_display_update_part(struct dim_prevpp_ds_s *ds, /* cfg cvs */ if (ndvfm->c.set_cfg.b.en_in_cvs) { if (in_dvfm->vfs.canvas0Addr == (u32)-1) { - /* configure cvs for input */ + /* config cvs for input */ cvsp = &ndvfm->c.cvspara_in; cvsp->plane_nub = in_dvfm->vfs.plane_num; ////update no need cvsp->cvs_cfg = &in_dvfm->vfs.canvas0_config[0];//update no need @@ -6122,6 +6127,55 @@ enum DI_ERRORTYPE dpvpp_empty_input_buffer(int index, struct di_buffer *buffer) return DI_ERR_NONE; } +void dpvpp_patch_first_buffer(int index, struct di_ch_s *pch) +{ + int i; + unsigned int cnt; + + struct buf_que_s *pbufq; + union q_buf_u q_buf; + struct dim_nins_s *ins; + bool ret; + unsigned int qt_in; + unsigned int bindex; + struct di_buffer *buffer; + + pbufq = &pch->nin_qb; + //qbuf_peek_s(pbufq, QBF_INS_Q_IN, q_buf); + if (get_datal()->dct_op && get_datal()->dct_op->is_en(pch)) + qt_in = QBF_NINS_Q_DCT; + else + qt_in = QBF_NINS_Q_CHECK; + + cnt = nins_cnt(pch, qt_in); + + if (!cnt) + return; + for (i = 0; i < cnt; i++) { + ret = qbuf_out(pbufq, qt_in, &bindex); + if (!ret) { + PR_ERR("%s:1:%d:can't get out\n", __func__, i); + continue; + } + if (bindex >= DIM_NINS_NUB) { + PR_ERR("%s:2:%d:%d\n", __func__, i, bindex); + continue; + } + q_buf = pbufq->pbuf[bindex]; + ins = (struct dim_nins_s *)q_buf.qbc; + buffer = (struct di_buffer *)ins->c.ori; + if (!buffer) { + PR_ERR("%s:3:%d,%d\n", __func__, i, bindex); + continue; + } + memset(&ins->c, 0, sizeof(ins->c)); + qbuf_in(pbufq, QBF_NINS_Q_IDLE, bindex); + + dpvpp_empty_input_buffer(DIM_PRE_VPP_NUB, buffer); + } + PR_INF("%s:%d\n", __func__, cnt); +} + /* @ary_note: buffer alloc by di */ /* @ary_note: use this api to put back display buffer */ /* @ary_note: same as vfm put */ diff --git a/drivers/media/di_multi/di_prc.c b/drivers/media/di_multi/di_prc.c index 28c520085..48693c408 100644 --- a/drivers/media/di_multi/di_prc.c +++ b/drivers/media/di_multi/di_prc.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include "deinterlace.h" @@ -53,6 +54,7 @@ bool dim_dbg_is_force_later(void) { return di_forc_pq_load_later; } + unsigned int di_dbg = DBG_M_EVENT/*|DBG_M_IC|DBG_M_MEM2|DBG_M_RESET_PRE*/; module_param(di_dbg, uint, 0664); MODULE_PARM_DESC(di_dbg, "debug print"); @@ -283,6 +285,12 @@ const struct di_cfg_ctr_s di_cfg_top_ctr[K_DI_CFG_NUB] = { EDI_CFG_AFBCE_LOSS_EN, 0, K_DI_CFG_T_FLG_DTS}, + [EDI_CFG_TB] = {"tb", + /* 0:not en; */ + /* 1:1channel; */ + EDI_CFG_TB, + 0, + K_DI_CFG_T_FLG_DTS}, [EDI_CFG_END] = {"cfg top end ", EDI_CFG_END, 0, K_DI_CFG_T_FLG_NONE}, @@ -448,6 +456,13 @@ void di_cfg_top_dts(void) if (cfgg(EN_PRE_LINK) && !IS_IC_SUPPORT(PRE_VPP_LINK)) PR_WARN("not support pre_vpp link?\n"); + + /* tb */ + if (cfgg(TB) && !IS_IC_SUPPORT(TB)) { + PR_WARN("TB not support\n"); + cfgs(TB, 0); + } + } static void di_cfgt_show_item_one(struct seq_file *s, unsigned int index) @@ -692,7 +707,7 @@ const struct di_mp_uit_s di_mp_ui_top[] = { edi_mp_pre_enable_mask, 3}, [edi_mp_post_refresh] = {"post_refresh:bool", edi_mp_post_refresh, 0}, - [edi_mp_nrds_en] = {"nrds_en:bool", + [edi_mp_nrds_en] = {"nrds_en:uint", edi_mp_nrds_en, 0}, [edi_mp_bypass_3d] = {"bypass_3d:int:def:1", edi_mp_bypass_3d, 1}, @@ -883,6 +898,11 @@ const struct di_mp_uit_s di_mp_ui_top[] = { ********************/ [edi_mp_shr_cfg] = {"shr_mode_w:uint:0:disable;0", edi_mp_shr_cfg, 0x0}, + [edi_mp_blend_mode] = {"edi_mp_blend_mode:uint:0~7coef0,8~15coef1", + edi_mp_blend_mode, 0xf2504040}, + //0~7coef0,8~15coef1,16~23coef2,24~27haa,28~31blendmode + [edi_mp_tb_dump] = {"edi_mp_tb_dump:uint:1", + edi_mp_tb_dump, 0},//1400 [EDI_MP_SUB_DI_E] = {"di end-------", EDI_MP_SUB_DI_E, 0}, /**************************************/ @@ -2079,7 +2099,8 @@ static void dip_process_reg_after(struct di_ch_s *pch) /*first channel reg*/ dpre_init(); dpost_init(); - get_dim_de_devp()->nrds_enable = 0; //nrds cause pre-vpp link crash + //get_dim_de_devp()->nrds_enable = 0; + //nrds cause pre-vpp link crash di_reg_setting(ch, vframe); get_datal()->pre_vpp_set = false; } @@ -3591,6 +3612,30 @@ struct dim_nins_s *nins_peek_pre(struct di_ch_s *pch) return ins; } +struct vframe_s *nins_peekvfm_ori(struct di_ch_s *pch) +{ + struct buf_que_s *pbufq; + union q_buf_u q_buf; + struct dim_nins_s *ins; + struct vframe_s *vfm; + bool ret; + + if (!pch || !dip_itf_is_vfm(pch)) { + PR_ERR("%s:\n", __func__); + return NULL; + } + + pbufq = &pch->nin_qb; + //qbuf_peek_s(pbufq, QBF_INS_Q_IN, q_buf); + ret = qbufp_peek(pbufq, QBF_NINS_Q_CHECK, &q_buf); + if (!ret || !q_buf.qbc) + return NULL; + ins = (struct dim_nins_s *)q_buf.qbc; + vfm = (struct vframe_s *)ins->c.ori; + + return vfm; +} + struct vframe_s *nins_peekvfm(struct di_ch_s *pch) { struct buf_que_s *pbufq; @@ -6599,7 +6644,6 @@ unsigned int di_buf_mem_get_nub(struct di_ch_s *pch) len = kfifo_len(&pch->fifo32[EDIM_QID_LMEM]); return len; } - bool dim_check_exit_process(void) { unsigned int ch; @@ -7058,6 +7102,31 @@ dim_mng_hf_err: } /*mng for hf buffer end */ + +/* for secure mode hf,from vlsi feijun*/ +static noinline int __invoke_psci_fn_vpub_smc(u64 function_id, u64 arg0, + u64 arg1, u64 arg2) +{ + struct arm_smccc_res res; + + arm_smccc_smc((unsigned long)function_id, + (unsigned long)arg0, + (unsigned long)arg1, + (unsigned long)arg2, + 0, 0, 0, 0, &res); + return res.a0; +} + +void di_probe_vpub_en_set(u32 enable) +{ + if (DIM_IS_IC(S5) && cfgg(HF)) { + if (enable) + __invoke_psci_fn_vpub_smc(0x82000080, 1, 0, 0); + else + __invoke_psci_fn_vpub_smc(0x82000080, 0, 0, 0); + } +} + /*************************************************/ #ifdef TEST_PIP diff --git a/drivers/media/di_multi/di_prc.h b/drivers/media/di_multi/di_prc.h index 9b19cff9c..956f80759 100644 --- a/drivers/media/di_multi/di_prc.h +++ b/drivers/media/di_multi/di_prc.h @@ -229,6 +229,7 @@ struct dim_nins_s *nins_peek_pre(struct di_ch_s *pch); struct dim_nins_s *nins_get(struct di_ch_s *pch); struct vframe_s *nins_peekvfm(struct di_ch_s *pch); struct vframe_s *nins_peekvfm_pre(struct di_ch_s *pch); +struct vframe_s *nins_peekvfm_ori(struct di_ch_s *pch); bool nins_out_some(struct di_ch_s *pch, struct dim_nins_s *ins, unsigned int q); @@ -350,6 +351,8 @@ void dcntr_pq_tune(struct dim_rpt_s *rpt); struct dim_rpt_s *dim_api_getrpt(struct vframe_s *vfm); void dim_pqrpt_init(struct dim_rpt_s *rpt); +void dim_tb_prob(void); +void dim_tb_t_release(struct di_ch_s *pch); void di_pq_db_setting(enum DIM_DB_SV idx); int dbg_dct_mif_show(struct seq_file *s, void *v); @@ -585,6 +588,7 @@ int dim_pre_vpp_link_display(struct vframe_s *vfm, struct pvpp_dis_para_in_s *in_para, void *out_para); enum DI_ERRORTYPE dpvpp_fill_output_buffer(int index, struct di_buffer *buffer); enum DI_ERRORTYPE dpvpp_empty_input_buffer(int index, struct di_buffer *buffer); +void dpvpp_patch_first_buffer(int index, struct di_ch_s *pch); int dpvpp_destroy_instance(int index); int dpvpp_create_instance(struct di_init_parm *parm); int dpvpp_check_vf(struct vframe_s *vfm); @@ -609,4 +613,7 @@ bool dim_is_creat_p_vpp_link(void); void dvpp_dbg_trig_sw(unsigned int cmd); int di_ls_bypass_ch(int index, bool on); bool dim_dbg_post_crash_check(unsigned int bit_mask); + +/* for secure mode hf,from vlsi feijun*/ +void di_probe_vpub_en_set(u32 enable); #endif /*__DI_PRC_H__*/ diff --git a/drivers/media/di_multi/di_pre.c b/drivers/media/di_multi/di_pre.c index 1a171d028..be78454fa 100644 --- a/drivers/media/di_multi/di_pre.c +++ b/drivers/media/di_multi/di_pre.c @@ -539,8 +539,10 @@ void dpre_mtotal_timeout_contr(void) dimh_enable_di_pre_mif(false, dimp_get(edi_mp_mcpre_en)); dcntr_dis(); - if (di_get_dts_nrds_en()) - dim_nr_ds_hw_ctrl(false); +#ifdef DIM_TB_DETECT + //if (di_get_dts_nrds_en()) + dim_nr_ds_hw_ctrl(false); +#endif pre->pres->pre_de_irq_timeout_count++; pre->pres->pre_de_busy = 0; diff --git a/drivers/media/di_multi/di_reg_v3.h b/drivers/media/di_multi/di_reg_v3.h index ac0d6bcf9..d61560fb6 100644 --- a/drivers/media/di_multi/di_reg_v3.h +++ b/drivers/media/di_multi/di_reg_v3.h @@ -2401,6 +2401,7 @@ //Bit 3:0 reg_arb_weight_ch0 //unsigned , RW,default = 10 //only pip mode use those bits,usually don't need configure + #define DI_CRC_CHK0 ((0x17c3)) /* << 2) + 0xd0100000) */ #define DI_RO_CRC_NRWR ((0x17c0)) /* << 2) + 0xd0100000) */ #define DI_RO_CRC_DEINT ((0x17c1)) /* << 2) + 0xd0100000) */ @@ -2414,6 +2415,8 @@ #define DI_PRE_SEC_IN 0x2010 #define DI_POST_SEC_IN 0x2011 #define DI_VIU_DATA_SEC 0x1A50 +#define DI_VIUB_SECURE_REG 0x200F +//for s5 from vlsi feijun HF secure Polarity //t7 #define CONTRD_BADDR 0x3729 diff --git a/drivers/media/di_multi/di_sys.c b/drivers/media/di_multi/di_sys.c index 9d69493f6..136e1b0f8 100644 --- a/drivers/media/di_multi/di_sys.c +++ b/drivers/media/di_multi/di_sys.c @@ -60,6 +60,7 @@ #include "di_dbg.h" #include "di_vframe.h" #include "di_task.h" +#include "tb_task.h" #include "di_prc.h" #include "di_sys.h" #include "di_api.h" @@ -75,10 +76,12 @@ struct di_dev_s *get_dim_de_devp(void) return di_pdev; } +#ifdef MARK_TB unsigned int di_get_dts_nrds_en(void) { return get_dim_de_devp()->nrds_enable; } +#endif u8 *dim_vmap(ulong addr, u32 size, bool *bflg) { @@ -323,8 +326,6 @@ unsigned int dim_cma_alloc_total(struct di_dev_s *de_devp) return 0; mmt->mem_start = omm.addr; mmt->total_pages = omm.ppage; - if (cfgnq(MEM_FLAG, EDI_MEM_M_REV) && de_devp->nrds_enable) - dim_nr_ds_buf_init(cfgg(MEM_FLAG), 0, &de_devp->pdev->dev, 0); return 1; } @@ -3060,6 +3061,8 @@ bool qiat_all_back2_ready(struct di_ch_s *pch) unsigned int len; struct buf_que_s *pbufq; int i; + bool ret; + bool err = false; unsigned int index; union q_buf_u q_buf; @@ -3067,13 +3070,19 @@ bool qiat_all_back2_ready(struct di_ch_s *pch) len = qbufp_count(pbufq, QBF_IAT_Q_IN_USED); for (i = 0; i < len; i++) { - qbuf_out(pbufq, QBF_IAT_Q_IN_USED, &index); + ret = qbuf_out(pbufq, QBF_IAT_Q_IN_USED, &index); + if (!ret) { + PR_ERR("%s:%d\n", __func__, i); + err = true; + break; + } q_buf = pbufq->pbuf[index]; qbuf_in(pbufq, QBF_IAT_Q_READY, index); } len = qbufp_count(pbufq, QBF_IAT_Q_READY); dbg_reg("%s:len[%d]\n", __func__, len); - + if (err) + return false; return true; } @@ -3724,7 +3733,8 @@ static const struct di_meson_data data_s5 = { .name = "dim_s5", .ic_id = DI_IC_ID_S5, .support = IC_SUPPORT_HDR | - IC_SUPPORT_DW + IC_SUPPORT_DW | + IC_SUPPORT_TB }; /* #ifdef CONFIG_USE_OF */ @@ -3861,8 +3871,8 @@ static int dim_probe(struct platform_device *pdev) /* move to dim_mem_prob dim_rev_mem(di_devp);*/ - ret = of_property_read_u32(pdev->dev.of_node, - "nrds-enable", &di_devp->nrds_enable); + //ret = of_property_read_u32(pdev->dev.of_node, + //"nrds-enable", &di_devp->nrds_enable); ret = of_property_read_u32(pdev->dev.of_node, "pps-enable", &di_devp->pps_enable); @@ -3879,10 +3889,11 @@ static int dim_probe(struct platform_device *pdev) /* mutex_init(&di_devp->cma_mutex); */ INIT_LIST_HEAD(&di_devp->pq_table_list); - +#ifdef HIS_CODE atomic_set(&di_devp->pq_flag, 1); /* idle */ atomic_set(&di_devp->pq_io, 1); /* idle */ - +#endif + mutex_init(&di_devp->lock_pq); di_devp->pre_irq = irq_of_parse_and_map(pdev->dev.of_node, 0); dbg_mem("pre_irq:%d\n", di_devp->pre_irq); di_devp->post_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); @@ -3998,6 +4009,7 @@ static int dim_probe(struct platform_device *pdev) dimp_get(edi_mp_mcpre_en)); dim_set_di_flag(); + di_probe_vpub_en_set(1); dim_polic_prob(); dct_pre_prob(pdev); dcntr_prob(); @@ -4005,9 +4017,11 @@ static int dim_probe(struct platform_device *pdev) dip_prob_ch(); dim_hdr_prob(); dim_mng_hf_prob(); + dim_tb_prob(); task_start(); mtask_start(); + tb_task_start(); if (DIM_IS_IC_EF(SC2)) opl1()->pst_mif_sw(false, DI_MIF0_SEL_PST_ALL); else @@ -4070,6 +4084,7 @@ static int dim_remove(struct platform_device *pdev) task_stop(); mtask_stop(); + tb_task_stop(); dim_rdma_exit(); diff --git a/drivers/media/di_multi/di_vframe.c b/drivers/media/di_multi/di_vframe.c index bbdd06947..b2bf1e9b9 100644 --- a/drivers/media/di_multi/di_vframe.c +++ b/drivers/media/di_multi/di_vframe.c @@ -326,7 +326,7 @@ static struct vframe_s *dim_nbypass_peek(struct di_ch_s *pch) { struct vframe_s *vframe; - vframe = nins_peekvfm(pch); + vframe = nins_peekvfm_ori(pch); return vframe; } diff --git a/drivers/media/di_multi/nr_downscale.c b/drivers/media/di_multi/nr_downscale.c index c6fb657f1..988a0b0b3 100644 --- a/drivers/media/di_multi/nr_downscale.c +++ b/drivers/media/di_multi/nr_downscale.c @@ -27,20 +27,1192 @@ #include #include #include +#include +#include #include "register.h" #include "nr_downscale.h" -#include "deinterlace.h" - #include "di_data_l.h" #include "di_sys.h" #include "di_api.h" +#include "di_dbg.h" +#include "di_prc.h" +#include "di_reg_v3.h" +#include "tb_task.h" -static struct nr_ds_s nrds_dev; +#ifdef DIM_TB_DETECT +struct tb_core_s { + unsigned int di_tb_quit_flag : 1, + first_frame : 1, + reset_tb : 1, + cur_invert : 2, + cur_invert_a : 2, + cur_invert_b : 2, + cur_invert_c : 2, + nr_dump_en : 1, + rev : 20; + u8 dim_tb_detect_last_flag; + unsigned int di_tb_buff_wptr; + unsigned int di_tb_buff_rptr; + s8 di_tb_buffer_status; + unsigned int di_tb_buffer_start; + void *virt; + unsigned int di_tb_buffer_size; + unsigned int di_tb_buffer_len; + u8 di_tb_first_frame_type; + int first_frame_type; + unsigned int skip_picture; + u8 last_type; + unsigned int last_width; + unsigned int last_height; + unsigned int di_tb_init_mute; + unsigned int init_mute; + atomic_t di_tb_sem; + atomic_t dim_detect_status; + atomic_t dim_tb_detect_flag; + atomic_t di_tb_reset_flag; + atomic_t di_tb_skip_flag; + atomic_t di_tb_run_flag; + struct dim_tb_buf_s di_detect_buf[DIM_TB_BUFFER_MAX_SIZE]; + struct dim_tb_buf_s di_detect_wbuf[DIM_TB_BUFFER_MAX_SIZE]; + unsigned int nr_dump_count; + int di_init; + unsigned char flg_from; +}; -static void nr_ds_hw_init(unsigned int width, unsigned int height) +//static struct tb_core_s dim_tbs[DI_CHANNEL_NUB]; +static struct tb_core_s *dim_tbs[DI_CHANNEL_NUB]; + +//struct tb_core_s *get_dim_tb(void) +//{ +// return dim_tbs; +//} + +static DEFINE_MUTEX(di_tb_mutex); + +static s32 di_tb_canvas = -1; +static struct TB_DetectFuncPtr *digfunc; +static struct tbff_stats *di_tb_reg[DI_CHANNEL_NUB]; + +//static u32 di_tb_src_canvas; +#endif + +#define NR_DETECT_DUMP_CNT 150 + +#ifdef DIM_TB_DETECT +static int diwrite_to_file(unsigned long dump_adr, int size, unsigned int ch) +{ +#ifdef CONFIG_AMLOGIC_ENABLE_MEDIA_FILE + int ret = 0; + struct file *fp = NULL; + mm_segment_t old_fs; + bool bflg_vmap = false; + void *buff = NULL; + loff_t pos = 0; + int nwrite = 0; + int offset = 0; + char parm[64]; + /* change to KERNEL_DS address limit */ + old_fs = get_fs(); + set_fs(KERNEL_DS); + //PR_ERR("11%s: open file ok\n", __func__); + /* open file to write */ + //fp = filp_open("/storage/A2DC-E6BA/tb.yuv", + //O_WRONLY | O_CREAT | O_APPEND, 0777); + sprintf(parm, "/storage/A2DC-E6BA/tb%d.yuv", ch); + fp = filp_open(parm, O_WRONLY | O_CREAT | O_APPEND, 0777); + //sprintf(parm, "/storage/A2DC-E6BA/TEST4/yuv00%d", didump_tb_cont++); + //fp = filp_open(parm, O_WRONLY | O_CREAT, 0666); + //PR_ERR("22%s: open file ok\n", __func__); + if (IS_ERR_OR_NULL(fp)) { + PR_ERR("%s: open file error\n", __func__); + ret = -1; + goto exit; + } + buff = dim_vmap(dump_adr, size, &bflg_vmap); + //PR_ERR("%s:vmap:0x%x\n", __func__, (unsigned int *)buff); + + pos = (unsigned long)offset; + //buff = codec_mm_vmap(dump_adr, size); + //PR_ERR("%s:vmap:0x%p\n", __func__, buff); + /* Write buf to file */ + if (IS_ERR_OR_NULL(buff)) + PR_ERR("%s: ioremap error.\n", __func__); + + nwrite = vfs_write(fp, buff, size, &pos); + offset += nwrite; + vfs_fsync(fp, 0); + if (bflg_vmap) + dim_unmap_phyaddr(buff); + + filp_close(fp, NULL); + + //PR_ERR("33%s: open file ok\n", __func__); +exit: + set_fs(old_fs); +#endif + return 0; //ret; +} + +int dim_tb_detect(struct vframe_tb_s *vf, int data1, unsigned int ch) +{ + bool is_top; + const struct reg_acc *op = &di_pre_regset; + struct tb_core_s *pcfg; + struct di_dev_s *di_devp = get_dim_de_devp(); + + dbg_tb("%s :step 3 s\n", __func__); + + pcfg = dim_tbs[ch]; + + if (!di_devp->tb_flag_int) + return -1; + + if (unlikely(!vf)) + return -1; + + if (pcfg->di_tb_buff_wptr & 1) + is_top = false; + else + is_top = true; + + if (data1 == 0) { + if ((vf->type & VIDTYPE_TYPEMASK) == VIDTYPE_INTERLACE_BOTTOM) { + pcfg->di_detect_buf[0].paddr = + pcfg->di_detect_wbuf[1].paddr; + pcfg->di_detect_buf[1].paddr = + pcfg->di_detect_wbuf[0].paddr; + pcfg->di_detect_buf[2].paddr = + pcfg->di_detect_wbuf[3].paddr; + pcfg->di_detect_buf[3].paddr = + pcfg->di_detect_wbuf[2].paddr; + pcfg->di_detect_buf[4].paddr = + pcfg->di_detect_wbuf[5].paddr; + pcfg->di_detect_buf[5].paddr = + pcfg->di_detect_wbuf[4].paddr; + pcfg->di_detect_buf[6].paddr = + pcfg->di_detect_wbuf[7].paddr; + pcfg->di_detect_buf[7].paddr = + pcfg->di_detect_wbuf[6].paddr; + pcfg->cur_invert_a = 1;//dump + pcfg->cur_invert_b = 1;//revert + pcfg->cur_invert_c = 1;//normal + dbg_tb("%s:NR01A %x\n", __func__, data1); + } else { + pcfg->di_detect_buf[0].paddr = + pcfg->di_detect_wbuf[0].paddr; + pcfg->di_detect_buf[1].paddr = + pcfg->di_detect_wbuf[1].paddr; + pcfg->di_detect_buf[2].paddr = + pcfg->di_detect_wbuf[2].paddr; + pcfg->di_detect_buf[3].paddr = + pcfg->di_detect_wbuf[3].paddr; + pcfg->di_detect_buf[4].paddr = + pcfg->di_detect_wbuf[4].paddr; + pcfg->di_detect_buf[5].paddr = + pcfg->di_detect_wbuf[5].paddr; + pcfg->di_detect_buf[6].paddr = + pcfg->di_detect_wbuf[6].paddr; + pcfg->di_detect_buf[7].paddr = + pcfg->di_detect_wbuf[7].paddr; + pcfg->cur_invert_a = 0; + pcfg->cur_invert_b = 2; + pcfg->cur_invert_c = 2; + dbg_tb("%s:NR01B %x\n", __func__, data1); + } + } + if (pcfg->cur_invert && pcfg->cur_invert_b) { + if (pcfg->cur_invert_b == 1) { + pcfg->di_detect_buf[0].paddr = + pcfg->di_detect_wbuf[0].paddr; + pcfg->di_detect_buf[1].paddr = + pcfg->di_detect_wbuf[1].paddr; + pcfg->di_detect_buf[2].paddr = + pcfg->di_detect_wbuf[2].paddr; + pcfg->di_detect_buf[3].paddr = + pcfg->di_detect_wbuf[3].paddr; + pcfg->di_detect_buf[4].paddr = + pcfg->di_detect_wbuf[4].paddr; + pcfg->di_detect_buf[5].paddr = + pcfg->di_detect_wbuf[5].paddr; + pcfg->di_detect_buf[6].paddr = + pcfg->di_detect_wbuf[6].paddr; + pcfg->di_detect_buf[7].paddr = + pcfg->di_detect_wbuf[7].paddr; + pcfg->cur_invert_a = 0; + pcfg->cur_invert_c = 1; + dbg_tb("%s:NR01C %x\n", __func__, data1); + + } else { + pcfg->di_detect_buf[0].paddr = + pcfg->di_detect_wbuf[1].paddr; + pcfg->di_detect_buf[1].paddr = + pcfg->di_detect_wbuf[0].paddr; + pcfg->di_detect_buf[2].paddr = + pcfg->di_detect_wbuf[3].paddr; + pcfg->di_detect_buf[3].paddr = + pcfg->di_detect_wbuf[2].paddr; + pcfg->di_detect_buf[4].paddr = + pcfg->di_detect_wbuf[5].paddr; + pcfg->di_detect_buf[5].paddr = + pcfg->di_detect_wbuf[4].paddr; + pcfg->di_detect_buf[6].paddr = + pcfg->di_detect_wbuf[7].paddr; + pcfg->di_detect_buf[7].paddr = + pcfg->di_detect_wbuf[6].paddr; + pcfg->cur_invert_a = 1; + pcfg->cur_invert_c = 2; + dbg_tb("%s:NR01D %x\n", __func__, data1); + } + pcfg->cur_invert_b = 0; + } + if (!pcfg->cur_invert && !pcfg->cur_invert_b && pcfg->cur_invert_c) { + if (pcfg->cur_invert_c == 1) { + pcfg->di_detect_buf[0].paddr = + pcfg->di_detect_wbuf[1].paddr; + pcfg->di_detect_buf[1].paddr = + pcfg->di_detect_wbuf[0].paddr; + pcfg->di_detect_buf[2].paddr = + pcfg->di_detect_wbuf[3].paddr; + pcfg->di_detect_buf[3].paddr = + pcfg->di_detect_wbuf[2].paddr; + pcfg->di_detect_buf[4].paddr = + pcfg->di_detect_wbuf[5].paddr; + pcfg->di_detect_buf[5].paddr = + pcfg->di_detect_wbuf[4].paddr; + pcfg->di_detect_buf[6].paddr = + pcfg->di_detect_wbuf[7].paddr; + pcfg->di_detect_buf[7].paddr = + pcfg->di_detect_wbuf[6].paddr; + pcfg->cur_invert_a = 1; + pcfg->cur_invert_b = 1; + dbg_tb("%s:NR01E %x\n", __func__, data1); + } else { + pcfg->di_detect_buf[0].paddr = + pcfg->di_detect_wbuf[0].paddr; + pcfg->di_detect_buf[1].paddr = + pcfg->di_detect_wbuf[1].paddr; + pcfg->di_detect_buf[2].paddr = + pcfg->di_detect_wbuf[2].paddr; + pcfg->di_detect_buf[3].paddr = + pcfg->di_detect_wbuf[3].paddr; + pcfg->di_detect_buf[4].paddr = + pcfg->di_detect_wbuf[4].paddr; + pcfg->di_detect_buf[5].paddr = + pcfg->di_detect_wbuf[5].paddr; + pcfg->di_detect_buf[6].paddr = + pcfg->di_detect_wbuf[6].paddr; + pcfg->di_detect_buf[7].paddr = + pcfg->di_detect_wbuf[7].paddr; + pcfg->cur_invert_a = 0; + pcfg->cur_invert_b = 2; + dbg_tb("%s:NR01F %x\n", __func__, data1); + } + pcfg->cur_invert_c = 0; + } + + canvas_config(di_tb_canvas, + pcfg->di_detect_buf[pcfg->di_tb_buff_wptr].paddr, + DIM_TB_DETECT_W, DIM_TB_DETECT_H, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + op->bwr(NRDSWR_CTRL, di_tb_canvas, 0, 8); + if (DIM_IS_IC_EF(T7)) + di_mif1_linear_wr_cfgds + (pcfg->di_detect_buf[pcfg->di_tb_buff_wptr].paddr, + NRDSWR_STRIDE, NRDSWR_BADDR); + //dim_nr_ds_hw_ctrl(true); + dbg_tb("%s:e:ch[%d]dump %x frames start\n", __func__, ch, + pcfg->di_tb_buff_wptr); + return 1; +} + +void dim_ds_detect(struct vframe_tb_s *vf, int data1, unsigned int ch) +{ + struct di_dev_s *di_devp = get_dim_de_devp(); + struct tb_core_s *pcfg; + struct di_ch_s *pch; + int ret = 0; + + pch = get_chdata(ch); + + if (!di_devp->tb_flag_int) + return; + if (!pch->en_tb) { + //dim_nr_ds_hw_ctrl(false); + return; + } + dbg_tb("%s :step 2 s\n", __func__); + pcfg = dim_tbs[ch]; + + if (vf->source_type != + VFRAME_SOURCE_TYPE_OTHERS) + return; + if ((vf->width * vf->height) + > (1920 * 1088)) { + // greater than (1920 * 1088), do not detect + return; + } + + if (pcfg->di_tb_buff_wptr < pcfg->di_tb_buffer_len) { + ret = dim_tb_detect(vf, data1, ch); + dbg_tb("%s:TB tb detect00,data1=%X\n", __func__, data1); + } else { + dbg_tb("%s :TB tb detect skip case2\n", __func__); + atomic_set(&pcfg->di_tb_skip_flag, 1); + pcfg->skip_picture++; + } + if (ret > 0) { + pcfg->di_tb_buff_wptr++; + if (pcfg->di_tb_buff_wptr >= DIM_TB_ALGO_COUNT && + (atomic_read(&pcfg->dim_detect_status) + == di_tb_idle)) { + atomic_set + (&pcfg->dim_detect_status, + di_tb_running); + dbg_tb("%s:TB tb detect01=%d\n", __func__, + pcfg->di_tb_buff_wptr); + } + if (pcfg->di_tb_buff_wptr >= DIM_TB_ALGO_COUNT) { + atomic_set(&pcfg->di_tb_sem, 1); + dbg_tb("%s:TB tb detect02=%d\n", __func__, + pcfg->di_tb_buff_wptr); + } + } +} + +void dim_tb_function(struct vframe_tb_s *vf, int data1, unsigned int ch) +{ + int ret = 0; + struct di_dev_s *di_devp = get_dim_de_devp(); + struct tb_core_s *pcfg; + struct di_ch_s *pch; + //const struct reg_acc *op = &di_pre_regset; + + pch = get_chdata(ch); + + if (!di_devp->tb_flag_int) + return; + if (!pch->en_tb) { + //dim_nr_ds_hw_ctrl(false); + return; + } + //dbg_tb("%s :s\n", __func__); + pcfg = dim_tbs[ch]; + + if (vf->source_type != + VFRAME_SOURCE_TYPE_OTHERS) + goto SKIP_DETECT; + if ((vf->width * vf->height) + > (1920 * 1088)) { + // greater than (1920 * 1088), do not detect + goto SKIP_DETECT; + } + + dbg_tb("%s:step 1 ch[%d]type=%x,cur_invert=%x,%x,%x,%x\n", __func__, + ch, vf->type, pcfg->cur_invert, vf->width, vf->height, data1); + + //op->bwr(NR_DS_CTRL, vf->width / NR_DS_WIDTH, 16, 6); + //op->bwr(NR_DS_CTRL, vf->height / 2 / NR_DS_HEIGHT, 24, 6); + + //if (data1 == 0) + //pcfg->first_frame = 1; + if (pcfg->first_frame) { + pcfg->last_type = vf->type & VIDTYPE_TYPEMASK; + pcfg->last_width = vf->width; + pcfg->last_height = vf->height; + pcfg->first_frame_type = pcfg->last_type; + pcfg->di_tb_first_frame_type = pcfg->last_type; + pcfg->first_frame = 0; + pcfg->reset_tb = 0; + pcfg->skip_picture = 0; + pcfg->cur_invert = 0; + pcfg->init_mute = pcfg->di_tb_init_mute; + atomic_set(&pcfg->di_tb_skip_flag, 1); + atomic_set(&pcfg->di_tb_reset_flag, 0); + dbg_tb("%s:first f type:%x,first_frame_type %X\n", __func__, + pcfg->last_type, pcfg->first_frame_type); + } else if ((pcfg->last_type == + (vf->type & VIDTYPE_TYPEMASK)) && pcfg->last_type) { + /* interlace seq changed */ + pcfg->first_frame_type = + vf->type & VIDTYPE_TYPEMASK; + pcfg->di_tb_first_frame_type = + pcfg->first_frame_type; + pcfg->reset_tb = 1; + data1 = 0; + /* keep old invert */ + dbg_tb("%s:DI:TB interlace seq chg,old:%d,new:%d,invert: %d\n", + __func__, + pcfg->last_type, + pcfg->first_frame_type, + pcfg->cur_invert); + } else if ((pcfg->last_type == 0) && + ((vf->type & VIDTYPE_TYPEMASK) != 0)) { + /* prog -> interlace changed */ + pcfg->first_frame_type = + vf->type & VIDTYPE_TYPEMASK; + pcfg->di_tb_first_frame_type = + pcfg->first_frame_type; + pcfg->reset_tb = 1; + dbg_tb("%s:TB prog -> interlace, new type: %d, invert: %d\n", + __func__, pcfg->first_frame_type, pcfg->cur_invert); + /* not invert */ + pcfg->cur_invert = 0; + } else if (((pcfg->last_width != vf->width) || + (pcfg->last_height != vf->height)) && + ((vf->type & VIDTYPE_TYPEMASK) != 0)) { + /* size changed and next seq is interlace */ + pcfg->first_frame_type = + vf->type & VIDTYPE_TYPEMASK; + pcfg->di_tb_first_frame_type = + pcfg->first_frame_type; + pcfg->reset_tb = 1; + /* keep old invert */ + dbg_tb("%s:TB tb size change new type: %d, invert: %d\n", + __func__, pcfg->first_frame_type, pcfg->cur_invert); + } else if ((pcfg->last_type != 0) && + ((vf->type & VIDTYPE_TYPEMASK) == 0)) { + /* interlace -> prog changed */ + dbg_tb("%s:TB tb interlace -> prog, invert: %d\n", + __func__, pcfg->cur_invert); + /* not invert */ + pcfg->cur_invert = 0; + } + pcfg->last_type = vf->type & VIDTYPE_TYPEMASK; + pcfg->last_width = vf->width; + pcfg->last_height = vf->height; + dbg_tb("%s:S frame type: %x,first_frame_type %X,cur_invert=%x\n", __func__, + pcfg->last_type, pcfg->first_frame_type, pcfg->cur_invert); + if (di_devp->tb_flag_int) { + ret = 0; + if (pcfg->di_tb_buffer_status <= 0) + goto SKIP_DETECT; + di_devp->tb_detect_buf_len = pcfg->di_tb_buffer_len; + vf->type = (vf->type & ~TB_DETECT_MASK); + if (pcfg->init_mute > 0) { + pcfg->init_mute--; + atomic_set(&pcfg->di_tb_skip_flag, 1); + goto SKIP_DETECT; + } + if (pcfg->last_type == 0) {/* cur type is prog */ + pcfg->skip_picture++; + pcfg->cur_invert = 0; + goto SKIP_DETECT; + } + vf->type |= + pcfg->cur_invert << + TB_DETECT_MASK_BIT; + dbg_tb("%s: M first f type:%x,first_frame_type %X\n", __func__, + pcfg->last_type, pcfg->first_frame_type); + + if (pcfg->reset_tb) { + /* wait tb task done */ + while ((pcfg->di_tb_buff_wptr >= DIM_TB_ALGO_COUNT) && + (pcfg->di_tb_buff_rptr <= + pcfg->di_tb_buff_wptr - DIM_TB_ALGO_COUNT) && + (atomic_read(&pcfg->di_tb_run_flag) == 1)) + usleep_range(100, 200); + //usleep_range(4000, 5000); + atomic_set(&pcfg->dim_detect_status, di_tb_idle); + pcfg->di_tb_buff_wptr = 0; + pcfg->di_tb_buff_rptr = 0; + atomic_set(&pcfg->dim_tb_detect_flag, TB_DETECT_NC); + atomic_set(&pcfg->di_tb_reset_flag, 1); + atomic_set(&pcfg->di_tb_skip_flag, 1); + pcfg->skip_picture = 0; + pcfg->reset_tb = 0; + dbg_tb("%s reset once\n", __func__); + } + if ((atomic_read(&pcfg->dim_detect_status) == di_tb_done) && + pcfg->skip_picture >= + di_devp->tb_detect_period && + pcfg->last_type == pcfg->first_frame_type) { + int tbf_flag = + atomic_read(&pcfg->dim_tb_detect_flag); + u8 old_invert = pcfg->cur_invert; + + atomic_set(&pcfg->dim_detect_status, di_tb_idle); + pcfg->di_tb_buff_wptr = 0; + pcfg->di_tb_buff_rptr = 0; + pcfg->skip_picture = 0; + if (tbf_flag == TB_DETECT_TBF && + pcfg->first_frame_type == VIDTYPE_INTERLACE_TOP) { + /* TBF sams as BFF */ + vf->type |= + TB_DETECT_INVERT + << TB_DETECT_MASK_BIT; + pcfg->cur_invert = 1; + } else if ((tbf_flag == TB_DETECT_BFF) && + (pcfg->first_frame_type == + VIDTYPE_INTERLACE_TOP)) { + vf->type |= + TB_DETECT_INVERT + << TB_DETECT_MASK_BIT; + pcfg->cur_invert = 1; + } else if ((tbf_flag == TB_DETECT_TFF) && + (pcfg->first_frame_type == + VIDTYPE_INTERLACE_BOTTOM)) { + vf->type |= + TB_DETECT_INVERT + << TB_DETECT_MASK_BIT; + pcfg->cur_invert = 1; + } else if (tbf_flag != TB_DETECT_NC) { + pcfg->cur_invert = 0; + } + vf->type = (vf->type & ~TB_DETECT_MASK); + vf->type |= + pcfg->cur_invert << + TB_DETECT_MASK_BIT; + dbg_tb("%s process mask:vf[0x%x] type=0x%x\n", + __func__, vf->omx_index, vf->type); + if (old_invert != pcfg->cur_invert) + dbg_tb + ("%s:flag00: %d->%d, invert: %d->%d\n", + __func__, + pcfg->dim_tb_detect_last_flag, + tbf_flag, + old_invert, + pcfg->cur_invert); + else if (pcfg->dim_tb_detect_last_flag != tbf_flag) + dbg_tb + ("%s:flag01: %d->%d, invert: %d\n", + __func__, + pcfg->dim_tb_detect_last_flag, + tbf_flag, + pcfg->cur_invert); + pcfg->dim_tb_detect_last_flag = tbf_flag; + atomic_set(&pcfg->dim_tb_detect_flag, TB_DETECT_NC); + } + + if (pcfg->di_tb_buff_wptr == 0 && + pcfg->last_type != pcfg->first_frame_type) { + pcfg->skip_picture++; + atomic_set(&pcfg->di_tb_skip_flag, 1); + dbg_tb("%s:TB tb detect skip case1\n", __func__); + goto SKIP_DETECT; + } + } else { + pcfg->reset_tb = 1; + pcfg->skip_picture++; + pcfg->cur_invert = 0; + if (pcfg->init_mute > 0) + pcfg->init_mute--; + dbg_tb("%s :step 1 else\n", __func__); + } + dbg_tb("%s :step 1 e\n", __func__); + +SKIP_DETECT: + if (pcfg->skip_picture > + di_devp->tb_detect_period) { + pcfg->skip_picture = + di_devp->tb_detect_period; + dbg_tb("%s :skip\n", __func__); + } +} + +int dim_tb_buffer_init(unsigned int ch) +{ + int i; + //int flags = CODEC_MM_FLAGS_DMA_CPU | CODEC_MM_FLAGS_CMA_CLEAR; + //int flags = 0; + struct di_dev_s *di_devp = get_dim_de_devp(); + struct tb_core_s *pcfg; + struct dim_mm_s omm; + //struct div2_mm_s *mm; + bool ret; + struct di_ch_s *pch; + + PR_INF("%s :s\n", __func__); + + if (!di_devp->tb_flag_int) + return -1; + + pch = get_chdata(ch); + if (!pch->en_tb) + return -1; + + pcfg = dim_tbs[ch]; + + di_tb_reg[ch] = kmalloc(sizeof(*di_tb_reg[ch]), GFP_KERNEL); + if (!di_tb_reg[ch]) + return -1; + + memset(di_tb_reg[ch], 0, sizeof(struct tbff_stats)); + + if (pcfg->di_tb_buffer_status) + return pcfg->di_tb_buffer_status; + + if (di_tb_canvas < 0) + di_tb_canvas = + canvas_pool_map_alloc_canvas("tb_detect_dst"); + + if (di_tb_canvas < 0) + return -1; + + if (pcfg->di_tb_buffer_start == 0 && pch->en_tb) { + if (!di_devp->tb_detect_buf_len) + di_devp->tb_detect_buf_len = 8; + pcfg->di_tb_buffer_len = di_devp->tb_detect_buf_len; + pcfg->di_tb_buffer_size = DIM_TB_DETECT_H * DIM_TB_DETECT_W + * pcfg->di_tb_buffer_len; + pcfg->di_tb_buffer_size = PAGE_ALIGN(pcfg->di_tb_buffer_size); + ret = mm_cma_alloc(NULL, + pcfg->di_tb_buffer_size >> PAGE_SHIFT, + &omm); + pcfg->flg_from = 1; + if (!ret) { + pcfg->flg_from = 2; + ret = mm_cma_alloc(&di_devp->pdev->dev, + pcfg->di_tb_buffer_size >> PAGE_SHIFT, + &omm); + if (!ret) { + PR_ERR("%s:cma\n", __func__); + pcfg->flg_from = 0; + return -1; + } + } + pcfg->di_tb_buffer_start = omm.addr; + pcfg->virt = omm.ppage; + + dbg_tb("%s:ch[%d] %x, size %x, item %d\n", __func__, ch, + (unsigned int)pcfg->di_tb_buffer_start, + (unsigned int)pcfg->di_tb_buffer_size, + pcfg->di_tb_buffer_len); + if (pcfg->di_tb_buffer_start == 0) { + PR_ERR("di:err:DI:TB cma memory config fail\n"); + pcfg->di_tb_buffer_status = -1; + return -1; + } + for (i = 0; i < pcfg->di_tb_buffer_len; i++) { + pcfg->di_detect_buf[i].paddr = + pcfg->di_tb_buffer_start + + DIM_TB_DETECT_H * DIM_TB_DETECT_W * i; + pcfg->di_detect_buf[i].vaddr = + (ulong)codec_mm_vmap + (pcfg->di_detect_buf[i].paddr, + DIM_TB_DETECT_H * DIM_TB_DETECT_W); + pcfg->di_detect_wbuf[i].paddr = + pcfg->di_detect_buf[i].paddr; + dbg_tb("%s:TBbuf(%d)paddr:%lx,vaddr: %lx,vaddr: %lx\n", + __func__, i, pcfg->di_detect_buf[i].paddr, + pcfg->di_detect_buf[i].vaddr, + pcfg->di_detect_wbuf[i].paddr); + } + } + pcfg->di_tb_buffer_status = 1; + dbg_tb("%s :e\n", __func__); + return 1; +} + +int dim_tb_buffer_uninit(unsigned int ch) +{ + int i; + struct tb_core_s *pcfg; + struct di_dev_s *di_devp = get_dim_de_devp(); + struct di_ch_s *pch; + + dbg_tb("%s :s\n", __func__); + + pch = get_chdata(ch); + pcfg = dim_tbs[ch]; + + if (!di_devp->tb_flag_int) + return 0; + if (!pch->en_tb) + return 0; + if (pcfg->di_tb_buffer_status <= 0) + return 0; + + if (di_tb_canvas >= 0) + canvas_pool_map_free_canvas(di_tb_canvas); + di_tb_canvas = -1; + if (pcfg->di_tb_buffer_start) { + dbg_tb("%s:ch[%d] free addr is %x, size is %x\n", __func__, ch, + (unsigned int)pcfg->di_tb_buffer_start, + (unsigned int)pcfg->di_tb_buffer_size); + for (i = 0; i < pcfg->di_tb_buffer_len; i++) { + if (pcfg->di_detect_buf[i].vaddr) { + codec_mm_unmap_phyaddr + ((u8 *)pcfg->di_detect_buf[i].vaddr); + pcfg->di_detect_buf[i].vaddr = 0; + } + } + if (pcfg->flg_from == 2) + dma_release_from_contiguous + (&di_devp->pdev->dev, + (struct page *)pcfg->virt, + pcfg->di_tb_buffer_size >> PAGE_SHIFT); + else + dma_release_from_contiguous + (NULL, + (struct page *)pcfg->virt, + pcfg->di_tb_buffer_size >> PAGE_SHIFT); + pcfg->di_tb_buffer_start = 0; + pcfg->di_tb_buffer_size = 0; + pcfg->virt = NULL; + } + pcfg->di_tb_buffer_status = 0; + + kfree(di_tb_reg[ch]); + di_tb_reg[ch] = NULL; + //di_devp->tb_detect = 0x8; + dbg_tb("%s :e\n", __func__); + return 0; +} + +void dim_tb_reg_init(struct vframe_tb_s *vfm, unsigned int on, unsigned int ch) +{ + int val = 0; + struct di_dev_s *di_devp = get_dim_de_devp(); + struct tb_core_s *pcfg; + struct di_ch_s *pch; + + dbg_tb("%s :s\n", __func__); + + pch = get_chdata(ch); + + if (vfm->source_type != + VFRAME_SOURCE_TYPE_OTHERS) + return; + if ((vfm->width * vfm->height) > (1920 * 1088)) + return; + if (!di_devp->tb_flag_int) + return; + if (!pch->en_tb) + return; + if (!(vfm->type & VIDTYPE_TYPEMASK)) + return; + + pcfg = dim_tbs[ch]; + + if (on) { + atomic_set(&pcfg->di_tb_sem, val); + memset(pcfg->di_detect_buf, 0, sizeof(pcfg->di_detect_buf)); + memset(pcfg->di_detect_wbuf, 0, sizeof(pcfg->di_detect_wbuf)); + atomic_set(&pcfg->dim_detect_status, di_tb_idle); + atomic_set(&pcfg->dim_tb_detect_flag, TB_DETECT_NC); + atomic_set(&pcfg->di_tb_reset_flag, 0); + atomic_set(&pcfg->di_tb_skip_flag, 0); + atomic_set(&pcfg->di_tb_run_flag, 1); + //di_devp->tb_detect = 0x8; + di_devp->tb_detect_period = 0; + di_devp->tb_detect_buf_len = 8; + di_devp->tb_detect_init_mute = 0; + + pcfg->dim_tb_detect_last_flag = TB_DETECT_NC; + pcfg->di_tb_buff_wptr = 0; + pcfg->di_tb_buff_rptr = 0; + pcfg->di_tb_buffer_status = 0; + pcfg->di_tb_buffer_start = 0; + pcfg->di_tb_buffer_size = 0; + pcfg->di_tb_first_frame_type = 0; + pcfg->di_tb_quit_flag = 0; + pcfg->di_tb_init_mute = di_devp->tb_detect_init_mute; + pcfg->cur_invert_b = 0; + pcfg->cur_invert_a = 0; + pcfg->first_frame = 1; + pcfg->di_tb_buffer_len = DIM_TB_BUFFER_MAX_SIZE; + pcfg->nr_dump_en = 0; + pcfg->nr_dump_count = 0; + pcfg->skip_picture = 0; + pcfg->cur_invert = 0; + dbg_tb("%s :ch[%d] TB init\n", __func__, ch); + } + dbg_tb("%s :e\n", __func__); +} + +bool dim_tb_t_try_alloc(struct di_ch_s *pch) +{ + if (pch->tb_busy) + return false; + + pch->tb_busy = true; + pch->tb_owner = pch->ch_id; + dbg_tb("%s :a:ch[%d]:alloc:ok\n", __func__, pch->ch_id); + return true; +} + +void dim_tb_polling_active(struct di_ch_s *pch) +{ + if (pch->en_tb_buf && pch->en_tb) { + if (dim_tb_t_try_alloc(pch)) + pch->en_tb = true; + } +} + +void dim_tb_t_release(struct di_ch_s *pch) +{ + struct di_dev_s *di_devp = get_dim_de_devp(); + + dbg_tb("%s :s\n", __func__); + + if (!di_devp->tb_flag_int) + return; + + if (!pch->en_tb) + return; + + if (pch->en_tb) { + if (pch->ch_id == pch->tb_owner) { + pch->tb_owner = 0xff; + pch->tb_busy = false; + } else { + PR_ERR("%s:%d->%d\n", + __func__, pch->ch_id, pch->tb_owner); + } + pch->en_tb = false; + } + + if (pch->en_tb_buf) { + get_datal()->tb_src_cnt--; + pch->en_tb_buf = false; + } + kfree(dim_tbs[pch->ch_id]); + + dbg_tb("%s :e:r:ch[%d]:cnt[%d]\n", __func__, + pch->ch_id, + get_datal()->tb_src_cnt); +} + +void dim_tb_alloc(struct vframe_tb_s *vf, struct di_ch_s *pch) +{ + unsigned char tb_cnt, tb_nub; + struct di_dev_s *di_devp = get_dim_de_devp(); + + dbg_tb("%s 0:s = %d\n", __func__, pch->ch_id); + + if (!di_devp->tb_flag_int) + return; + + pch->en_tb = false; + pch->en_tb_buf = false; + + if (vf->source_type != + VFRAME_SOURCE_TYPE_OTHERS) + return; + if ((vf->width * vf->height) > (1920 * 1088)) + return; + if (!(vf->type & VIDTYPE_TYPEMASK)) + return; + + tb_nub = cfgg(TB); + if (!tb_nub) + return; + + tb_cnt = get_datal()->tb_src_cnt; + tb_cnt++; + if (tb_cnt > tb_nub) + return; + + if (!dim_tb_t_try_alloc(pch)) + return; + + pch->en_tb = true; + pch->en_tb_buf = true; + get_datal()->tb_src_cnt = tb_cnt; + dbg_tb("%s s = %d\n", __func__, get_datal()->tb_src_cnt); + + dim_tbs[pch->ch_id] = kmalloc(sizeof(*dim_tbs[pch->ch_id]), GFP_KERNEL); + if (!dim_tbs[pch->ch_id]) + return; + //memset(dim_tbs[pch->ch_id], 0, sizeof(struct tb_core_s)); + + dbg_tb("%s :e:ch[%d]:cnt[%d]\n", __func__, + pch->ch_id, + get_datal()->tb_src_cnt); +} + +int dim_tb_task_process(struct vframe_tb_s *vf, u32 data, unsigned int ch) +{ + int tbff_flag = 0; + ulong y5fld[5] = {0}; + int is_top = 0; + int i; + int di_inter_flag = 0; + struct di_dev_s *di_devp = get_dim_de_devp(); + static const char * const detect_type[] = {"NC", "TFF", "BFF", "TBF"}; + struct tb_core_s *pcfg; + struct di_ch_s *pch; + + dbg_tb("%s :step 4 s\n", __func__); + + if (!di_devp->tb_flag_int) + return 1; + if (vf->source_type != + VFRAME_SOURCE_TYPE_OTHERS) + return 1; + if ((vf->width * vf->height) > (1920 * 1088)) + return 1; + + pch = get_chdata(ch); + if (!pch->en_tb) + return 1; + + if (digfunc) + digfunc->stats_init(di_tb_reg[ch], + DIM_TB_DETECT_H, DIM_TB_DETECT_W); + + pcfg = dim_tbs[ch]; + + if (atomic_read(&pcfg->di_tb_sem) != 0) { + if (pcfg->di_tb_quit_flag) + return 1; + + if (pcfg->di_tb_buff_rptr == 0) { + if (atomic_read(&pcfg->di_tb_reset_flag) != 0) + pcfg->di_init = 0; + atomic_set(&pcfg->di_tb_reset_flag, 0); + if (digfunc) + digfunc->fwalg_init(pcfg->di_init, ch); + } + pcfg->di_init = 1; + is_top = (pcfg->di_tb_buff_rptr & 1) ? 0 : 1; + + if (pcfg->di_tb_buff_rptr == 0) { + codec_mm_dma_flush + ((void *)pcfg->di_detect_buf[pcfg->di_tb_buff_rptr + 5].vaddr, + DIM_TB_DETECT_W * DIM_TB_DETECT_H, + DMA_FROM_DEVICE); + codec_mm_dma_flush + ((void *)pcfg->di_detect_buf[pcfg->di_tb_buff_rptr + 4].vaddr, + DIM_TB_DETECT_W * DIM_TB_DETECT_H, + DMA_FROM_DEVICE); + codec_mm_dma_flush + ((void *)pcfg->di_detect_buf[pcfg->di_tb_buff_rptr + 3].vaddr, + DIM_TB_DETECT_W * DIM_TB_DETECT_H, + DMA_FROM_DEVICE); + codec_mm_dma_flush + ((void *)pcfg->di_detect_buf[pcfg->di_tb_buff_rptr + 2].vaddr, + DIM_TB_DETECT_W * DIM_TB_DETECT_H, + DMA_FROM_DEVICE); + codec_mm_dma_flush + ((void *)pcfg->di_detect_buf[pcfg->di_tb_buff_rptr + 1].vaddr, + DIM_TB_DETECT_W * DIM_TB_DETECT_H, + DMA_FROM_DEVICE); + codec_mm_dma_flush + ((void *)pcfg->di_detect_buf[pcfg->di_tb_buff_rptr].vaddr, + DIM_TB_DETECT_W * DIM_TB_DETECT_H, + DMA_FROM_DEVICE); + if (data >= dimp_get(edi_mp_tb_dump) && + dimp_get(edi_mp_tb_dump)) { + pcfg->nr_dump_en = 1; + if (pcfg->cur_invert_a == 1) { + dim_dump_tb(1, ch); + dim_dump_tb(0, ch); + dim_dump_tb(3, ch); + dim_dump_tb(2, ch); + } else { + dim_dump_tb(0, ch); + dim_dump_tb(1, ch); + dim_dump_tb(2, ch); + dim_dump_tb(3, ch); + } + } + } else if (pcfg->di_tb_buff_rptr == 1) { + codec_mm_dma_flush((void *)pcfg->di_detect_buf[6].vaddr, + DIM_TB_DETECT_W * DIM_TB_DETECT_H, + DMA_FROM_DEVICE); + if (pcfg->nr_dump_en) { + if (pcfg->cur_invert_a == 1) { + dim_dump_tb(5, ch); + dim_dump_tb(4, ch); + } else { + dim_dump_tb(4, ch); + dim_dump_tb(5, ch); + } + } + + } else if (pcfg->di_tb_buff_rptr == 2) { + codec_mm_dma_flush((void *)pcfg->di_detect_buf[7].vaddr, + DIM_TB_DETECT_W * DIM_TB_DETECT_H, + DMA_FROM_DEVICE); + if (pcfg->nr_dump_en) { + if (pcfg->cur_invert_a == 1) { + dim_dump_tb(7, ch); + dim_dump_tb(6, ch); + } else { + dim_dump_tb(6, ch); + dim_dump_tb(7, ch); + } + } + + } else if (pcfg->di_tb_buff_rptr == 3) { + codec_mm_dma_flush((void *)pcfg->di_detect_buf[7].vaddr, + DIM_TB_DETECT_W * DIM_TB_DETECT_H, + DMA_FROM_DEVICE); + if (pcfg->nr_dump_en) { + dim_dump_tb(6, ch); + dim_dump_tb(7, ch); + } + } + /* new -> old */ + y5fld[0] = pcfg->di_detect_buf[pcfg->di_tb_buff_rptr + 4].vaddr; + y5fld[1] = pcfg->di_detect_buf[pcfg->di_tb_buff_rptr + 3].vaddr; + y5fld[2] = pcfg->di_detect_buf[pcfg->di_tb_buff_rptr + 2].vaddr; + y5fld[3] = pcfg->di_detect_buf[pcfg->di_tb_buff_rptr + 1].vaddr; + y5fld[4] = pcfg->di_detect_buf[pcfg->di_tb_buff_rptr].vaddr; + + if (digfunc) { + if (IS_ERR_OR_NULL(di_tb_reg[ch])) { + kfree(di_tb_reg[ch]); + PR_ERR("di:err:DI:TB di_tb_reg is NULL!\n"); + return 1; + } + for (i = 0; i < 5; i++) { + if (IS_ERR_OR_NULL((void *)y5fld[i])) { + PR_ERR("di:err:DI:TB y5fld[%d]isNULL\n", + i); + di_inter_flag = 1; + break; + } + } + if (di_inter_flag) { + di_inter_flag = 0; + return 1; + } + digfunc->stats_get(y5fld, di_tb_reg[ch]); + } + is_top = is_top ^ 1; + tbff_flag = -1; + if (digfunc) + tbff_flag = digfunc->fwalg_get(di_tb_reg[ch], is_top, + (pcfg->di_tb_first_frame_type == 3) ? 0 : 1, + pcfg->di_tb_buff_rptr, + atomic_read(&pcfg->di_tb_skip_flag), + (dimp_get(edi_mp_nrds_en)) ? 1 : 0, ch); + dbg_tb("%s TB=%x,=%x,=%x,=%x,=%x,data=%x,ch=%x\n", __func__, + is_top, + pcfg->di_tb_first_frame_type, pcfg->di_tb_buff_rptr, + atomic_read(&pcfg->di_tb_skip_flag), + tbff_flag, data, ch); + if (pcfg->di_tb_buff_rptr == 0) + atomic_set(&pcfg->di_tb_skip_flag, 0); + + if ((tbff_flag < -1) || tbff_flag > 2) { + PR_ERR("di:err:DI:TB get tb detect flag error: %d\n", + tbff_flag); + } + + if ((tbff_flag == -1) && (digfunc)) + tbff_flag = + digfunc->majority_get(ch); + + if (tbff_flag == -1) + tbff_flag = + TB_DETECT_NC; + else if (tbff_flag == 0) + tbff_flag = + TB_DETECT_TFF; + else if (tbff_flag == 1) + tbff_flag = + TB_DETECT_BFF; + else if (tbff_flag == 2) + tbff_flag = + TB_DETECT_TBF; + else + tbff_flag = + TB_DETECT_NC; + + //tbff_flag = + //TB_DETECT_NC;//mark for dis di tb + + pcfg->di_tb_buff_rptr++; + dbg_tb("%s:task %d,%d\n", __func__, + pcfg->di_tb_buff_rptr, pcfg->di_tb_buffer_len); + + if ((pcfg->di_tb_buff_rptr > + pcfg->di_tb_buffer_len - DIM_TB_ALGO_COUNT) && + (atomic_read(&pcfg->dim_detect_status) == di_tb_running)) { + atomic_set(&pcfg->dim_tb_detect_flag, tbff_flag); + dbg_tb("%s:TB get tb detect final flag: %s\n", + __func__, detect_type[tbff_flag]); + atomic_set(&pcfg->dim_detect_status, di_tb_done); + } + atomic_set(&pcfg->di_tb_sem, 0); + } + atomic_set(&pcfg->di_tb_run_flag, 0); + dbg_tb("%s :e\n", __func__); + return 0; +} + +void dim_tb_ext_cmd(struct vframe_s *vf, int data1, unsigned int ch, + unsigned int cmd) +{ + struct tb_task_cmd_s tb_blk_cmd; + struct vframe_tb_s cfg_data; + struct vframe_tb_s *cfg = &cfg_data; + + memset(cfg, 0, sizeof(struct vframe_tb_s)); + if (!IS_ERR_OR_NULL(vf)) { + cfg->height = vf->height; + cfg->width = vf->width; + cfg->source_type = vf->source_type; + cfg->type = vf->type; + } + + dbg_tb("%s :S\n", __func__); + if (cmd == ECMD_TB_REG) + dim_tb_alloc(cfg, get_chdata(ch)); + tb_blk_cmd.cmd = cmd; + tb_blk_cmd.field_count = data1; + tb_blk_cmd.ch = ch; + tb_blk_cmd.in_buf_vf = vf; + tb_task_alloc_block(ch, &tb_blk_cmd); + if (cmd == ECMD_TB_PROC) + dim_ds_detect(cfg, data1, ch); +} +#endif + +#ifdef DIM_TB_DETECT +int RegisterTB_Function(struct TB_DetectFuncPtr *func, const char *ver) +{ + int ret = -1; + + mutex_lock(&di_tb_mutex); + pr_info("DI:TB RegDITB digfunc %p, func: %p, ver:%s\n", digfunc, + func, ver); + if (!digfunc && func) { + digfunc = func; + ret = 0; + } + mutex_unlock(&di_tb_mutex); + + return ret; +} +EXPORT_SYMBOL(RegisterTB_Function); + +int UnRegisterTB_Function(struct TB_DetectFuncPtr *func) +{ + int ret = -1; + + mutex_lock(&di_tb_mutex); + pr_info("DI:TB UnRegDITB: digfunc %p, func: %p\n", digfunc, func); + if (func && func == digfunc) { + digfunc = NULL; + ret = 0; + } + mutex_unlock(&di_tb_mutex); + + return ret; +} +EXPORT_SYMBOL(UnRegisterTB_Function); + +void dim_nr_ds_hw_init(unsigned int width, unsigned int height, unsigned int ch) { unsigned char h_step = 0, v_step = 0; unsigned int width_out, height_out; + const struct reg_acc *op = &di_pre_regset; + struct di_dev_s *di_devp = get_dim_de_devp(); + struct di_ch_s *pch; + + dbg_tb("%s :s\n", __func__); + + if (!di_devp->tb_flag_int) + return; + + pch = get_chdata(ch); + if (!pch->en_tb) + return; width_out = NR_DS_WIDTH; height_out = NR_DS_HEIGHT; @@ -49,152 +1221,55 @@ static void nr_ds_hw_init(unsigned int width, unsigned int height) v_step = height / height_out; /*Switch MIF to NR_DS*/ - DIM_RDMA_WR_BITS(VIUB_MISC_CTRL0, 3, 5, 2); + op->bwr(VIUB_MISC_CTRL0, 3, 5, 2); /* config dsbuf_ocol*/ - DIM_RDMA_WR_BITS(NR_DS_BUF_SIZE_REG, width_out, 0, 8); + op->bwr(NR_DS_BUF_SIZE_REG, width_out, 0, 8); /* config dsbuf_orow*/ - DIM_RDMA_WR_BITS(NR_DS_BUF_SIZE_REG, height_out, 8, 8); + op->bwr(NR_DS_BUF_SIZE_REG, height_out, 8, 8); - DIM_RDMA_WR_BITS(NRDSWR_X, (width_out - 1), 0, 13); - DIM_RDMA_WR_BITS(NRDSWR_Y, (height_out - 1), 0, 13); + op->bwr(NRDSWR_X, (width_out - 1), 0, 13); + op->bwr(NRDSWR_Y, (height_out - 1), 0, 13); - DIM_RDMA_WR_BITS(NRDSWR_CAN_SIZE, (height_out - 1), 0, 13); - DIM_RDMA_WR_BITS(NRDSWR_CAN_SIZE, (width_out - 1), 16, 13); + op->bwr(NRDSWR_CAN_SIZE, (height_out - 1), 0, 13); + op->bwr(NRDSWR_CAN_SIZE, (width_out - 1), 16, 13); /* little endian */ - DIM_RDMA_WR_BITS(NRDSWR_CAN_SIZE, 1, 13, 1); + op->bwr(NRDSWR_CAN_SIZE, 1, 13, 1); - DIM_RDMA_WR_BITS(NR_DS_CTRL, v_step, 16, 6); - DIM_RDMA_WR_BITS(NR_DS_CTRL, h_step, 24, 6); + op->bwr(NR_DS_CTRL, v_step, 16, 6); + op->bwr(NR_DS_CTRL, h_step, 24, 6); + op->bwr(NR_DS_CTRL, (dimp_get(edi_mp_blend_mode) >> 24) & 0xf, 12, 3); + op->bwr(NR_DS_CTRL, (dimp_get(edi_mp_blend_mode) >> 24) & 0xf, 8, 3); + //op->bwr(NR_DS_CTRL, 2, 8, 3); + + op->bwr(NR_DS_BLD_COEF, (dimp_get(edi_mp_blend_mode) >> 16) & 0xff, + 16, 8); + op->bwr(NR_DS_BLD_COEF, (dimp_get(edi_mp_blend_mode) >> 8) & 0xff, + 8, 8); + op->bwr(NR_DS_BLD_COEF, dimp_get(edi_mp_blend_mode) & 0xff, 0, 8); + + op->bwr(NR_DS_CTRL, (dimp_get(edi_mp_blend_mode) >> 28) & 0xf, 0, 1); + dbg_tb("%s:e:done\n", __func__); } -/* - * init nr ds buffer - */ -void dim_nr_ds_buf_init(unsigned int cma_flag, unsigned long mem_start, - struct device *dev, bool tvp_flg) +void dim_dump_tb(unsigned int data, unsigned int ch) { - unsigned int i = 0; - bool ret; - struct dim_mm_s omm; + struct tb_core_s *pcfg; - if (cma_flag == 0) { - nrds_dev.nrds_addr = mem_start; - } else { - #ifdef MARK_HIS - nrds_dev.nrds_pages = dma_alloc_from_contiguous(dev, - NR_DS_PAGE_NUM, - 0, 0); - if (nrds_dev.nrds_pages) - nrds_dev.nrds_addr = page_to_phys(nrds_dev.nrds_pages); - else - PR_ERR("DI: alloc nr ds mem error.\n"); - #else - ret = dim_mm_alloc_api(cma_flag, NR_DS_PAGE_NUM, &omm, tvp_flg); - if (ret) { - nrds_dev.nrds_pages = omm.ppage; - nrds_dev.nrds_addr = omm.addr; + pcfg = dim_tbs[ch]; + + if (pcfg->nr_dump_en) { + if (pcfg->nr_dump_count < NR_DETECT_DUMP_CNT) { + diwrite_to_file(pcfg->di_detect_buf[data].paddr, + NR_DS_WIDTH * NR_DS_HEIGHT + * 1, ch); + dbg_tb("%s:dump NR1 %d %d done\n", __func__, + pcfg->nr_dump_count, data); + pcfg->nr_dump_count++; } else { - PR_ERR("alloc nr ds mem error.\n"); - } - - #endif - } - for (i = 0; i < NR_DS_BUF_NUM; i++) - nrds_dev.buf[i] = nrds_dev.nrds_addr + (NR_DS_BUF_SIZE * i); - nrds_dev.cur_buf_idx = 0; -} - -void dim_nr_ds_buf_uninit(unsigned int cma_flag, struct device *dev) -{ - unsigned int i = 0; - - if (cma_flag == 0) { - nrds_dev.nrds_addr = 0; - } else { - if (nrds_dev.nrds_pages) { - dim_mm_release_api(cma_flag, - nrds_dev.nrds_pages, - NR_DS_PAGE_NUM, - nrds_dev.nrds_addr); - nrds_dev.nrds_addr = 0; - nrds_dev.nrds_pages = NULL; - } else { - PR_INF("no release nr ds mem.\n"); + dbg_tb("%s:dump done\n", __func__); + pcfg->nr_dump_en = 0; } } - for (i = 0; i < NR_DS_BUF_NUM; i++) - nrds_dev.buf[i] = 0; - nrds_dev.cur_buf_idx = 0; -} - -/* - * hw config, alloc canvas - */ -void dim_nr_ds_init(unsigned int width, unsigned int height) -{ - nr_ds_hw_init(width, height); - nrds_dev.field_num = 0; - - if (nrds_dev.canvas_idx != 0) - return; - - if (ops_ext()->cvs_alloc_table("nr_ds", - &nrds_dev.canvas_idx, - 1, CANVAS_MAP_TYPE_1)) { - PR_ERR("%s alloc nrds canvas error.\n", __func__); - return; - } - PR_INF("%s alloc nrds canvas %u.\n", __func__, nrds_dev.canvas_idx); - get_datal()->cvs.nr_ds_idx = nrds_dev.canvas_idx; - get_datal()->cvs.en |= DI_CVS_EN_DS; -} - -/* - * config nr ds mif, switch buffer - */ -void dim_nr_ds_mif_config(void) -{ - unsigned long mem_addr = 0; - - mem_addr = nrds_dev.buf[nrds_dev.cur_buf_idx]; - canvas_config(nrds_dev.canvas_idx, mem_addr, - NR_DS_WIDTH, NR_DS_HEIGHT, 0, 0); - DIM_RDMA_WR_BITS(NRDSWR_CTRL, - nrds_dev.canvas_idx, 0, 8); - dim_nr_ds_hw_ctrl(true); -} - -/* - * enable/disable nr ds mif&hw - */ -void dim_nr_ds_hw_ctrl(bool enable) -{ - /*Switch MIF to NR_DS*/ - DIM_RDMA_WR_BITS(VIUB_MISC_CTRL0, enable ? 3 : 2, 5, 2); - DIM_RDMA_WR_BITS(NRDSWR_CTRL, enable ? 1 : 0, 12, 1); - DIM_RDMA_WR_BITS(NR_DS_CTRL, enable ? 1 : 0, 30, 1); -} - -/* - * process in irq - */ -void dim_nr_ds_irq(void) -{ - dim_nr_ds_hw_ctrl(false); - nrds_dev.field_num++; - nrds_dev.cur_buf_idx++; - if (nrds_dev.cur_buf_idx >= NR_DS_BUF_NUM) - nrds_dev.cur_buf_idx = 0; -} - -/* - * get buf addr&size for dump - */ -void dim_get_nr_ds_buf(unsigned long *addr, unsigned long *size) -{ - *addr = nrds_dev.nrds_addr; - *size = NR_DS_BUF_SIZE; - PR_INF("%s addr 0x%lx, size 0x%lx.\n", __func__, *addr, *size); } /* @@ -215,3 +1290,37 @@ void dim_dump_nrds_reg(unsigned int base_addr) base_addr + (i << 2), i, DIM_RDMA_RD(i)); pr_info("-----nrds reg end-----\n"); } +#endif + +/* + * enable/disable nr ds mif&hw + */ +void dim_nr_ds_hw_ctrl(bool enable) +{ + /*Switch MIF to NR_DS*/ + const struct reg_acc *op = &di_pre_regset; +#ifdef DIM_TB_DETECT + struct di_dev_s *di_devp = get_dim_de_devp(); + + if (!di_devp->tb_flag_int) + enable = 0; +#endif + op->bwr(VIUB_MISC_CTRL0, enable ? 3 : 2, 5, 2); + op->bwr(NRDSWR_CTRL, enable ? 1 : 0, 12, 1); + op->bwr(NR_DS_CTRL, enable ? 1 : 0, 30, 1); + dbg_tb("%s TB %d\n", __func__, enable); +} + +void dim_tb_prob(void) +{ +#ifdef DIM_TB_DETECT + struct di_dev_s *di_devp = get_dim_de_devp(); + + if (IS_IC_SUPPORT(TB)) + di_devp->tb_flag_int = 1; + else + di_devp->tb_flag_int = 0; + PR_INF("%s:end=%d\n", __func__, di_devp->tb_flag_int); +#endif +} + diff --git a/drivers/media/di_multi/nr_downscale.h b/drivers/media/di_multi/nr_downscale.h index 45f340ae5..2d9a9443e 100644 --- a/drivers/media/di_multi/nr_downscale.h +++ b/drivers/media/di_multi/nr_downscale.h @@ -19,6 +19,56 @@ #ifndef _NR_DS_H #define _NR_DS_H +#include "deinterlace.h" + +#ifdef DIM_TB_DETECT +#define DIM_TB_BUFFER_MAX_SIZE 16 +#define DIM_TB_DETECT_W 128 +#define DIM_TB_DETECT_H 96 +#define DIM_TB_ALGO_COUNT 6 + +struct dim_tb_buf_s { + ulong vaddr; + ulong paddr; +}; + +enum dim_tb_status { + di_tb_idle, + di_tb_running, + di_tb_done, +}; + +void write_file(void); + +void dim_tb_status(void); + +struct vframe_tb_s { + enum vframe_source_type_e source_type; + u32 width; + u32 height; + u32 type; + u32 omx_index; +}; + +int dim_tb_buffer_init(unsigned int ch); + +int dim_tb_buffer_uninit(unsigned int ch); + +void dim_tb_reg_init(struct vframe_tb_s *vfm, unsigned int on, unsigned int ch); + +int dim_tb_detect(struct vframe_tb_s *vf, int data1, unsigned int ch); + +void dim_tb_function(struct vframe_tb_s *vf, int data1, unsigned int ch); + +void dim_ds_detect(struct vframe_tb_s *vf, int data1, unsigned int ch); + +int dim_tb_task_process(struct vframe_tb_s *vf, u32 data, unsigned int ch); + +void dim_tb_ext_cmd(struct vframe_s *vf, int data1, unsigned int ch, + unsigned int cmd); +#endif +void dim_dump_tb(unsigned int data, unsigned int ch); + #define NR_DS_WIDTH 128 #define NR_DS_HEIGHT 96 #define NR_DS_BUF_SIZE (96 << 7) @@ -35,10 +85,8 @@ struct nr_ds_s { unsigned long buf[NR_DS_BUF_NUM]; }; -void dim_nr_ds_buf_init(unsigned int cma_flag, unsigned long mem_start, - struct device *dev, bool tvp_flg); -void dim_nr_ds_buf_uninit(unsigned int cma_flag, struct device *dev); -void dim_nr_ds_init(unsigned int width, unsigned int height); +void dim_nr_ds_hw_init(unsigned int width, unsigned int height, + unsigned int ch); void dim_nr_ds_mif_config(void); void dim_nr_ds_hw_ctrl(bool enable); void dim_nr_ds_irq(void); diff --git a/drivers/media/di_multi/set_hdr2_v0_di.c b/drivers/media/di_multi/set_hdr2_v0_di.c index b404a7af6..0c44923ef 100644 --- a/drivers/media/di_multi/set_hdr2_v0_di.c +++ b/drivers/media/di_multi/set_hdr2_v0_di.c @@ -15,12 +15,16 @@ #endif #include "deinterlace.h" +#ifdef DIM_HAVE_HDR #include +#endif /* DIM_HAVE_HDR */ #include "di_data_l.h" #include #include "register.h" #include "di_prc.h" +#ifdef DIM_HAVE_HDR + enum EREG_HDR_IDX { EMATRIXI_COEF00_01, EMATRIXI_COEF02_10, @@ -852,10 +856,13 @@ const struct di_hdr_ops_s di_hdr_op_data = { .get_setting = hdr_get_setting, .set = dim_hdr_set, .get_pre_post = hdr_get_pre_post, + }; +#endif /* DIM_HAVE_HDR */ void dim_hdr_prob(void) { +#ifdef DIM_HAVE_HDR struct di_hdr_s *hdr; unsigned int sizev; @@ -883,30 +890,37 @@ void dim_hdr_prob(void) /*check*/ hdr = (struct di_hdr_s *)get_datal()->hw_hdr; PR_INF("%s:0x%x\n", __func__, hdr->code); +#endif /* DIM_HAVE_HDR */ } void dim_hdr_remove(void) { +#ifdef DIM_HAVE_HDR if (!get_datal()->hw_hdr) return; vfree(get_datal()->hw_hdr); get_datal()->hw_hdr = NULL; PR_INF("%s:end\n", __func__); +#endif /* DIM_HAVE_HDR */ } const struct di_hdr_ops_s *dim_hdr_ops(void) { +#ifdef DIM_HAVE_HDR struct di_hdr_s *hdr; if (!get_datal()->hw_hdr) return NULL; hdr = (struct di_hdr_s *)get_datal()->hw_hdr; return hdr->ops; +#endif /* DIM_HAVE_HDR */ + return NULL; } int dim_dbg_hdr_reg1(struct seq_file *s, void *v, unsigned int index) { +#ifdef DIM_HAVE_HDR int i; unsigned int rbase = 0; unsigned int nub1, off2, nub2, off3, nub3; @@ -948,11 +962,13 @@ int dim_dbg_hdr_reg1(struct seq_file *s, void *v, unsigned int index) rbase + off3 + i, DIM_RDMA_RD(rbase + off3 + i)); } +#endif /* DIM_HAVE_HDR */ return 0; } int dim_dbg_hdr_para_show(struct seq_file *s, void *v) { +#ifdef DIM_HAVE_HDR int i; struct di_hdr_s *pd; char *splt = "---------------------------"; @@ -1003,6 +1019,7 @@ int dim_dbg_hdr_para_show(struct seq_file *s, void *v) for (i = 0; i < MTX_NUM_PARAM; i++) seq_printf(s, "%d:%d\n", i, pd->c.hdr_para.hdr_mtx_param.mtx_in[i]); +#endif /* DIM_HAVE_HDR */ return 0; } diff --git a/drivers/media/di_multi/tb_task.c b/drivers/media/di_multi/tb_task.c new file mode 100644 index 000000000..22b8c8c73 --- /dev/null +++ b/drivers/media/di_multi/tb_task.c @@ -0,0 +1,513 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +#include /*ary add*/ +#include +#include +#include +#include +#include +#include "deinterlace.h" +#include "di_data_l.h" + +#include "di_prc.h" +#include "di_sys.h" +#include "nr_downscale.h" +#include "tb_task.h" +#include "di_vframe.h" +#include "di_dbg.h" + +#ifdef DIM_TB_DETECT +void tb_polling(unsigned int ch, struct tb_task_cmd_s *cmd) +{ + struct di_tb_task *tsk = get_tb_task(); + struct dim_fcmd_s *fcmd; + struct di_ch_s *pch; + struct vframe_tb_s cfg_data; + struct vframe_tb_s *cfg = &cfg_data; + + memset(cfg, 0, sizeof(struct vframe_tb_s)); + pch = get_chdata(cmd->ch); + fcmd = &tsk->fcmd[cmd->ch]; + if (!IS_ERR_OR_NULL(cmd->in_buf_vf)) { + cfg->height = cmd->in_buf_vf->height; + cfg->width = cmd->in_buf_vf->width; + cfg->source_type = cmd->in_buf_vf->source_type; + cfg->type = cmd->in_buf_vf->type; + } + dbg_tb("%s:cmd=0x%x,ch=0x%x,cmd_ch=0x%x\n", __func__, + cmd->cmd, ch, cmd->ch); + if (ch != cmd->ch) + return; + + switch (cmd->cmd) { + case ECMD_TB_REG: + #ifdef DIM_TB_DETECT + //dim_tb_alloc(pch); + dim_tb_reg_init(cfg, 1, cmd->ch); + if (dim_tb_buffer_init(cmd->ch) < 0) { + PR_INF(" alloc tb mem ng.\n"); + dim_tb_t_release(pch); + return; + } + #endif + break; + case ECMD_TB_PROC: + #ifdef DIM_TB_DETECT + dim_tb_function(cfg, cmd->field_count, cmd->ch); + #endif + break; + case ECMD_TB_RELEASE: + #ifdef DIM_TB_DETECT + dim_tb_buffer_uninit(cmd->ch); + dim_tb_t_release(pch); + #endif + break; + case ECMD_TB_ALGORITHM: + #ifdef DIM_TB_DETECT + if (dim_tb_task_process(cfg, + cmd->field_count, + cmd->ch)) + dbg_tb("not support tb_task\n"); + #endif + break; + + default: + dbg_tb("no command\n"); + break; + } + + atomic_dec(&fcmd->doing);//fcmd->doing--; + + tb_task_send_ready(0); +} + +static bool tb_task_get_cmd(unsigned int ch, struct tb_task_cmd_s *cmd) +{ + struct di_tb_task *tsk = get_tb_task(); + struct dim_fcmd_s *fcmd; + struct tb_task_cmd_s val; + unsigned int ret; + + fcmd = &tsk->fcmd[ch]; + if (!fcmd->flg) { +#ifdef PRINT_BASIC + PR_ERR("%s:no fifo\n", __func__); +#endif + return false; + } + + if (kfifo_is_empty(&fcmd->fifo)) + return false; + + if (fcmd->flg_lock & DIM_QUE_LOCK_RD) + ret = kfifo_out_spinlocked(&fcmd->fifo, + &val, + sizeof(struct tb_task_cmd_s), + &fcmd->lock_r); + else + ret = kfifo_out(&fcmd->fifo, &val, sizeof(struct tb_task_cmd_s)); + if (ret != sizeof(struct tb_task_cmd_s)) + return false; + + *cmd = val; + return true; +} + +static void tb_task_polling_cmd(unsigned int ch) +{ + int i; + struct di_tb_task *tsk = get_tb_task(); + struct dim_fcmd_s *fcmd; +// union DI_L_CMD_BLK_BITS cmdbyte; + struct tb_task_cmd_s blk_cmd; + struct di_ch_s *pch; + + pch = get_chdata(ch); + if ((!IS_IC_SUPPORT(TB)) || !pch->en_tb) + return; + + fcmd = &tsk->fcmd[ch]; + + if (!fcmd->flg || kfifo_is_empty(&fcmd->fifo)) + return; + + for (i = 0; i < MAX_KFIFO_L_CMD_NUB; i++) { + if (!tb_task_get_cmd(ch, &blk_cmd)) + break; + + tb_polling(ch, &blk_cmd); + if (blk_cmd.block_mode) + complete(&fcmd->alloc_done); + } +} + +static int tb_task_is_exiting(struct di_tb_task *tsk) +{ + if (tsk->exit) + return 1; + +/* if (afepriv->dvbdev->writers == 1) + * if (time_after_eq(jiffies, fepriv->release_jiffies + + * dvb_shutdown_timeout * HZ)) + * return 1; + */ + return 0; +} + +static int tb_task_should_wakeup(struct di_tb_task *tsk) +{ + if (tsk->wakeup) { + tsk->wakeup = 0; + /*dbg only dbg_tsk("wkg[%d]\n", di_dbg_task_flg);*/ + dbg_once("%s:\n", __func__); + return 1; + } + return tb_task_is_exiting(tsk); +} + +static void tb_task_wakeup(struct di_tb_task *tsk) +{ + tsk->wakeup = 1; + wake_up_interruptible(&tsk->wait_queue); +} + +void tb_task_send_ready(unsigned int id) +{ + struct di_tb_task *tsk = get_tb_task(); + + tb_task_wakeup(tsk); + //dbg_once("%s:id=0x%x\n", __func__, id); +} + +bool tb_task_send_cmd(unsigned int ch, struct tb_task_cmd_s *cmd) +{ + struct di_tb_task *tsk = get_tb_task(); + struct dim_fcmd_s *fcmd; + struct tb_task_cmd_s val; + + fcmd = &tsk->fcmd[ch]; + if (!fcmd->flg) { + //PR_ERR("%s:no fifo\n", __func__); + return false; + } + + //PR_INF("%s:cmd[%d]:\n", __func__, cmd->cmd); + cmd->block_mode = 0; + if (kfifo_is_full(&fcmd->fifo)) { + if (kfifo_out(&fcmd->fifo, &val, sizeof(unsigned int)) + != sizeof(struct tb_task_cmd_s)) { + //PR_ERR("%s:can't out\n", __func__); + return false; + } + + PR_ERR("%s:lost cmd[%d]\n", __func__, val.cmd); + tsk->err_cmd_cnt++; + /*return false;*/ + } + if (fcmd->flg_lock & DIM_QUE_LOCK_WR) + kfifo_in_spinlocked(&fcmd->fifo, cmd, sizeof(struct tb_task_cmd_s), + &fcmd->lock_w); + else + kfifo_in(&fcmd->fifo, cmd, sizeof(struct tb_task_cmd_s)); + + atomic_inc(&fcmd->doing);//fcmd->doing++; + tb_task_wakeup(tsk); + return true; +} + +bool tb_task_send_cmd_block(unsigned int ch, struct tb_task_cmd_s *cmd) +{ + struct di_tb_task *tsk = get_tb_task(); + struct dim_fcmd_s *fcmd; + struct tb_task_cmd_s val; + + fcmd = &tsk->fcmd[ch]; + if (!fcmd->flg) { + //PR_ERR("%s:no fifo\n", __func__); + return false; + } + + cmd->block_mode = 1; + if (kfifo_is_full(&fcmd->fifo)) { + if (kfifo_out(&fcmd->fifo, &val, sizeof(unsigned int)) + != sizeof(struct tb_task_cmd_s)) { + //PR_ERR("%s:can't out\n", __func__); + return false; + } + + PR_ERR("%s:lost cmd[%d]\n", __func__, val.cmd); + tsk->err_cmd_cnt++; + /*return false;*/ + } + if (fcmd->flg_lock & DIM_QUE_LOCK_WR) + kfifo_in_spinlocked(&fcmd->fifo, cmd, sizeof(struct tb_task_cmd_s), + &fcmd->lock_w); + else + kfifo_in(&fcmd->fifo, cmd, sizeof(struct tb_task_cmd_s)); + + atomic_inc(&fcmd->doing);//fcmd->doing++; + tb_task_wakeup(tsk); + return true; +} + +bool tb_task_alloc_block(unsigned int ch, struct tb_task_cmd_s *cmd) +{ + struct dim_fcmd_s *fcmd; + struct di_tb_task *tsk = get_tb_task(); +// unsigned int cnt; + int timeout = 0; + struct di_ch_s *pch; + + pch = get_chdata(ch); + + if ((!IS_IC_SUPPORT(TB)) || !pch->en_tb) + return false; + dbg_tb("%s :s =%d\n", __func__, ch); + + tb_task_send_cmd_block(ch, cmd); + fcmd = &tsk->fcmd[ch]; + + timeout = wait_for_completion_timeout(&fcmd->alloc_done, + msecs_to_jiffies(30)); + if (!timeout) { + PR_WARN("%s:ch[%d]timeout\n", __func__, ch); + return false; + } + return true; +} + +bool tb_task_release_block(unsigned int ch, unsigned int cmd) +{ + struct dim_fcmd_s *fcmd; + struct di_tb_task *tsk = get_tb_task(); + unsigned int cnt; + struct tb_task_cmd_s blk_cmd; + + blk_cmd.cmd = cmd; + tb_task_send_cmd(ch, &blk_cmd); + fcmd = &tsk->fcmd[ch]; + cnt = 0; + while ((atomic_read(&fcmd->doing) > 0) && (cnt < 200)) { + /*wait 2s for finish*/ + usleep_range(10000, 10001); + cnt++; + } + if (atomic_read(&fcmd->doing) > 0) { + PR_ERR("%s:can't finish[%d] fix\n", __func__, + atomic_read(&fcmd->doing)); + /*fix*/ + atomic_set(&fcmd->doing, 0); + return false; + } + return true; +} + +static int tb_thread(void *data) +{ + struct di_tb_task *tsk = data; + bool semheld = false; + int i; + //struct di_ch_s *pch; + + tsk->delay = HZ; + tsk->status = 0; + tsk->wakeup = 0; + + set_freezable(); + + while (1) { + up(&tsk->sem);/* is locked when we enter the thread... */ +mrestart: + wait_event_interruptible_timeout(tsk->wait_queue, + tb_task_should_wakeup(tsk) || + kthread_should_stop() || + freezing(current), + tsk->delay); + + if (kthread_should_stop() || tb_task_is_exiting(tsk)) { + /* got signal or quitting */ + if (!down_interruptible(&tsk->sem)) + semheld = true; + tsk->exit = 1; + break; + } + + if (try_to_freeze()) + goto mrestart; + + if (down_interruptible(&tsk->sem)) + break; + + /**/ + for (i = 0; i < DI_CHANNEL_NUB; i++) { + //pch = get_chdata(i); + tb_task_polling_cmd(i); + //blk_polling(i); + //mtask_polling_sct(pch); + } + } + + tsk->thread = NULL; + if (kthread_should_stop()) + tsk->exit = 1; + else + tsk->exit = 0; + /*mb();*/ + + if (semheld) + up(&tsk->sem); + + tb_task_wakeup(tsk);/*?*/ + return 0; +} + +static void tb_task_alloc(struct di_tb_task *tsk) +{ + int i; + struct dim_fcmd_s *fcmd; + int ret; + + for (i = 0; i < DI_CHANNEL_NUB; i++) { + /*ini*/ + fcmd = &tsk->fcmd[i]; + fcmd->flg_lock = 0; + + if (fcmd->flg_lock & DIM_QUE_LOCK_RD) + spin_lock_init(&fcmd->lock_r); + if (fcmd->flg_lock & DIM_QUE_LOCK_WR) + spin_lock_init(&fcmd->lock_w); + + ret = kfifo_alloc(&fcmd->fifo, + sizeof(struct tb_task_cmd_s) * + MAX_KFIFO_L_CMD_NUB, + GFP_KERNEL); + if (ret < 0) { + fcmd->flg = false; + tsk->err_res++; + PR_ERR("%s:can't get kfifo2,ch[%d]\n", + __func__, i); + break; + } + init_completion(&fcmd->alloc_done); + fcmd->flg = true; + } +} + +static void tb_task_release(struct di_tb_task *tsk) +{ + int i; + struct dim_fcmd_s *fcmd; + + for (i = 0; i < DI_CHANNEL_NUB; i++) { + fcmd = &tsk->fcmd[i]; + + if (fcmd->flg) { + kfifo_free(&fcmd->fifo); + fcmd->flg = false; + } + if (fcmd->flg_lock & DIM_QUE_LOCK_RD) + spin_lock_init(&fcmd->lock_r); + if (fcmd->flg_lock & DIM_QUE_LOCK_WR) + spin_lock_init(&fcmd->lock_w); + } + tsk->err_res = 0; +} +#endif + +void tb_task_stop(void/*struct di_task *tsk*/) +{ +#ifdef DIM_TB_DETECT + struct di_tb_task *tsk = get_tb_task(); + + if (!IS_IC_SUPPORT(TB)) + return; + + /*not use cmd*/ + pr_info("."); + /*--------------------*/ + tb_task_release(tsk); + /*--------------------*/ + + tsk->exit = 1; + /*mb();*/ + + if (!tsk->thread) + return; + + kthread_stop(tsk->thread); + + sema_init(&tsk->sem, 1); + tsk->status = 0; + + /* paranoia check in case a signal arrived */ + if (tsk->thread) + PR_ERR("warning: thread %p won't exit\n", tsk->thread); + PR_INF("%s:finish\n", __func__); +#endif +} + +int tb_task_start(void) +{ +#ifdef DIM_TB_DETECT + int ret; + int flg_err; + struct di_tb_task *tsk = get_tb_task(); + struct task_struct *fe_thread; + //struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 }; + + dbg_tb("%s :s\n", __func__); + + if (!IS_IC_SUPPORT(TB)) + return 0; + pr_info("."); + flg_err = 0; + /*not use cmd*/ + /*--------------------*/ + tb_task_alloc(tsk); + + /*--------------------*/ + sema_init(&tsk->sem, 1); + init_waitqueue_head(&tsk->wait_queue); + + if (tsk->thread) { + if (!tsk->exit) + return 0; + + tb_task_stop(); + } + + if (signal_pending(current)) { + tb_task_release(tsk); + + return -EINTR; + } + if (down_interruptible(&tsk->sem)) { + tb_task_release(tsk); + + return -EINTR; + } + + tsk->status = 0; + tsk->exit = 0; + tsk->thread = NULL; + /*mb();*/ + + fe_thread = kthread_run(tb_thread, tsk, "aml-tb-1"); + if (IS_ERR(fe_thread)) { + ret = PTR_ERR(fe_thread); + PR_ERR(" failed to start kthread (%d)\n", ret); + up(&tsk->sem); + tsk->flg_init = 0; + return ret; + } + + //sched_setscheduler_nocheck(fe_thread, SCHED_FIFO, ¶m); + tsk->flg_init = 1; + tsk->thread = fe_thread; +#endif + return 0; +} + diff --git a/drivers/media/di_multi/tb_task.h b/drivers/media/di_multi/tb_task.h new file mode 100644 index 000000000..f30455068 --- /dev/null +++ b/drivers/media/di_multi/tb_task.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +#ifndef __TB_TASK_H__ +#define __TB_TASK_H__ + +int tb_task_start(void); +void tb_task_stop(void); +bool tb_task_alloc_block(unsigned int ch, struct tb_task_cmd_s *cmd); +void tb_task_send_ready(unsigned int id); +void tb_polling(unsigned int ch, struct tb_task_cmd_s *cmd); + +#endif /*__TB_TASK_H__*/