diff --git a/drivers/drm/meson_sysfs.c b/drivers/drm/meson_sysfs.c index 65d8197ee..4813dd226 100644 --- a/drivers/drm/meson_sysfs.c +++ b/drivers/drm/meson_sysfs.c @@ -3,12 +3,82 @@ * Copyright (c) 2019 Amlogic, Inc. All rights reserved. */ +#include +#include +#include +#include +#include + #include "meson_sysfs.h" #include "meson_crtc.h" +#include "meson_plane.h" +#include "meson_vpu_pipeline.h" static const char vpu_group_name[] = "vpu"; +static const char osd0_group_name[] = "osd0"; +static const char osd1_group_name[] = "osd1"; +static const char osd2_group_name[] = "osd2"; +static const char osd3_group_name[] = "osd3"; +int osd_index[MESON_MAX_OSDS] = {0, 1, 2, 3}; +static const char crtc0_group_name[] = "crtc0"; +static const char crtc1_group_name[] = "crtc1"; +static const char crtc2_group_name[] = "crtc2"; +int crtc_index[MESON_MAX_POSTBLEND] = {0, 1, 2}; +u32 pages; //EXPORT_SYMBOL_GPL(vpu_group_name); +static u8 *am_meson_drm_vmap(ulong addr, u32 size, bool *bflg) +{ + u8 *vaddr = NULL; + ulong phys = addr; + u32 offset = phys & ~PAGE_MASK; + u32 npages = PAGE_ALIGN(size) / PAGE_SIZE; + struct page **pages = NULL; + pgprot_t pgprot; + int i; + + if (!PageHighMem(phys_to_page(phys))) + return phys_to_virt(phys); + + if (offset) + npages++; + + pages = kcalloc(npages, sizeof(struct page *), GFP_KERNEL); + if (!pages) + return NULL; + + for (i = 0; i < npages; i++) { + pages[i] = phys_to_page(phys); + phys += PAGE_SIZE; + } + + pgprot = PAGE_KERNEL; + + vaddr = vmap(pages, npages, VM_MAP, pgprot); + if (!vaddr) { + pr_err("the phy(%lx) vmap fail, size: %d\n", + addr - offset, npages << PAGE_SHIFT); + kfree(pages); + return NULL; + } + + kfree(pages); + + DRM_DEBUG("map high mem pa(%lx) to va(%p), size: %d\n", + addr, vaddr + offset, npages << PAGE_SHIFT); + *bflg = true; + + return vaddr + offset; +} + +static void am_meson_drm_unmap_phyaddr(u8 *vaddr) +{ + void *addr = (void *)(PAGE_MASK & (ulong)vaddr); + + DRM_DEBUG("unmap va(%p)\n", addr); + vunmap(addr); +} + static ssize_t vpu_blank_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -65,10 +135,111 @@ static ssize_t vpu_blank_store(struct device *dev, struct device_attribute *attr return n; } +static ssize_t debug_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int i; + + DRM_INFO("echo rv reg > debug to read the register\n"); + DRM_INFO("echo wv reg val > debug to overwrite the register\n"); + DRM_INFO("echo ow 1 > debug to enable overwrite register\n"); + DRM_INFO("\noverwrote status: %s\n", overwrite_enable ? "on" : "off"); + + if (overwrite_enable) { + for (i = 0; i < reg_num; i++) + DRM_INFO("reg[0x%04x]=0x%08x\n", overwrite_reg[i], + overwrite_val[i]); + } + + return 0; +} + +static void parse_param(char *buf_orig, char **parm) +{ + char *ps, *token; + unsigned int n = 0; + char delim1[3] = " "; + char delim2[2] = "\n"; + + ps = buf_orig; + strcat(delim1, delim2); + while (1) { + token = strsep(&ps, delim1); + if (!token) + break; + if (*token == '\0') + continue; + parm[n++] = token; + } +} + +static ssize_t debug_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t n) +{ + char dst_buf[64]; + long val; + int i; + unsigned int reg_addr, reg_val; + char *bufp, *parm[8] = {NULL}; + int len = strlen(buf); + + if (len > sizeof(dst_buf) - 1) + return -EINVAL; + + memcpy(dst_buf, buf, len); + + dst_buf[len] = '\0'; + bufp = dst_buf; + parse_param(bufp, (char **)&parm); + if (!strcmp(parm[0], "rv")) { + if (kstrtoul(parm[1], 16, &val) < 0) + return -EINVAL; + + reg_addr = val; + DRM_INFO("reg[0x%04x]=0x%08x\n", reg_addr, meson_drm_read_reg(reg_addr)); + } else if (!strcmp(parm[0], "wv")) { + if (kstrtoul(parm[1], 16, &val) < 0) + return -EINVAL; + reg_addr = val; + + if (kstrtoul(parm[2], 16, &val) < 0) + return -EINVAL; + + reg_val = val; + for (i = 0; i < reg_num; i++) { + if (overwrite_reg[i] == reg_addr) { + overwrite_val[i] = reg_val; + return len; + } + } + + if (i == reg_num) { + overwrite_reg[i] = reg_addr; + overwrite_val[i] = reg_val; + reg_num++; + } + } else if (!strcmp(parm[0], "ow")) { + if (parm[1] && !strcmp(parm[1], "1")) { + overwrite_enable = 1; + } else if (parm[1] && !strcmp(parm[1], "0")) { + overwrite_enable = 0; + for (i = 0; i < reg_num; i++) { + overwrite_val[i] = 0; + overwrite_val[i] = 0; + } + reg_num = 0; + } + } + + return n; +} + static DEVICE_ATTR_RW(vpu_blank); +static DEVICE_ATTR_RW(debug); static struct attribute *vpu_attrs[] = { &dev_attr_vpu_blank.attr, + &dev_attr_debug.attr, NULL, }; @@ -77,20 +248,530 @@ static const struct attribute_group vpu_attr_group = { .attrs = vpu_attrs, }; +static ssize_t osd_reverse_show(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, loff_t off, + size_t count) +{ + struct device *dev = kobj_to_dev(kobj); + struct drm_minor *minor = dev_get_drvdata(dev); + struct meson_drm *priv; + struct am_osd_plane *amp; + + if (!minor || !minor->dev) + return -EINVAL; + + priv = minor->dev->dev_private; + amp = priv->osd_planes[*(int *)attr->private]; + + DRM_INFO("echo 1/2/3 > osd_reverse :reverse the osd xy/x/y\n"); + DRM_INFO("echo 0 > osd_reverse to un_reverse the osd plane\n"); + DRM_INFO("osd_reverse: %d\n", amp->osd_reverse); + return 0; +} + +static ssize_t osd_reverse_store(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, loff_t off, + size_t count) +{ + struct device *dev = kobj_to_dev(kobj); + struct drm_minor *minor = dev_get_drvdata(dev); + int idx = *(int *)attr->private; + struct meson_drm *priv; + struct am_osd_plane *amp; + + if (!minor || !minor->dev) + return -EINVAL; + priv = minor->dev->dev_private; + amp = priv->osd_planes[idx]; + + if (sysfs_streq(buf, "0")) { + amp->osd_reverse = 0; + DRM_INFO("disable the osd reverse\n"); + } else if (sysfs_streq(buf, "1")) { + amp->osd_reverse = DRM_MODE_REFLECT_MASK; + DRM_INFO("enable the osd reverse\n"); + } else if (sysfs_streq(buf, "2")) { + amp->osd_reverse = DRM_MODE_REFLECT_X; + DRM_INFO("enable the osd reverse_x\n"); + } else if (sysfs_streq(buf, "3")) { + amp->osd_reverse = DRM_MODE_REFLECT_Y; + DRM_INFO("enable the osd reverse_y\n"); + } else { + return -EINVAL; + } + + return count; +} + +static ssize_t osd_blend_bypass_show(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, loff_t off, + size_t count) +{ + struct device *dev = kobj_to_dev(kobj); + struct drm_minor *minor = dev_get_drvdata(dev); + struct meson_drm *priv; + struct am_osd_plane *amp; + + if (!minor || !minor->dev) + return -EINVAL; + + priv = minor->dev->dev_private; + amp = priv->osd_planes[*(int *)attr->private]; + + DRM_INFO("echo 1/0 > osd_blend_bypass :enable/disable\n"); + DRM_INFO("osd_blend_bypass: %d\n", amp->osd_blend_bypass); + + return 0; +} + +static ssize_t osd_blend_bypass_store(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, loff_t off, + size_t count) +{ + struct device *dev = kobj_to_dev(kobj); + struct drm_minor *minor = dev_get_drvdata(dev); + struct meson_drm *priv; + struct am_osd_plane *amp; + + if (!minor || !minor->dev) + return -EINVAL; + + priv = minor->dev->dev_private; + amp = priv->osd_planes[*(int *)attr->private]; + + if (sysfs_streq(buf, "1")) { + amp->osd_blend_bypass = 1; + DRM_INFO("enable the osd blend bypass\n"); + } else if (sysfs_streq(buf, "0")) { + amp->osd_blend_bypass = 0; + DRM_INFO("disable the osd blend bypass\n"); + } + + return count; +} + +static ssize_t osd_read_port_show(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, loff_t off, + size_t count) +{ + struct device *dev = kobj_to_dev(kobj); + struct drm_minor *minor = dev_get_drvdata(dev); + struct meson_drm *priv; + struct am_osd_plane *amp; + + if (!minor || !minor->dev) + return -EINVAL; + + priv = minor->dev->dev_private; + amp = priv->osd_planes[*(int *)attr->private]; + + DRM_INFO("echo 1 > enable read port setting\n"); + DRM_INFO("echo 0 > disable read port setting\n"); + DRM_INFO("\nstatus：%d\n", (amp->osd_read_ports == 1) ? 1 : 0); + + return 0; +} + +static ssize_t osd_read_port_store(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, loff_t off, + size_t count) +{ + struct device *dev = kobj_to_dev(kobj); + struct drm_minor *minor = dev_get_drvdata(dev); + struct meson_drm *priv; + struct am_osd_plane *amp; + long val; + + if (!minor || !minor->dev) + return -EINVAL; + + priv = minor->dev->dev_private; + amp = priv->osd_planes[*(int *)attr->private]; + + if (kstrtoul(buf, 16, &val) < 0) + return -EINVAL; + + val = val >= 1 ? 1 : 0; + amp->osd_read_ports = val; + + return count; +} + +static ssize_t osd_fbdump_show(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, loff_t off, + size_t count) +{ + struct device *dev = kobj_to_dev(kobj); + struct drm_minor *minor = dev_get_drvdata(dev); + struct meson_drm *priv; + struct am_osd_plane *amp; + bool bflg; + u32 fb_size; + void *vir_addr; + u64 phy_addr; + struct meson_vpu_pipeline *pipeline; + struct meson_vpu_osd_layer_info *info; + struct meson_vpu_pipeline_state *mvps; + u32 num_pages; + + if (!minor || !minor->dev) + return -EINVAL; + + priv = minor->dev->dev_private; + amp = priv->osd_planes[*(int *)attr->private]; + pipeline = priv->pipeline; + mvps = priv_to_pipeline_state(pipeline->obj.state); + info = &mvps->plane_info[*(int *)attr->private]; + + if (!info->enable) { + DRM_INFO("osd is disabled\n"); + return 0; + } + + phy_addr = info->phy_addr; + fb_size = info->fb_size; + bflg = false; + if (pages == 0 && off < fb_size) { + vir_addr = am_meson_drm_vmap(phy_addr, fb_size, &bflg); + amp->bflg = bflg; + amp->vir_addr = vir_addr; + amp->dump_size = fb_size; + } + if (!amp->vir_addr) { + DRM_INFO("vmap failed, vir_addr is null\n"); + return -EINVAL; + } + num_pages = PAGE_ALIGN(amp->dump_size) / PAGE_SIZE; + pages++; + + if (pages <= num_pages && off < amp->dump_size) { + memcpy(buf, amp->vir_addr + off, count); + if (pages == num_pages && amp->bflg) + am_meson_drm_unmap_phyaddr(amp->vir_addr); + return count; + } + + if (off >= amp->dump_size) + pages = 0; + + return 0; +} + +static ssize_t osd_fbdump_store(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, loff_t off, + size_t count) +{ + return count; +} + +static ssize_t crtc_reg_dump_show(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, loff_t off, + size_t count) +{ + struct device *dev = kobj_to_dev(kobj); + struct drm_minor *minor = dev_get_drvdata(dev); + struct meson_drm *priv; + struct am_meson_crtc *amc; + struct meson_vpu_pipeline *mvp1; + struct meson_vpu_block *mvb; + int i; + + if (!minor || !minor->dev) + return -EINVAL; + + priv = minor->dev->dev_private; + amc = priv->crtcs[*(int *)attr->private]; + mvp1 = amc->pipeline; + + for (i = 0; i < MESON_MAX_BLOCKS; i++) { + mvb = mvp1->mvbs[i]; + if (!mvb) + continue; + + DRM_INFO("*************%s*************\n", mvb->name); + if (mvb->ops && mvb->ops->sysfs_dump_register) + mvb->ops->sysfs_dump_register(mvb); + } + + return 0; +} + +static ssize_t crtc_reg_dump_store(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, loff_t off, + size_t count) +{ + return count; +} + +static struct bin_attribute osd0_attr[] = { + { + .attr.name = "osd_reverse", + .attr.mode = 0664, + .private = &osd_index[0], + .read = osd_reverse_show, + .write = osd_reverse_store, + }, + { + .attr.name = "osd_blend_bypass", + .attr.mode = 0664, + .private = &osd_index[0], + .read = osd_blend_bypass_show, + .write = osd_blend_bypass_store, + }, + { + .attr.name = "osd_read_port", + .attr.mode = 0664, + .private = &osd_index[0], + .read = osd_read_port_show, + .write = osd_read_port_store, + }, + { + .attr.name = "fbdump", + .attr.mode = 0664, + .private = &osd_index[0], + .read = osd_fbdump_show, + .write = osd_fbdump_store, + .size = 36864000, + }, +}; + +static struct bin_attribute *osd0_bin_attrs[] = { + &osd0_attr[0], + &osd0_attr[1], + &osd0_attr[2], + &osd0_attr[3], + NULL, +}; + +static struct bin_attribute osd1_attr[] = { + { + .attr.name = "osd_reverse", + .attr.mode = 0664, + .private = &osd_index[1], + .read = osd_reverse_show, + .write = osd_reverse_store, + }, + { + .attr.name = "osd_blend_bypass", + .attr.mode = 0664, + .private = &osd_index[1], + .read = osd_blend_bypass_show, + .write = osd_blend_bypass_store, + }, + { + .attr.name = "osd_read_port", + .attr.mode = 0664, + .private = &osd_index[1], + .read = osd_read_port_show, + .write = osd_read_port_store, + }, + { + .attr.name = "fbdump", + .attr.mode = 0664, + .private = &osd_index[1], + .read = osd_fbdump_show, + .write = osd_fbdump_store, + .size = 36864000, + }, +}; + +static struct bin_attribute *osd1_bin_attrs[] = { + &osd1_attr[0], + &osd1_attr[1], + &osd1_attr[2], + &osd1_attr[3], + NULL, +}; + +static struct bin_attribute osd2_attr[] = { + { + .attr.name = "osd_reverse", + .attr.mode = 0664, + .private = &osd_index[2], + .read = osd_reverse_show, + .write = osd_reverse_store, + }, + { + .attr.name = "osd_blend_bypass", + .attr.mode = 0664, + .private = &osd_index[2], + .read = osd_blend_bypass_show, + .write = osd_blend_bypass_store, + }, + { + .attr.name = "osd_read_port", + .attr.mode = 0664, + .private = &osd_index[2], + .read = osd_read_port_show, + .write = osd_read_port_store, + }, + { + .attr.name = "fbdump", + .attr.mode = 0664, + .private = &osd_index[2], + .read = osd_fbdump_show, + .write = osd_fbdump_store, + .size = 36864000, + }, +}; + +static struct bin_attribute *osd2_bin_attrs[] = { + &osd2_attr[0], + &osd2_attr[1], + &osd2_attr[2], + &osd2_attr[3], + NULL, +}; + +static struct bin_attribute osd3_attr[] = { + { + .attr.name = "osd_reverse", + .attr.mode = 0664, + .private = &osd_index[3], + .read = osd_reverse_show, + .write = osd_reverse_store, + }, + { + .attr.name = "osd_blend_bypass", + .attr.mode = 0664, + .private = &osd_index[3], + .read = osd_blend_bypass_show, + .write = osd_blend_bypass_store, + }, + { + .attr.name = "osd_read_port", + .attr.mode = 0664, + .private = &osd_index[3], + .read = osd_read_port_show, + .write = osd_read_port_store, + }, + { + .attr.name = "fbdump", + .attr.mode = 0664, + .private = &osd_index[3], + .read = osd_fbdump_show, + .write = osd_fbdump_store, + .size = 36864000, + }, +}; + +static struct bin_attribute *osd3_bin_attrs[] = { + &osd3_attr[0], + &osd3_attr[1], + &osd3_attr[2], + &osd3_attr[3], + NULL, +}; + +static const struct attribute_group osd_attr_group[MESON_MAX_OSDS] = { + { + .name = osd0_group_name, + .bin_attrs = osd0_bin_attrs, + }, + { + .name = osd1_group_name, + .bin_attrs = osd1_bin_attrs, + }, + { + .name = osd2_group_name, + .bin_attrs = osd2_bin_attrs, + }, + { + .name = osd3_group_name, + .bin_attrs = osd3_bin_attrs, + }, +}; + +static struct bin_attribute crtc0_attr[] = { + { + .attr.name = "reg_dump", + .attr.mode = 0664, + .private = &crtc_index[0], + .read = crtc_reg_dump_show, + .write = crtc_reg_dump_store, + }, +}; + +static struct bin_attribute *crtc0_bin_attrs[] = { + &crtc0_attr[0], + NULL, +}; + +static struct bin_attribute crtc1_attr[] = { + { + .attr.name = "reg_dump", + .attr.mode = 0664, + .private = &crtc_index[1], + .read = crtc_reg_dump_show, + .write = crtc_reg_dump_store, + }, +}; + +static struct bin_attribute *crtc1_bin_attrs[] = { + &crtc1_attr[0], + NULL, +}; + +static struct bin_attribute crtc2_attr[] = { + { + .attr.name = "reg_dump", + .attr.mode = 0664, + .private = &crtc_index[2], + .read = crtc_reg_dump_show, + .write = crtc_reg_dump_store, + }, +}; + +static struct bin_attribute *crtc2_bin_attrs[] = { + &crtc2_attr[0], + NULL, +}; + +static const struct attribute_group crtc_attr_group[MESON_MAX_POSTBLEND] = { + { + .name = crtc0_group_name, + .bin_attrs = crtc0_bin_attrs, + }, + { + .name = crtc1_group_name, + .bin_attrs = crtc1_bin_attrs, + }, + { + .name = crtc2_group_name, + .bin_attrs = crtc2_bin_attrs, + }, +}; + int meson_drm_sysfs_register(struct drm_device *drm_dev) { - int rc; + int rc, i; + struct meson_drm *priv = drm_dev->dev_private; struct device *dev = drm_dev->primary->kdev; rc = sysfs_create_group(&dev->kobj, &vpu_attr_group); + for (i = 0; i < priv->pipeline->num_osds; i++) + rc = sysfs_create_group(&dev->kobj, &osd_attr_group[i]); + + for (i = 0; i < priv->pipeline->num_postblend; i++) + rc = sysfs_create_group(&dev->kobj, &crtc_attr_group[i]); + return rc; } void meson_drm_sysfs_unregister(struct drm_device *drm_dev) { + int rc, i; + struct meson_drm *priv = drm_dev->dev_private; struct device *dev = drm_dev->primary->kdev; sysfs_remove_group(&dev->kobj, &vpu_attr_group); + + for (i = 0; i < priv->pipeline->num_osds; i++) + rc = sysfs_create_group(&dev->kobj, &osd_attr_group[i]); + + for (i = 0; i < priv->pipeline->num_postblend; i++) + rc = sysfs_create_group(&dev->kobj, &crtc_attr_group[i]); + } diff --git a/drivers/drm/meson_vpu_pipeline.h b/drivers/drm/meson_vpu_pipeline.h index 6d34b41e7..74568c2eb 100644 --- a/drivers/drm/meson_vpu_pipeline.h +++ b/drivers/drm/meson_vpu_pipeline.h @@ -102,6 +102,7 @@ struct meson_vpu_block_ops { struct meson_vpu_block_state *old_state); void (*dump_register)(struct meson_vpu_block *vblk, struct seq_file *seq); + void (*sysfs_dump_register)(struct meson_vpu_block *vblk); void (*init)(struct meson_vpu_block *vblk); void (*fini)(struct meson_vpu_block *vblk); }; diff --git a/drivers/drm/vpu-hw/meson_osd_afbc.c b/drivers/drm/vpu-hw/meson_osd_afbc.c index 1a682a66d..bcdc159af 100644 --- a/drivers/drm/vpu-hw/meson_osd_afbc.c +++ b/drivers/drm/vpu-hw/meson_osd_afbc.c @@ -1482,6 +1482,92 @@ static void osd_afbc_dump_register(struct meson_vpu_block *vblk, value); } +static void sysfs_osd_afbc_dump_register(struct meson_vpu_block *vblk) +{ + int osd_index; + u32 value, reg_addr; + char buff[8]; + struct meson_vpu_afbc *afbc; + struct afbc_osd_reg_s *reg; + + osd_index = vblk->index; + afbc = to_afbc_block(vblk); + reg = afbc->afbc_regs; + + snprintf(buff, 8, "OSD%d", osd_index + 1); + DRM_INFO("afbc error [%d]\n", afbc_err_cnt); + + reg_addr = VPU_MAFBC_SURFACE_CFG; + value = meson_drm_read_reg(VPU_MAFBC_SURFACE_CFG); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, "VPU_MAFBC_SURFACE_CFG", + reg_addr, value); + + reg_addr = reg->vpu_mafbc_header_buf_addr_low_s; + value = meson_drm_read_reg(reg->vpu_mafbc_header_buf_addr_low_s); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, "AFBC_HEADER_BUF_ADDR_LOW", + reg_addr, value); + + reg_addr = reg->vpu_mafbc_header_buf_addr_high_s; + value = meson_drm_read_reg(reg->vpu_mafbc_header_buf_addr_high_s); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "AFBC_HEADER_BUF_ADDR_HIGH", reg_addr, value); + + reg_addr = reg->vpu_mafbc_format_specifier_s; + value = meson_drm_read_reg(reg->vpu_mafbc_format_specifier_s); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "AFBC_FORMAT_SPECIFIER", reg_addr, value); + + reg_addr = reg->vpu_mafbc_buffer_width_s; + value = meson_drm_read_reg(reg->vpu_mafbc_buffer_width_s); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, "AFBC_BUFFER_WIDTH", + reg_addr, value); + + reg_addr = reg->vpu_mafbc_buffer_height_s; + value = meson_drm_read_reg(reg->vpu_mafbc_buffer_height_s); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, "AFBC_BUFFER_HEIGHT", + reg_addr, value); + + reg_addr = reg->vpu_mafbc_bounding_box_x_start_s; + value = meson_drm_read_reg(reg->vpu_mafbc_bounding_box_x_start_s); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "AFBC_BOUNDING_BOX_X_START", reg_addr, value); + + reg_addr = reg->vpu_mafbc_bounding_box_x_end_s; + value = meson_drm_read_reg(reg->vpu_mafbc_bounding_box_x_end_s); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, "AFBC_BOUNDING_BOX_X_END", + reg_addr, value); + + reg_addr = reg->vpu_mafbc_bounding_box_y_start_s; + value = meson_drm_read_reg(reg->vpu_mafbc_bounding_box_y_start_s); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "AFBC_BOUNDING_BOX_Y_START", reg_addr, value); + + reg_addr = reg->vpu_mafbc_bounding_box_y_end_s; + value = meson_drm_read_reg(reg->vpu_mafbc_bounding_box_y_end_s); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "AFBC_BOUNDING_BOX_Y_END", reg_addr, value); + + reg_addr = reg->vpu_mafbc_output_buf_addr_low_s; + value = meson_drm_read_reg(reg->vpu_mafbc_output_buf_addr_low_s); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "AFBC_OUTPUT_BUF_ADDR_LOW", reg_addr, value); + + reg_addr = reg->vpu_mafbc_output_buf_addr_high_s; + value = meson_drm_read_reg(reg->vpu_mafbc_output_buf_addr_high_s); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "AFBC_OUTPUT_BUF_ADDR_HIGH", reg_addr, value); + + reg_addr = reg->vpu_mafbc_output_buf_stride_s; + value = meson_drm_read_reg(reg->vpu_mafbc_output_buf_stride_s); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "AFBC_OUTPUT_BUF_STRIDE", reg_addr, value); + + reg_addr = reg->vpu_mafbc_prefetch_cfg_s; + value = meson_drm_read_reg(reg->vpu_mafbc_prefetch_cfg_s); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, "AFBC_PREFETCH_CFG", + reg_addr, value); +} + static void osd_afbc_hw_enable(struct meson_vpu_block *vblk, struct meson_vpu_block_state *state) { @@ -1627,6 +1713,7 @@ struct meson_vpu_block_ops afbc_ops = { .enable = osd_afbc_hw_enable, .disable = osd_afbc_hw_disable, .dump_register = osd_afbc_dump_register, + .sysfs_dump_register = sysfs_osd_afbc_dump_register, .init = osd_afbc_hw_init, }; @@ -1637,6 +1724,7 @@ struct meson_vpu_block_ops t7_afbc_ops = { .enable = osd_afbc_hw_enable, .disable = t7_osd_afbc_hw_disable, .dump_register = osd_afbc_dump_register, + .sysfs_dump_register = sysfs_osd_afbc_dump_register, .init = t7_osd_afbc_hw_init, }; @@ -1646,6 +1734,7 @@ struct meson_vpu_block_ops t3_afbc_ops = { .enable = osd_afbc_hw_enable, .disable = t7_osd_afbc_hw_disable, .dump_register = osd_afbc_dump_register, + .sysfs_dump_register = sysfs_osd_afbc_dump_register, .init = t3_osd_afbc_hw_init, }; @@ -1655,6 +1744,7 @@ struct meson_vpu_block_ops s5_afbc_ops = { .enable = osd_afbc_hw_enable, .disable = t7_osd_afbc_hw_disable, .dump_register = osd_afbc_dump_register, + .sysfs_dump_register = sysfs_osd_afbc_dump_register, .init = s5_osd_afbc_hw_init, }; @@ -1664,6 +1754,7 @@ struct meson_vpu_block_ops t3x_afbc_ops = { .enable = osd_afbc_hw_enable, .disable = t7_osd_afbc_hw_disable, .dump_register = osd_afbc_dump_register, + .sysfs_dump_register = sysfs_osd_afbc_dump_register, .init = t3x_osd_afbc_hw_init, }; #endif diff --git a/drivers/drm/vpu-hw/meson_osd_proc.c b/drivers/drm/vpu-hw/meson_osd_proc.c index d85e1948e..9e16bd0ab 100644 --- a/drivers/drm/vpu-hw/meson_osd_proc.c +++ b/drivers/drm/vpu-hw/meson_osd_proc.c @@ -196,6 +196,131 @@ static void slice2ppc_dump_register(struct meson_vpu_block *vblk, seq_printf(seq, "%-35s\t\t0x%08X\n", "OSD_SYS_2SLICE_HWIN_CUT:", value); } +static void sysfs_slice2ppc_dump_register(struct meson_vpu_block *vblk) +{ + u32 value, reg_addr; + struct meson_vpu_slice2ppc *slice2ppc; + struct slice2ppc_reg_s *reg; + + slice2ppc = to_slice2ppc_block(vblk); + reg = slice2ppc->reg; + + reg_addr = reg->osd1_proc_in_size; + value = meson_drm_read_reg(reg->osd1_proc_in_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD1_PROC_IN_SIZE", + reg_addr, value); + + reg_addr = reg->osd2_proc_in_size; + value = meson_drm_read_reg(reg->osd2_proc_in_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD2_PROC_IN_SIZE", + reg_addr, value); + + reg_addr = reg->osd3_proc_in_size; + value = meson_drm_read_reg(reg->osd3_proc_in_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD3_PROC_IN_SIZE", + reg_addr, value); + + reg_addr = reg->osd4_proc_in_size; + value = meson_drm_read_reg(reg->osd4_proc_in_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD4_PROC_IN_SIZE", + reg_addr, value); + + reg_addr = reg->osd1_proc_out_size; + value = meson_drm_read_reg(reg->osd1_proc_out_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD1_PROC_OUT_SIZE", + reg_addr, value); + + reg_addr = reg->osd2_proc_out_size; + value = meson_drm_read_reg(reg->osd2_proc_out_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD2_PROC_OUT_SIZE", + reg_addr, value); + + reg_addr = reg->osd3_proc_out_size; + value = meson_drm_read_reg(reg->osd3_proc_out_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD3_PROC_OUT_SIZE", + reg_addr, value); + + reg_addr = reg->osd4_proc_out_size; + value = meson_drm_read_reg(reg->osd4_proc_out_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD4_PROC_OUT_SIZE", + reg_addr, value); + + reg_addr = reg->osd_blend_dout0_size; + value = meson_drm_read_reg(reg->osd_blend_dout0_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_BLEND_DOUT0_SIZE", + reg_addr, value); + + reg_addr = reg->osd_blend_dout1_size; + value = meson_drm_read_reg(reg->osd_blend_dout1_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_BLEND_DOUT1_SIZE", + reg_addr, value); + + reg_addr = reg->osd_proc_1mux3_sel; + value = meson_drm_read_reg(reg->osd_proc_1mux3_sel); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_PROC_1MUX3_SEL", + reg_addr, value); + + reg_addr = reg->osd_2slice2ppc_in_size; + value = meson_drm_read_reg(reg->osd_2slice2ppc_in_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_2SLICE2PPC_IN_SIZE", + reg_addr, value); + + reg_addr = reg->osd_2slice2ppc_mode; + value = meson_drm_read_reg(reg->osd_2slice2ppc_mode); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_2SLICE2PPC_MODE", + reg_addr, value); + + reg_addr = reg->osd_pi_bypass_en; + value = meson_drm_read_reg(reg->osd_pi_bypass_en); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_PI_BYPASS_EN", + reg_addr, value); + + reg_addr = reg->osd_sys_5mux4_sel; + value = meson_drm_read_reg(reg->osd_sys_5mux4_sel); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_SYS_5MUX4_SEL", + reg_addr, value); + + reg_addr = reg->osd_sys_hwin0_cut; + value = meson_drm_read_reg(reg->osd_sys_hwin0_cut); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_SYS_HWIN0_CUT", + reg_addr, value); + + reg_addr = reg->osd_sys_hwin1_cut; + value = meson_drm_read_reg(reg->osd_sys_hwin1_cut); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_SYS_HWIN1_CUT", + reg_addr, value); + + reg_addr = reg->osd_sys_pad_ctrl; + value = meson_drm_read_reg(reg->osd_sys_pad_ctrl); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_SYS_PAD_CTRL", + reg_addr, value); + + reg_addr = reg->osd_sys_pad_dummy_data0; + value = meson_drm_read_reg(reg->osd_sys_pad_dummy_data0); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_SYS_PAD_DUMMY_DATA0", + reg_addr, value); + + reg_addr = reg->osd_sys_pad_dummy_data1; + value = meson_drm_read_reg(reg->osd_sys_pad_dummy_data1); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_SYS_PAD_DUMMY_DATA1", + reg_addr, value); + + reg_addr = reg->osd_sys_pad_h_size; + value = meson_drm_read_reg(reg->osd_sys_pad_h_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_SYS_PAD_H_SIZE", + reg_addr, value); + + reg_addr = reg->osd_sys_pad_v_size; + value = meson_drm_read_reg(reg->osd_sys_pad_v_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_SYS_PAD_V_SIZE", + reg_addr, value); + + reg_addr = reg->osd_sys_2slice_hwin_cut; + value = meson_drm_read_reg(reg->osd_sys_2slice_hwin_cut); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD_SYS_2SLICE_HWIN_CUT", + reg_addr, value); +} + static void slice2ppc_hw_init(struct meson_vpu_block *vblk) { struct meson_vpu_slice2ppc *slice2ppc = to_slice2ppc_block(vblk); @@ -213,6 +338,7 @@ struct meson_vpu_block_ops slice2ppc_ops = { .enable = slice2ppc_hw_enable, .disable = slice2ppc_hw_disable, .dump_register = slice2ppc_dump_register, + .sysfs_dump_register = sysfs_slice2ppc_dump_register, .init = slice2ppc_hw_init, .fini = slice2ppc_hw_fini, }; diff --git a/drivers/drm/vpu-hw/meson_osd_scaler.c b/drivers/drm/vpu-hw/meson_osd_scaler.c index 8154dfb34..18df4e714 100644 --- a/drivers/drm/vpu-hw/meson_osd_scaler.c +++ b/drivers/drm/vpu-hw/meson_osd_scaler.c @@ -1084,6 +1084,76 @@ static void scaler_dump_register(struct meson_vpu_block *vblk, seq_printf(seq, "%s_%-35s\t0x%08X\n", buff, "SCO_V_START_END:", value); } +static void sysfs_scaler_dump_register(struct meson_vpu_block *vblk) +{ + int osd_index; + u32 value, reg_addr; + char buff[8]; + struct meson_vpu_scaler *scaler; + struct osd_scaler_reg_s *reg; + + osd_index = vblk->index; + scaler = to_scaler_block(vblk); + reg = scaler->reg; + + snprintf(buff, 8, "OSD%d", osd_index + 1); + + reg_addr = reg->vpp_osd_vsc_phase_step; + value = meson_drm_read_reg(reg->vpp_osd_vsc_phase_step); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "VSC_PHASE_STEP", reg_addr, value); + + reg_addr = reg->vpp_osd_vsc_ini_phase; + value = meson_drm_read_reg(reg->vpp_osd_vsc_ini_phase); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "VSC_INIT_PHASE", reg_addr, value); + + reg_addr = reg->vpp_osd_vsc_ctrl0; + value = meson_drm_read_reg(reg->vpp_osd_vsc_ctrl0); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "VSC_CTRL0", reg_addr, value); + + reg_addr = reg->vpp_osd_hsc_phase_step; + value = meson_drm_read_reg(reg->vpp_osd_hsc_phase_step); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "HSC_PHASE_STEP", reg_addr, value); + + reg_addr = reg->vpp_osd_hsc_ini_phase; + value = meson_drm_read_reg(reg->vpp_osd_hsc_ini_phase); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "HSC_INIT_PHASE", reg_addr, value); + + reg_addr = reg->vpp_osd_hsc_ctrl0; + value = meson_drm_read_reg(reg->vpp_osd_hsc_ctrl0); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "HSC_CTRL0", reg_addr, value); + + reg_addr = reg->vpp_osd_sc_dummy_data; + value = meson_drm_read_reg(reg->vpp_osd_sc_dummy_data); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "SC_DUMMY_DATA", reg_addr, value); + + reg_addr = reg->vpp_osd_sc_ctrl0; + value = meson_drm_read_reg(reg->vpp_osd_sc_ctrl0); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "SC_CTRL0", reg_addr, value); + + reg_addr = reg->vpp_osd_sci_wh_m1; + value = meson_drm_read_reg(reg->vpp_osd_sci_wh_m1); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "SCI_WH_M1", reg_addr, value); + + reg_addr = reg->vpp_osd_sco_h_start_end; + value = meson_drm_read_reg(reg->vpp_osd_sco_h_start_end); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "SCO_H_START_END", reg_addr, value); + + reg_addr = reg->vpp_osd_sco_v_start_end; + value = meson_drm_read_reg(reg->vpp_osd_sco_v_start_end); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "SCO_V_START_END", reg_addr, value); +} + static void scaler_hw_init(struct meson_vpu_block *vblk) { struct meson_vpu_scaler *scaler = to_scaler_block(vblk); @@ -1121,6 +1191,7 @@ struct meson_vpu_block_ops scaler_ops = { .enable = scaler_hw_enable, .disable = scaler_hw_disable, .dump_register = scaler_dump_register, + .sysfs_dump_register = sysfs_scaler_dump_register, .init = scaler_hw_init, }; @@ -1131,6 +1202,7 @@ struct meson_vpu_block_ops s5_scaler_ops = { .enable = scaler_hw_enable, .disable = scaler_hw_disable, .dump_register = scaler_dump_register, + .sysfs_dump_register = sysfs_scaler_dump_register, .init = s5_scaler_hw_init, }; #endif diff --git a/drivers/drm/vpu-hw/meson_vpu_osd_mif.c b/drivers/drm/vpu-hw/meson_vpu_osd_mif.c index 7f22ae961..d765134b3 100644 --- a/drivers/drm/vpu-hw/meson_vpu_osd_mif.c +++ b/drivers/drm/vpu-hw/meson_vpu_osd_mif.c @@ -1522,6 +1522,86 @@ static void osd_dump_register(struct meson_vpu_block *vblk, seq_printf(seq, "%s_%-35s\t0x%08X\n", buff, "DIMM_CTRL:", value); } +static void sysfs_osd_dump_register(struct meson_vpu_block *vblk) +{ + int osd_index; + u32 value, reg_addr; + char buff[8]; + struct meson_vpu_osd *osd; + struct osd_mif_reg_s *reg; + + osd_index = vblk->index; + osd = to_osd_block(vblk); + reg = osd->reg; + + snprintf(buff, 8, "OSD%d", osd_index + 1); + + reg_addr = reg->viu_osd_fifo_ctrl_stat; + value = meson_drm_read_reg(reg->viu_osd_fifo_ctrl_stat); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "FIFO_CTRL_STAT", reg_addr, value); + + reg_addr = reg->viu_osd_ctrl_stat; + value = meson_drm_read_reg(reg->viu_osd_ctrl_stat); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "CTRL_STAT", reg_addr, value); + + reg_addr = reg->viu_osd_ctrl_stat2; + value = meson_drm_read_reg(reg->viu_osd_ctrl_stat2); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "CTRL_STAT2", reg_addr, value); + + reg_addr = reg->viu_osd_blk0_cfg_w0; + value = meson_drm_read_reg(reg->viu_osd_blk0_cfg_w0); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "BLK0_CFG_W0", reg_addr, value); + + reg_addr = reg->viu_osd_blk0_cfg_w1; + value = meson_drm_read_reg(reg->viu_osd_blk0_cfg_w1); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "BLK0_CFG_W1", reg_addr, value); + + reg_addr = reg->viu_osd_blk0_cfg_w2; + value = meson_drm_read_reg(reg->viu_osd_blk0_cfg_w2); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "BLK0_CFG_W2", reg_addr, value); + + reg_addr = reg->viu_osd_blk0_cfg_w3; + value = meson_drm_read_reg(reg->viu_osd_blk0_cfg_w3); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "BLK0_CFG_W3", reg_addr, value); + + reg_addr = reg->viu_osd_blk0_cfg_w4; + value = meson_drm_read_reg(reg->viu_osd_blk0_cfg_w4); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "BLK0_CFG_W4", reg_addr, value); + + reg_addr = reg->viu_osd_blk1_cfg_w4; + value = meson_drm_read_reg(reg->viu_osd_blk1_cfg_w4); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "BLK1_CFG_W4", reg_addr, value); + + reg_addr = reg->viu_osd_blk2_cfg_w4; + value = meson_drm_read_reg(reg->viu_osd_blk2_cfg_w4); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "BLK2_CFG_W4", reg_addr, value); + + reg_addr = reg->viu_osd_prot_ctrl; + value = meson_drm_read_reg(reg->viu_osd_prot_ctrl); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "PROT_CTRL", reg_addr, value); + + reg_addr = reg->viu_osd_mali_unpack_ctrl; + value = meson_drm_read_reg(reg->viu_osd_mali_unpack_ctrl); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "MALI_UNPACK_CTRL", reg_addr, value); + + reg_addr = reg->viu_osd_dimm_ctrl; + value = meson_drm_read_reg(reg->viu_osd_dimm_ctrl); + DRM_INFO("%s_%-35s addr: 0x%08X\tvalue: 0x%08X\n", buff, + "DIMM_CTRL", reg_addr, value); +} + #ifndef CONFIG_AMLOGIC_ZAPPER_CUT #ifdef CONFIG_AMLOGIC_MEDIA_SECURITY static void osd_secure_cb(u32 arg) @@ -1719,6 +1799,7 @@ struct meson_vpu_block_ops osd_ops = { .enable = osd_hw_enable, .disable = osd_hw_disable, .dump_register = osd_dump_register, + .sysfs_dump_register = sysfs_osd_dump_register, .init = osd_hw_init, .fini = osd_hw_fini, }; @@ -1730,6 +1811,7 @@ struct meson_vpu_block_ops g12b_osd_ops = { .enable = osd_hw_enable, .disable = osd_hw_disable, .dump_register = osd_dump_register, + .sysfs_dump_register = sysfs_osd_dump_register, .init = g12b_osd_hw_init, .fini = osd_hw_fini, }; @@ -1740,6 +1822,7 @@ struct meson_vpu_block_ops t7_osd_ops = { .enable = osd_hw_enable, .disable = osd_hw_disable, .dump_register = osd_dump_register, + .sysfs_dump_register = sysfs_osd_dump_register, .init = t7_osd_hw_init, .fini = osd_hw_fini, }; @@ -1750,6 +1833,7 @@ struct meson_vpu_block_ops s5_osd_ops = { .enable = osd_hw_enable, .disable = osd_hw_disable, .dump_register = osd_dump_register, + .sysfs_dump_register = sysfs_osd_dump_register, .init = s5_osd_hw_init, .fini = osd_hw_fini, }; diff --git a/drivers/drm/vpu-hw/meson_vpu_osdblend.c b/drivers/drm/vpu-hw/meson_vpu_osdblend.c index 4b92449bd..21d6b5eab 100644 --- a/drivers/drm/vpu-hw/meson_vpu_osdblend.c +++ b/drivers/drm/vpu-hw/meson_vpu_osdblend.c @@ -1155,6 +1155,86 @@ static void osdblend_dump_register(struct meson_vpu_block *vblk, seq_printf(seq, "%-35s\t\t0x%08X\n", "VIU_OSD_BLEND_CTRL1:", value); } +static void sysfs_osdblend_dump_register(struct meson_vpu_block *vblk) +{ + u32 value, reg_addr; + struct meson_vpu_osdblend *osdblend; + struct osdblend_reg_s *reg; + + osdblend = to_osdblend_block(vblk); + reg = osdblend->reg; + + reg_addr = reg->viu_osd_blend_ctrl; + value = meson_drm_read_reg(reg->viu_osd_blend_ctrl); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VIU_OSD_BLEND_CTRL", + reg_addr, value); + + reg_addr = reg->viu_osd_blend_din0_scope_h; + value = meson_drm_read_reg(reg->viu_osd_blend_din0_scope_h); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VIU_OSD_BLEND_DIN0_SCOPE_H", + reg_addr, value); + + reg_addr = reg->viu_osd_blend_din0_scope_v; + value = meson_drm_read_reg(reg->viu_osd_blend_din0_scope_v); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VIU_OSD_BLEND_DIN0_SCOPE_V", + reg_addr, value); + + reg_addr = reg->viu_osd_blend_din1_scope_h; + value = meson_drm_read_reg(reg->viu_osd_blend_din1_scope_h); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VIU_OSD_BLEND_DIN1_SCOPE_H", + reg_addr, value); + + reg_addr = reg->viu_osd_blend_din1_scope_v; + value = meson_drm_read_reg(reg->viu_osd_blend_din1_scope_v); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VIU_OSD_BLEND_DIN1_SCOPE_V", + reg_addr, value); + + reg_addr = reg->viu_osd_blend_din2_scope_h; + value = meson_drm_read_reg(reg->viu_osd_blend_din2_scope_h); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VIU_OSD_BLEND_DIN2_SCOPE_H", + reg_addr, value); + + reg_addr = reg->viu_osd_blend_din2_scope_v; + value = meson_drm_read_reg(reg->viu_osd_blend_din2_scope_v); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VIU_OSD_BLEND_DIN2_SCOPE_V", + reg_addr, value); + + reg_addr = reg->viu_osd_blend_din3_scope_h; + value = meson_drm_read_reg(reg->viu_osd_blend_din3_scope_h); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VIU_OSD_BLEND_DIN3_SCOPE_H", + reg_addr, value); + + reg_addr = reg->viu_osd_blend_din3_scope_v; + value = meson_drm_read_reg(reg->viu_osd_blend_din3_scope_v); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VIU_OSD_BLEND_DIN3_SCOPE_V", + reg_addr, value); + + reg_addr = reg->viu_osd_blend_dummy_data0; + value = meson_drm_read_reg(reg->viu_osd_blend_dummy_data0); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VIU_OSD_BLEND_DUMMY_DATA0", + reg_addr, value); + + reg_addr = reg->viu_osd_blend_dummy_alpha; + value = meson_drm_read_reg(reg->viu_osd_blend_dummy_alpha); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VIU_OSD_BLEND_DUMMY_ALPHA", + reg_addr, value); + + reg_addr = reg->viu_osd_blend0_size; + value = meson_drm_read_reg(reg->viu_osd_blend0_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VIU_OSD_BLEND_BLEND0_SIZE", + reg_addr, value); + + reg_addr = reg->viu_osd_blend1_size; + value = meson_drm_read_reg(reg->viu_osd_blend1_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VIU_OSD_BLEND_BLEND1_SIZE", + reg_addr, value); + + reg_addr = reg->viu_osd_blend_ctrl1; + value = meson_drm_read_reg(reg->viu_osd_blend_ctrl1); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VIU_OSD_BLEND_CTRL1", + reg_addr, value); +} + static void osdblend_hw_init(struct meson_vpu_block *vblk) { struct meson_vpu_osdblend *osdblend = to_osdblend_block(vblk); @@ -1208,6 +1288,7 @@ struct meson_vpu_block_ops osdblend_ops = { .enable = osdblend_hw_enable, .disable = osdblend_hw_disable, .dump_register = osdblend_dump_register, + .sysfs_dump_register = sysfs_osdblend_dump_register, .init = osdblend_hw_init, }; @@ -1218,6 +1299,7 @@ struct meson_vpu_block_ops txhd2_osdblend_ops = { .enable = osdblend_hw_enable, .disable = osdblend_hw_disable, .dump_register = osdblend_dump_register, + .sysfs_dump_register = sysfs_osdblend_dump_register, .init = txhd2_osdblend_hw_init, }; @@ -1227,6 +1309,7 @@ struct meson_vpu_block_ops s5_osdblend_ops = { .enable = osdblend_hw_enable, .disable = osdblend_hw_disable, .dump_register = osdblend_dump_register, + .sysfs_dump_register = sysfs_osdblend_dump_register, .init = s5_osdblend_hw_init, }; @@ -1236,6 +1319,7 @@ struct meson_vpu_block_ops t3x_osdblend_ops = { .enable = osdblend_hw_enable, .disable = osdblend_hw_disable, .dump_register = osdblend_dump_register, + .sysfs_dump_register = sysfs_osdblend_dump_register, .init = s5_osdblend_hw_init, }; #endif diff --git a/drivers/drm/vpu-hw/meson_vpu_postblend.c b/drivers/drm/vpu-hw/meson_vpu_postblend.c index c31e23af6..d51ac093b 100644 --- a/drivers/drm/vpu-hw/meson_vpu_postblend.c +++ b/drivers/drm/vpu-hw/meson_vpu_postblend.c @@ -769,7 +769,219 @@ static void postblend_dump_register(struct meson_vpu_block *vblk, seq_printf(seq, "%-35s\t\t0x%08X\n", "VPP_OSD2_BLD_V_SCOPE:", value); } +static void sysfs_postblend_dump_register(struct meson_vpu_block *vblk) +{ + u32 value, reg_addr; + struct meson_vpu_postblend *postblend; + struct postblend_reg_s *reg; + + postblend = to_postblend_block(vblk); + reg = postblend->reg; + + reg_addr = reg->osd1_blend_src_ctrl; + value = meson_drm_read_reg(reg->osd1_blend_src_ctrl); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD1_BLEND_SRC_CTRL", + reg_addr, value); + + reg_addr = reg->osd2_blend_src_ctrl; + value = meson_drm_read_reg(reg->osd2_blend_src_ctrl); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD2_BLEND_SRC_CTRL", + reg_addr, value); + + reg_addr = reg->vd1_blend_src_ctrl; + value = meson_drm_read_reg(reg->vd1_blend_src_ctrl); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VD1_BLEND_SRC_CTRL", + reg_addr, value); + + reg_addr = reg->vd2_blend_src_ctrl; + value = meson_drm_read_reg(reg->vd2_blend_src_ctrl); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VD2_BLEND_SRC_CTRL", + reg_addr, value); + + reg_addr = reg->vpp_osd1_in_size; + value = meson_drm_read_reg(reg->vpp_osd1_in_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP_OSD1_IN_SIZE:", + reg_addr, value); + + reg_addr = reg->vpp_osd1_bld_h_scope; + value = meson_drm_read_reg(reg->vpp_osd1_bld_h_scope); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP_OSD1_BLD_H_SCOPE", + reg_addr, value); + + reg_addr = reg->vpp_osd1_bld_v_scope; + value = meson_drm_read_reg(reg->vpp_osd1_bld_v_scope); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP_OSD1_BLD_V_SCOPE", + reg_addr, value); + + reg_addr = reg->vpp_osd2_bld_h_scope; + value = meson_drm_read_reg(reg->vpp_osd2_bld_h_scope); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP_OSD2_BLD_H_SCOPE", + reg_addr, value); + + reg_addr = reg->vpp_osd2_bld_v_scope; + value = meson_drm_read_reg(reg->vpp_osd2_bld_v_scope); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP_OSD2_BLD_V_SCOPE", + reg_addr, value); +} + #ifndef CONFIG_AMLOGIC_ZAPPER_CUT +static void t7_sysfs_postblend_dump_register(struct meson_vpu_block *vblk) +{ + u32 value, reg_addr; + struct meson_vpu_postblend *postblend; + struct postblend_reg_s *reg; + + postblend = to_postblend_block(vblk); + if (vblk->index == 0) { + reg = postblend->reg; + + reg_addr = reg->osd1_blend_src_ctrl; + value = meson_drm_read_reg(reg->osd1_blend_src_ctrl); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD1_BLEND_SRC_CTRL", + reg_addr, value); + + reg_addr = reg->osd2_blend_src_ctrl; + value = meson_drm_read_reg(reg->osd2_blend_src_ctrl); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "OSD2_BLEND_SRC_CTRL", + reg_addr, value); + + reg_addr = reg->vd1_blend_src_ctrl; + value = meson_drm_read_reg(reg->vd1_blend_src_ctrl); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VD1_BLEND_SRC_CTRL", + reg_addr, value); + + reg_addr = reg->vd2_blend_src_ctrl; + value = meson_drm_read_reg(reg->vd2_blend_src_ctrl); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VD2_BLEND_SRC_CTRL", + reg_addr, value); + + reg_addr = reg->vpp_osd1_in_size; + value = meson_drm_read_reg(reg->vpp_osd1_in_size); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP_OSD1_IN_SIZE:", + reg_addr, value); + + reg_addr = reg->vpp_osd1_bld_h_scope; + value = meson_drm_read_reg(reg->vpp_osd1_bld_h_scope); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP_OSD1_BLD_H_SCOPE", + reg_addr, value); + + reg_addr = reg->vpp_osd1_bld_v_scope; + value = meson_drm_read_reg(reg->vpp_osd1_bld_v_scope); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP_OSD1_BLD_V_SCOPE", + reg_addr, value); + + reg_addr = reg->vpp_osd2_bld_h_scope; + value = meson_drm_read_reg(reg->vpp_osd2_bld_h_scope); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP_OSD2_BLD_H_SCOPE", + reg_addr, value); + + reg_addr = reg->vpp_osd2_bld_v_scope; + value = meson_drm_read_reg(reg->vpp_osd2_bld_v_scope); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP_OSD2_BLD_V_SCOPE", + reg_addr, value); + } else if (vblk->index == 1) { + reg_addr = VPP1_BLD_DIN0_HSCOPE; + value = meson_drm_read_reg(VPP1_BLD_DIN0_HSCOPE); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP1_BLD_DIN0_HSCOPE", + reg_addr, value); + + reg_addr = VPP1_BLD_DIN0_VSCOPE; + value = meson_drm_read_reg(VPP1_BLD_DIN0_VSCOPE); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP1_BLD_DIN0_VSCOPE", + reg_addr, value); + + reg_addr = VPP1_BLD_DIN1_HSCOPE; + value = meson_drm_read_reg(VPP1_BLD_DIN1_HSCOPE); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP1_BLD_DIN1_HSCOPE", + reg_addr, value); + + reg_addr = VPP1_BLD_DIN1_VSCOPE; + value = meson_drm_read_reg(VPP1_BLD_DIN1_VSCOPE); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP1_BLD_DIN1_VSCOPE", + reg_addr, value); + + reg_addr = VPP1_BLD_DIN2_HSCOPE; + value = meson_drm_read_reg(VPP1_BLD_DIN2_HSCOPE); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP1_BLD_DIN2_HSCOPE", + reg_addr, value); + + reg_addr = VPP1_BLD_DIN2_VSCOPE; + value = meson_drm_read_reg(VPP1_BLD_DIN2_VSCOPE); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP1_BLD_DIN2_VSCOPE", + reg_addr, value); + + reg_addr = VPP1_BLD_CTRL; + value = meson_drm_read_reg(VPP1_BLD_CTRL); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP1_BLD_CTRL", + reg_addr, value); + + reg_addr = VPP1_BLD_OUT_SIZE; + value = meson_drm_read_reg(VPP1_BLD_OUT_SIZE); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP1_BLD_OUT_SIZE", + reg_addr, value); + + reg_addr = VPP1_BLEND_BLEND_DUMMY_DATA; + value = meson_drm_read_reg(VPP1_BLEND_BLEND_DUMMY_DATA); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP1_BLEND_BLEND_DUMMY_DATA", + reg_addr, value); + + reg_addr = VPP1_BLEND_DUMMY_ALPHA; + value = meson_drm_read_reg(VPP1_BLEND_DUMMY_ALPHA); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP1_BLEND_DUMMY_ALPHA", + reg_addr, value); + } else if (vblk->index == 2) { + reg_addr = VPP2_BLD_DIN0_HSCOPE; + value = meson_drm_read_reg(VPP2_BLD_DIN0_HSCOPE); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP2_BLD_DIN0_HSCOPE", + reg_addr, value); + + reg_addr = VPP2_BLD_DIN0_VSCOPE; + value = meson_drm_read_reg(VPP2_BLD_DIN0_VSCOPE); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP2_BLD_DIN0_VSCOPE", + reg_addr, value); + + reg_addr = VPP2_BLD_DIN1_HSCOPE; + value = meson_drm_read_reg(VPP2_BLD_DIN1_HSCOPE); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP2_BLD_DIN1_HSCOPE", + reg_addr, value); + + reg_addr = VPP2_BLD_DIN1_VSCOPE; + value = meson_drm_read_reg(VPP2_BLD_DIN1_VSCOPE); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP2_BLD_DIN1_VSCOPE", + reg_addr, value); + + reg_addr = VPP2_BLD_DIN2_HSCOPE; + value = meson_drm_read_reg(VPP2_BLD_DIN2_HSCOPE); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP2_BLD_DIN2_HSCOPE", + reg_addr, value); + + reg_addr = VPP2_BLD_DIN2_VSCOPE; + value = meson_drm_read_reg(VPP2_BLD_DIN2_VSCOPE); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP2_BLD_DIN2_VSCOPE", + reg_addr, value); + + reg_addr = VPP2_BLD_CTRL; + value = meson_drm_read_reg(VPP2_BLD_CTRL); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP2_BLD_CTRL", + reg_addr, value); + + reg_addr = VPP2_BLD_OUT_SIZE; + value = meson_drm_read_reg(VPP2_BLD_OUT_SIZE); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP2_BLD_OUT_SIZE", + reg_addr, value); + + reg_addr = VPP2_BLEND_BLEND_DUMMY_DATA; + value = meson_drm_read_reg(VPP2_BLEND_BLEND_DUMMY_DATA); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP2_BLEND_BLEND_DUMMY_DATA", + reg_addr, value); + + reg_addr = VPP2_BLEND_DUMMY_ALPHA; + value = meson_drm_read_reg(VPP2_BLEND_DUMMY_ALPHA); + DRM_INFO("%-35s addr: 0x%08X\tvalue: 0x%08X\n", "VPP2_BLEND_DUMMY_ALPHA", + reg_addr, value); + } +} + /*based on crtc index select corresponding rdma handle write method*/ static void fix_vpu_clk2_default_regs(struct meson_vpu_block *vblk, struct rdma_reg_ops *reg_ops, int crtc_index, u32 *crtcmask_osd) @@ -928,6 +1140,7 @@ struct meson_vpu_block_ops postblend_ops = { .enable = postblend_hw_enable, .disable = postblend_hw_disable, .dump_register = postblend_dump_register, + .sysfs_dump_register = sysfs_postblend_dump_register, .init = postblend_hw_init, }; @@ -938,6 +1151,7 @@ struct meson_vpu_block_ops g12b_postblend_ops = { .enable = postblend_hw_enable, .disable = g12b_postblend_hw_disable, .dump_register = postblend_dump_register, + .sysfs_dump_register = sysfs_postblend_dump_register, .init = postblend_hw_init, }; @@ -947,6 +1161,7 @@ struct meson_vpu_block_ops t7_postblend_ops = { .enable = postblend_hw_enable, .disable = postblend_hw_disable, .dump_register = postblend_dump_register, + .sysfs_dump_register = t7_sysfs_postblend_dump_register, .init = t7_postblend_hw_init, }; @@ -956,6 +1171,7 @@ struct meson_vpu_block_ops t3_postblend_ops = { .enable = postblend_hw_enable, .disable = postblend_hw_disable, .dump_register = postblend_dump_register, + .sysfs_dump_register = sysfs_postblend_dump_register, .init = t3_postblend_hw_init, }; @@ -965,6 +1181,7 @@ struct meson_vpu_block_ops s5_postblend_ops = { .enable = postblend_hw_enable, .disable = s5_postblend_hw_disable, .dump_register = postblend_dump_register, + .sysfs_dump_register = sysfs_postblend_dump_register, .init = s5_postblend_hw_init, }; @@ -974,6 +1191,7 @@ struct meson_vpu_block_ops t3x_postblend_ops = { .enable = postblend_hw_enable, .disable = s5_postblend_hw_disable, .dump_register = postblend_dump_register, + .sysfs_dump_register = sysfs_postblend_dump_register, .init = t3x_postblend_hw_init, }; @@ -983,6 +1201,7 @@ struct meson_vpu_block_ops txhd2_postblend_ops = { .enable = postblend_hw_enable, .disable = postblend_hw_disable, .dump_register = postblend_dump_register, + .sysfs_dump_register = sysfs_postblend_dump_register, .init = txhd2_postblend_hw_init, };