From 916779b17cd0879ff37dc7a3c4fdefb63da99ad4 Mon Sep 17 00:00:00 2001 From: "xiang.wu1" Date: Fri, 12 Jan 2024 17:35:47 +0800 Subject: [PATCH] hdmitx: enable hdcp gate [1/1] PD#SWPL-152392 Problem: hdcp auth Solution: enable hdcp gate Verify: s7 Test: DRM-TX-37 Change-Id: Ica12428bcbc96bd2308a62c592c16e72ba693337 Signed-off-by: xiang.wu1 --- drivers/media/vout/hdmitx21/hw/hdmi_tx_hw.c | 2 ++ drivers/media/vout/hdmitx21/hw/interrupts.c | 28 ++++++++++----------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/media/vout/hdmitx21/hw/hdmi_tx_hw.c b/drivers/media/vout/hdmitx21/hw/hdmi_tx_hw.c index c3b41964a..933b16dec 100644 --- a/drivers/media/vout/hdmitx21/hw/hdmi_tx_hw.c +++ b/drivers/media/vout/hdmitx21/hw/hdmi_tx_hw.c @@ -430,6 +430,8 @@ static void hdmi_hwp_init(struct hdmitx_dev *hdev, u8 reset) hd21_set_reg_bits(CLKCTRL_HTX_CLK_CTRL1, 1, 24, 1); } + if (hdev->tx_hw.chip_data->chip_type == MESON_CPU_ID_S7) + hdmitx21_set_reg_bits(HDMITX_TOP_CLK_GATE, 3, 16, 2);//enable hdcp gate HDMITX_INFO("%s%d\n", __func__, __LINE__); if (!reset && hdmitx21_uboot_already_display()) { HDMITX_INFO("uboot already displayed\n"); diff --git a/drivers/media/vout/hdmitx21/hw/interrupts.c b/drivers/media/vout/hdmitx21/hw/interrupts.c index cd1593d16..317a241c3 100644 --- a/drivers/media/vout/hdmitx21/hw/interrupts.c +++ b/drivers/media/vout/hdmitx21/hw/interrupts.c @@ -251,22 +251,22 @@ static void intr_status_save_and_clear(void) { int i; struct intr_t *pint = (struct intr_t *)&hdmi_all_intrs; - struct hdmitx_dev *hdev = get_hdmitx21_device(); +// struct hdmitx_dev *hdev = get_hdmitx21_device(); for (i = 0; i < sizeof(union intr_u) / sizeof(struct intr_t); i++) { - if (hdev->tx_hw.chip_data->chip_type == MESON_CPU_ID_S7) { - if (hdev->tx_comm.hdcp_mode != 1) { - if (pint->intr_st_reg == TPI_INTR_ST0_IVCTX) - continue; - } - if (hdev->tx_comm.hdcp_mode != 2) { - if (pint->intr_st_reg == CP2TX_INTR0_IVCTX || - pint->intr_st_reg == CP2TX_INTR1_IVCTX || - pint->intr_st_reg == CP2TX_INTR2_IVCTX || - pint->intr_st_reg == CP2TX_INTR3_IVCTX) - continue; - } - } + // if (hdev->tx_hw.chip_data->chip_type == MESON_CPU_ID_S7) { + // if (hdev->tx_comm.hdcp_mode != 1) { + // if (pint->intr_st_reg == TPI_INTR_ST0_IVCTX) + // continue; + // } + // if (hdev->tx_comm.hdcp_mode != 2) { + // if (pint->intr_st_reg == CP2TX_INTR0_IVCTX || + // pint->intr_st_reg == CP2TX_INTR1_IVCTX || + // pint->intr_st_reg == CP2TX_INTR2_IVCTX || + // pint->intr_st_reg == CP2TX_INTR3_IVCTX) + // continue; + // } + // } pint->st_data = hdmitx21_rd_reg(pint->intr_st_reg); /* if (pint->intr_st_reg == TPI_INTR_ST0_IVCTX) */ /*HDMITX_INFO("TPI_INTR_ST0_IVCTX :0x%x\n", pint->st_data); */