From ae17aa4b79b30aa11bbbdc19133a3e89a4443336 Mon Sep 17 00:00:00 2001 From: "qinglin.li" Date: Wed, 31 May 2023 15:54:34 +0800 Subject: [PATCH] ddr_tool: some error need fix [1/1] PD#SWPL-123454 Problem: some error need fix Solution: dmc show include mode ddr banwidth device port set error ddr priority fix Verify: local Change-Id: If7d3034c9e18562b42d8ca235c79566f5c18147a Signed-off-by: qinglin.li --- drivers/memory_debug/ddr_tool/ddr_band_op_g12.c | 2 +- drivers/memory_debug/ddr_tool/ddr_band_op_s4.c | 2 +- drivers/memory_debug/ddr_tool/ddr_band_op_t5.c | 2 +- drivers/memory_debug/ddr_tool/ddr_bandwidth.c | 13 +++++++++++-- drivers/memory_debug/ddr_tool/ddr_bandwidth.h | 3 ++- drivers/memory_debug/ddr_tool/ddr_priority.c | 6 ++++-- drivers/memory_debug/ddr_tool/dmc_monitor.c | 10 +++------- 7 files changed, 23 insertions(+), 15 deletions(-) diff --git a/drivers/memory_debug/ddr_tool/ddr_band_op_g12.c b/drivers/memory_debug/ddr_tool/ddr_band_op_g12.c index 3b31582c1..cc04c620b 100644 --- a/drivers/memory_debug/ddr_tool/ddr_band_op_g12.c +++ b/drivers/memory_debug/ddr_tool/ddr_band_op_g12.c @@ -44,7 +44,7 @@ static void g12_dmc_port_config(struct ddr_bandwidth *db, int channel, int port) val = 0xffff; writel(val, db->ddr_reg1 + rs[channel]); } else { - val = (0x1 << 23); /* select device */ + val = (0x1 << 7); /* select device */ writel(val, db->ddr_reg1 + rp[channel]); val = readl(db->ddr_reg1 + rs[channel]); val |= (1 << subport); diff --git a/drivers/memory_debug/ddr_tool/ddr_band_op_s4.c b/drivers/memory_debug/ddr_tool/ddr_band_op_s4.c index 613bd1006..d8c94afba 100644 --- a/drivers/memory_debug/ddr_tool/ddr_band_op_s4.c +++ b/drivers/memory_debug/ddr_tool/ddr_band_op_s4.c @@ -92,7 +92,7 @@ static void s4_dmc_port_config(struct ddr_bandwidth *db, int channel, int port) val = 0xffff; writel(val, db->ddr_reg1 + off + 8); /* DMC_MON*_CTRL2 */ } else { - val = (0x1 << 23); /* select device */ + val = (0x1 << 7); /* select device */ writel(val, db->ddr_reg1 + off + 4); val = readl(db->ddr_reg1 + off + 8); val |= (1 << subport); diff --git a/drivers/memory_debug/ddr_tool/ddr_band_op_t5.c b/drivers/memory_debug/ddr_tool/ddr_band_op_t5.c index 0d6fb2980..14ca95fa4 100644 --- a/drivers/memory_debug/ddr_tool/ddr_band_op_t5.c +++ b/drivers/memory_debug/ddr_tool/ddr_band_op_t5.c @@ -92,7 +92,7 @@ static void t5_dmc_port_config(struct ddr_bandwidth *db, int channel, int port) val = 0xffff; writel(val, db->ddr_reg1 + off + 8); /* DMC_MON*_CTRL2 */ } else { - val = (0x1 << 23); /* select device */ + val = (0x1 << 7); /* select device */ writel(val, db->ddr_reg1 + off + 4); val = readl(db->ddr_reg1 + off + 8); val |= (1 << subport); diff --git a/drivers/memory_debug/ddr_tool/ddr_bandwidth.c b/drivers/memory_debug/ddr_tool/ddr_bandwidth.c index 4d43587f9..2ee9dbe51 100644 --- a/drivers/memory_debug/ddr_tool/ddr_bandwidth.c +++ b/drivers/memory_debug/ddr_tool/ddr_bandwidth.c @@ -76,6 +76,13 @@ static int dmc_dev_is_byte(struct ddr_bandwidth *db) return 0; } +static int ddr_width_is_16bit(struct ddr_bandwidth *db) +{ + if (db && (db->soc_feature & DDR_WIDTH_IS_16BIT)) + return 1; + return 0; +} + static int dmc_is_asymmetry(struct ddr_bandwidth *db) { if (db && (db->soc_feature & DMC_ASYMMETRY)) @@ -199,7 +206,7 @@ static void cal_ddr_usage(struct ddr_bandwidth *db, struct ddr_grant *dg) * After s4 soc, not register to distinguish ddr data bus width, * default ereryone dmc bus width is 32, but p1 and s5 is 16. */ - if (db->cpu_type == DMC_TYPE_P1 || db->cpu_type == DMC_TYPE_S5) + if (ddr_width_is_16bit(db)) mbw = (u64)freq * db->bytes_per_cycle * db->dmc_number / 2; else mbw = (u64)freq * db->bytes_per_cycle * db->dmc_number; @@ -445,7 +452,7 @@ static ssize_t port_store(struct class *cla, if (port < 0) /* clear port set */ aml_db->port[ch] = 0; else - aml_db->port[ch] |= 1ULL << (port & 0x1f); + aml_db->port[ch] |= 1ULL << (port & 0x3f); aml_db->ops->config_port(aml_db, ch, port); } } @@ -1216,6 +1223,7 @@ static int __init init_chip_config(int cpu, struct ddr_bandwidth *band) band->channels = 8; band->dmc_number = 4; band->soc_feature |= DMC_DEVICE_8BIT; + band->soc_feature |= DDR_WIDTH_IS_16BIT; band->mali_port[0] = 3; /* port3: mali */ band->mali_port[1] = 4; break; @@ -1264,6 +1272,7 @@ static int __init init_chip_config(int cpu, struct ddr_bandwidth *band) band->channels = 8; band->dmc_number = 4; band->soc_feature |= DMC_DEVICE_8BIT; + band->soc_feature |= DDR_WIDTH_IS_16BIT; band->mali_port[0] = 4; band->mali_port[1] = -1; break; diff --git a/drivers/memory_debug/ddr_tool/ddr_bandwidth.h b/drivers/memory_debug/ddr_tool/ddr_bandwidth.h index 1e250ba0a..a69e8129a 100644 --- a/drivers/memory_debug/ddr_tool/ddr_bandwidth.h +++ b/drivers/memory_debug/ddr_tool/ddr_bandwidth.h @@ -20,7 +20,8 @@ #define MAX_DMC_NUM 4 /* for soc_feature */ -#define DMC_ASYMMETRY BIT(3) +#define DMC_ASYMMETRY BIT(4) +#define DDR_WIDTH_IS_16BIT BIT(3) #define DMC_DEVICE_8BIT BIT(2) #define PLL_IS_SEC BIT(1) diff --git a/drivers/memory_debug/ddr_tool/ddr_priority.c b/drivers/memory_debug/ddr_tool/ddr_priority.c index 1573b5a70..171037c40 100644 --- a/drivers/memory_debug/ddr_tool/ddr_priority.c +++ b/drivers/memory_debug/ddr_tool/ddr_priority.c @@ -15,6 +15,8 @@ #include "ddr_port.h" #include "ddr_bandwidth.h" +#define PRIORITY_NUM (aml_db->ddr_priority_num & 0xffff) + static struct ddr_priority ddr_priority_s4[] __initdata = { { .port_id = 0, .reg_base = 0xfe036000, .reg_mode = 0, .reg_config = 0, @@ -797,7 +799,7 @@ static int ddr_priority_get_info(unsigned char port_id) return -EINVAL; } - for (i = 0; i < aml_db->ddr_priority_num; i++) { + for (i = 0; i < PRIORITY_NUM; i++) { if (aml_db->ddr_priority_desc[i].port_id == port_id) return i; } @@ -974,7 +976,7 @@ int priority_display(char *buf) "\tparm2: 'r' or 'w' priority (default set all)\n"); s += sprintf(buf + s, "\tid\t name \t\tw_current \tw_max \t\tr_current \tr_max\n"); - for (i = 0; i < aml_db->ddr_priority_num; i++) { + for (i = 0; i < PRIORITY_NUM; i++) { info = aml_db->ddr_priority_desc[i]; ret = ddr_priority_rw(info.port_id, &priority_r, &priority_w, DMC_READ); diff --git a/drivers/memory_debug/ddr_tool/dmc_monitor.c b/drivers/memory_debug/ddr_tool/dmc_monitor.c index 60b332cab..0b5af5089 100644 --- a/drivers/memory_debug/ddr_tool/dmc_monitor.c +++ b/drivers/memory_debug/ddr_tool/dmc_monitor.c @@ -374,7 +374,8 @@ size_t dump_dmc_reg(char *buf) sz += sprintf(buf + sz, "IO_BASE:%lx\n", dmc_mon->io_base); sz += sprintf(buf + sz, "RANGE:%lx - %lx\n", dmc_mon->addr_start, dmc_mon->addr_end); - sz += sprintf(buf + sz, "MONITOR DEVICE:\n"); + sz += sprintf(buf + sz, "MONITOR DEVICE(%s):\n", + dmc_mon->configs & POLICY_INCLUDE ? "include" : "exclude"); if (!dmc_mon->device) return sz; @@ -719,6 +720,7 @@ static void __init get_dmc_ops(int chip, struct dmc_monitor *mon) /* set default parameters */ mon->debug = 0x01; mon->mon_number = 1; + mon->configs |= POLICY_INCLUDE; switch (chip) { #ifdef CONFIG_AMLOGIC_DMC_MONITOR_G12 @@ -780,13 +782,11 @@ static void __init get_dmc_ops(int chip, struct dmc_monitor *mon) case DMC_TYPE_T7: case DMC_TYPE_T3: mon->ops = &t7_dmc_mon_ops; - mon->configs |= POLICY_INCLUDE; mon->configs |= DMC_DEVICE_8BIT; mon->mon_number = 2; break; case DMC_TYPE_P1: mon->ops = &t7_dmc_mon_ops; - mon->configs |= POLICY_INCLUDE; mon->configs |= DMC_DEVICE_8BIT; mon->mon_number = 4; break; @@ -800,14 +800,12 @@ static void __init get_dmc_ops(int chip, struct dmc_monitor *mon) #ifdef CONFIG_AMLOGIC_DMC_MONITOR_C3 case DMC_TYPE_C3: mon->ops = &c3_dmc_mon_ops; - mon->configs |= POLICY_INCLUDE; mon->configs |= DMC_DEVICE_8BIT; break; #endif #ifdef CONFIG_AMLOGIC_DMC_MONITOR_T5M case DMC_TYPE_T5M: mon->ops = &t5m_dmc_mon_ops; - mon->configs |= POLICY_INCLUDE; mon->configs |= DMC_DEVICE_8BIT; mon->mon_number = 2; break; @@ -815,13 +813,11 @@ static void __init get_dmc_ops(int chip, struct dmc_monitor *mon) #ifdef CONFIG_AMLOGIC_DMC_MONITOR_S5 case DMC_TYPE_S5: mon->ops = &s5_dmc_mon_ops; - mon->configs |= POLICY_INCLUDE; mon->configs |= DMC_DEVICE_8BIT; mon->mon_number = 4; break; case DMC_TYPE_T3X: mon->ops = &s5_dmc_mon_ops; - mon->configs |= POLICY_INCLUDE; mon->configs |= DMC_DEVICE_8BIT; mon->mon_number = 2; break;