From c100e8d5fe3caa3e5ee36810cd31b6bf01963ee2 Mon Sep 17 00:00:00 2001
From: jiebing chen <jiebing.chen@amlogic.com>
Date: Thu, 11 May 2023 16:55:26 +0800
Subject: [PATCH] Audio: support pdm dclk 2.048M for 32k [1/1]

PD#SWPL-123541

Problem:
need support pdm dclk 2.048M for 32k

Solution:
support pdm dclk 2.048M for 32k

Verify:
use t3x

Signed-off-by: jiebing chen <jiebing.chen@amlogic.com>
Change-Id: Idef51bd1047f956fe1933f76c4af7c19d176a1fd
---
 sound/soc/amlogic/auge/pdm.c    | 8 ++++++++
 sound/soc/amlogic/auge/pdm_hw.c | 9 +++++++++
 2 files changed, 17 insertions(+)

diff --git a/sound/soc/amlogic/auge/pdm.c b/sound/soc/amlogic/auge/pdm.c
index cc9fed1ef..3ad600892 100644
--- a/sound/soc/amlogic/auge/pdm.c
+++ b/sound/soc/amlogic/auge/pdm.c
@@ -169,6 +169,7 @@ static const char *const pdm_dclk_texts[] = {
 	"PDM Dclk 3.072m, support 8k/16k/32k/48k/64k/96k",
 	"PDM Dclk 1.024m, support 8k/16k",
 	"PDM Dclk   768k, support 8k/16k",
+	"PDM Dclk 2.048m, support 32k/16k/8k",
 };
 
 static const struct soc_enum pdm_dclk_enum =
@@ -1260,6 +1261,13 @@ static int aml_pdm_platform_probe(struct platform_device *pdev)
 	pr_debug("%s pdm train sample count from dts:%d\n",
 		__func__, p_pdm->train_sample_count);
 
+	ret = of_property_read_u32(node, "pdm_dclk_id",
+			&p_pdm->dclk_idx);
+	if (ret < 0)
+		p_pdm->dclk_idx = 0;
+	pr_debug("%s pdm dclk id  from dts:%d\n",
+		__func__, p_pdm->dclk_idx);
+
 	if (p_pdm->chipinfo->regulator) {
 		p_pdm->regulator_vcc3v3 = devm_regulator_get(dev, "pdm3v3");
 		ret = PTR_ERR_OR_ZERO(p_pdm->regulator_vcc3v3);
diff --git a/sound/soc/amlogic/auge/pdm_hw.c b/sound/soc/amlogic/auge/pdm_hw.c
index 42abbb8d4..0f943036d 100644
--- a/sound/soc/amlogic/auge/pdm_hw.c
+++ b/sound/soc/amlogic/auge/pdm_hw.c
@@ -532,6 +532,8 @@ int pdm_dclkidx2rate(int idx)
 		rate = 768000;
 	else if (idx == 1)
 		rate = 1024000;
+	else if (idx == 3)
+		rate = 2048000;
 	else
 		rate = 3072000;
 
@@ -577,6 +579,13 @@ int pdm_get_ors(int dclk_idx, int sample_rate)
 		else
 			pr_err("%s, Not support rate:%d\n",
 				__func__, sample_rate);
+	} else if (dclk_idx == 3) {
+		if (sample_rate == 32000)
+			osr = 64;
+		else if (sample_rate == 16000)
+			osr = 128;
+		else if (sample_rate == 16000)
+			osr = 256;
 	} else {
 		if (sample_rate == 96000)
 			osr = 32;