From c6077ace20140ff9fcf80446c8105fb9d8adcd0e Mon Sep 17 00:00:00 2001 From: Sunny Luo Date: Wed, 7 Dec 2022 17:02:38 +0800 Subject: [PATCH] spi: typo check fix [1/1] PD#SWPL-103904 Problem: spicc driver typo check failed Solution: correct it Verify: SC2 AH212 Change-Id: I1a90f6e967ae17e0f53e3ac46760455c26af8bdc Signed-off-by: Sunny Luo --- drivers/spi/spi-meson-spicc-slave.c | 4 ++-- drivers/spi/spi-meson-spicc.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-meson-spicc-slave.c b/drivers/spi/spi-meson-spicc-slave.c index b9d55f3ae..41bd83f9b 100644 --- a/drivers/spi/spi-meson-spicc-slave.c +++ b/drivers/spi/spi-meson-spicc-slave.c @@ -54,7 +54,7 @@ #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */ #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */ #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */ -#define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */ +#define SPICC_TC_EN BIT(7) /* Transfer Complete Interrupt */ #define SPICC_DMAREG 0x10 #define SPICC_DMA_ENABLE BIT(0) @@ -77,7 +77,7 @@ #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */ #define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */ #define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */ -#define SPICC_TC BIT(7) /* Transfert Complete Interrupt */ +#define SPICC_TC BIT(7) /* Transfer Complete Interrupt */ #define SPICC_PERIODREG 0x18 #define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */ diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index 8403a87ca..9f93db9f9 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -96,7 +96,7 @@ #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */ #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */ #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */ -#define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */ +#define SPICC_TC_EN BIT(7) /* Transfer Complete Interrupt */ #define SPICC_DMAREG 0x10 #define SPICC_DMA_ENABLE BIT(0) @@ -118,7 +118,7 @@ #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */ #define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */ #define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */ -#define SPICC_TC BIT(7) /* Transfert Complete Interrupt */ +#define SPICC_TC BIT(7) /* Transfer Complete Interrupt */ #define SPICC_PERIODREG 0x18 #define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */