diff --git a/drivers/media/di_multi/deinterlace.c b/drivers/media/di_multi/deinterlace.c
index 5548a6933..8c0ee47e8 100644
--- a/drivers/media/di_multi/deinterlace.c
+++ b/drivers/media/di_multi/deinterlace.c
@@ -5675,6 +5675,62 @@ unsigned char dim_pre_de_buf_config(unsigned int channel)
 			  vframe->index_disp,
 			  jiffies_to_msecs(jiffies_64 -
 			  vframe->ready_jiffies64));
+
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+		if (DIM_IS_IC_TXHD2) {
+			ppre->di_nrwr_mif.nr_wr_mif_8bit = -1;
+			if (!dimp_get(edi_mp_force_422_8bit)) {
+				if (pch->record_10bit_flag) {
+					pch->switch_index = pch->cur_index;
+					dim_print("set 10 bit\n");
+					pch->record_10bit_flag = 0;
+					pch->record_8bit_flag = 1;
+					ppre->di_nrwr_mif.nr_wr_mif_8bit = 0;
+				}
+			}
+			if (dimp_get(edi_mp_force_422_8bit) == 1) {
+				if (pch->record_8bit_flag) {
+					dim_print("set 8 bit\n");
+					pch->switch_index = pch->cur_index;
+					pch->record_10bit_flag = 1;
+					pch->record_8bit_flag = 0;
+					ppre->di_nrwr_mif.nr_wr_mif_8bit = 1;
+				}
+			}
+		}
+		dim_print("flag 10-8:<%d %d> index cur-switch:<%d %d> %d\n",
+			pch->record_10bit_flag, pch->record_8bit_flag,
+			pch->cur_index, pch->switch_index, ppre->di_nrwr_mif.nr_wr_mif_8bit);
+		if (ppre->di_nrwr_mif.nr_wr_mif_8bit == 1) {
+			if (pch->cur_index == (pch->switch_index + 1)) {
+				ppre->di_chan2_mif.bit8_flag = 1;
+				dim_print("di_chan2_mif->bit8_flag\n");
+			}
+
+			if (pch->cur_index == (pch->switch_index + 2)) {
+				ppre->di_mem_mif.bit8_flag = 1;
+				dim_print("di_mem_mif->bit8_flag\n");
+			}
+
+			if (pch->cur_index == (pch->switch_index + 4))
+				ppre->di_nrwr_mif.nr_wr_mif_8bit = 2;
+
+		} else if (!ppre->di_nrwr_mif.nr_wr_mif_8bit) {
+			if (pch->cur_index == (pch->switch_index + 1)) {
+				ppre->di_chan2_mif.bit8_flag = 0;
+				dim_print("di_chan2_mif->bit8_flag\n");
+			}
+
+			if (pch->cur_index == (pch->switch_index + 2)) {
+				ppre->di_mem_mif.bit8_flag = 0;
+				dim_print("di_mem_mif->bit8_flag\n");
+			}
+
+			if (pch->cur_index == (pch->switch_index + 4))
+				ppre->di_nrwr_mif.nr_wr_mif_8bit = 3;
+		}
+		dim_print("pch->cut_index:%d\n", pch->cur_index++);
+#endif
 		vframe->prog_proc_config = (cfg_prog_proc & 0x20) >> 5;
 
 		bit10_pack_patch =  (is_meson_gxtvbb_cpu() ||
@@ -7583,6 +7639,9 @@ static void dimpst_fill_outvf(struct vframe_s *vfm,
 	unsigned int ch;
 	struct di_ch_s *pch;
 	bool ext_buf = false;
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	unsigned int ori_vfm_bitdepth;
+#endif
 
 	//check ext buffer:
 	ch = di_buf->channel;
@@ -7686,7 +7745,18 @@ static void dimpst_fill_outvf(struct vframe_s *vfm,
 				  BITDEPTH_U8	|
 				  BITDEPTH_V8);
 	}
-
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	ori_vfm_bitdepth = vfm->bitdepth;
+	if (di_buf->bit_8_flag == 1) {
+		dim_print("bitdepth: 0x%x\n", vfm->bitdepth);
+		vfm->bitdepth &= ~(BITDEPTH_MASK);
+		vfm->bitdepth |= (FULL_PACK_422_MODE);
+		vfm->bitdepth |= (BITDEPTH_Y8	| BITDEPTH_U8 | BITDEPTH_V8);
+	} else if (!di_buf->bit_8_flag) {
+		vfm->bitdepth = ori_vfm_bitdepth;
+	}
+	dim_print("%s bitdepth: 0x%x\n", __func__, vfm->bitdepth);
+#endif
 	if (de_devp->pps_enable &&
 	    dimp_get(edi_mp_pps_position) == 0) {
 		if (dimp_get(edi_mp_pps_dstw))
@@ -8032,7 +8102,16 @@ int dim_post_process(void *arg, unsigned int zoom_start_x_lines,
 	}
 	if (dip_itf_is_ins(pch) && dim_dbg_new_int(2))
 		dim_dbg_buffer2(di_buf->c.buffer, 7);
-
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	if (DIM_IS_IC_TXHD2) {
+		ppost->di_buf2_mif.bit8_flag = ppre->di_nrwr_mif.nr_wr_mif_8bit;
+		dim_print("di_nrwr_mif.nr_wr_mif_8bit:%d\n", ppre->di_nrwr_mif.nr_wr_mif_8bit);
+		if (ppost->di_buf2_mif.bit8_flag == 1 || ppost->di_buf2_mif.bit8_flag == 2)
+			di_buf->bit_8_flag = 1;
+		else if (ppost->di_buf2_mif.bit8_flag == 0 || ppost->di_buf2_mif.bit8_flag == 3)
+			di_buf->bit_8_flag = 0;
+	}
+#endif
 #ifdef DIM_OUT_NV21
 	/* nv 21*/
 	if (is_mask(SC2_DW_EN))
@@ -8765,6 +8844,13 @@ int dim_post_process(void *arg, unsigned int zoom_start_x_lines,
 			}
 			/* */
 		} else {
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+			if (DIM_IS_IC_TXHD2) {
+				ppost->di_buf0_mif.bit8_flag = ppre->di_chan2_mif.bit8_flag;
+				ppost->di_buf1_mif.bit8_flag = ppre->di_mem_mif.bit8_flag;
+				ppost->di_buf2_mif.bit8_flag = ppre->di_nrwr_mif.nr_wr_mif_8bit;
+			}
+#endif
 			dimh_enable_di_post_2
 				(&ppost->di_buf0_mif,
 				 &ppost->di_buf1_mif,
@@ -8829,6 +8915,13 @@ int dim_post_process(void *arg, unsigned int zoom_start_x_lines,
 				dim_print("0x%px:\n", acfg->buf_o->vframe);
 			}
 		} else {
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+			if (DIM_IS_IC_TXHD2) {
+				ppost->di_buf0_mif.bit8_flag = ppre->di_chan2_mif.bit8_flag;
+				ppost->di_buf1_mif.bit8_flag = ppre->di_mem_mif.bit8_flag;
+				ppost->di_buf2_mif.bit8_flag = ppre->di_nrwr_mif.nr_wr_mif_8bit;
+			}
+#endif
 			dimh_post_switch_buffer
 				(&ppost->di_buf0_mif,
 				 &ppost->di_buf1_mif,
@@ -9524,6 +9617,14 @@ static void set_pulldown_mode(struct di_buf_s *di_buf, unsigned int channel)
 			if (pre_buf_p) {
 				di_buf->pd_config.global_mode =
 					pre_buf_p->pd_config.global_mode;
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+				if (DIM_IS_IC_TXHD2) {
+					if (ppre->di_nrwr_mif.nr_wr_mif_8bit == 1 ||
+						ppre->di_nrwr_mif.nr_wr_mif_8bit == 0) {
+						di_buf->pd_config.global_mode = PULL_DOWN_EI;
+					}
+				}
+#endif
 			} else {
 				/* ary add 2019-06-19*/
 				di_buf->pd_config.global_mode =
@@ -10722,6 +10823,10 @@ void di_unreg_variable(unsigned int channel)
 	pch->sumx.need_local = 0;
 	pch->self_trig_need = 0;
 	pch->rsc_bypass.d32 = 0;
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	pch->record_10bit_flag = 0;
+	pch->record_8bit_flag = 0;
+#endif
 	set_bypass2_complete(channel, false);
 	init_completion(&tsk->fcmd[channel].alloc_done);
 	dbg_timer_clear(channel);
diff --git a/drivers/media/di_multi/deinterlace.h b/drivers/media/di_multi/deinterlace.h
index 4362bccf1..e8adc576a 100644
--- a/drivers/media/di_multi/deinterlace.h
+++ b/drivers/media/di_multi/deinterlace.h
@@ -382,6 +382,9 @@ struct di_buf_s {
 	bool hf_irq;
 	bool dw_have;
 	bool flg_dummy;
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	bool bit_8_flag;
+#endif
 };
 
 #define RDMA_DET3D_IRQ			0x20
diff --git a/drivers/media/di_multi/deinterlace_hw.c b/drivers/media/di_multi/deinterlace_hw.c
index 8d964fc1a..1c0345044 100644
--- a/drivers/media/di_multi/deinterlace_hw.c
+++ b/drivers/media/di_multi/deinterlace_hw.c
@@ -1730,6 +1730,9 @@ static void set_di_mem_mif(struct DI_MIF_S *mif, int urgent, int hold_line)
 	unsigned int chroma0_rpt_loop_end;
 	unsigned int chroma0_rpt_loop_pat;
 	unsigned int reset_on_gofield;
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	unsigned int bit_mode_val;
+#endif
 
 	if (mif->set_separate_en != 0 && mif->src_field_mode == 1) {
 		chro_rpt_lastl_ctrl = 1;
@@ -1765,6 +1768,14 @@ static void set_di_mem_mif(struct DI_MIF_S *mif, int urgent, int hold_line)
 		chroma0_rpt_loop_pat = 0x00;
 	}
 
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	bit_mode_val = mif->bit_mode;
+	if (mif->bit8_flag == 1)
+		mif->bit_mode = 0;
+	else if (!mif->bit8_flag)
+		mif->bit_mode = 0x3;
+	dim_print("mif->bit_mode:%d\n", mif->bit_mode);
+#endif
 	bytes_per_pixel = mif->set_separate_en ? 0 : (mif->video_mode ? 2 : 1);
 	demux_mode = mif->video_mode;
 
@@ -2215,6 +2226,9 @@ static void set_di_chan2_mif(struct DI_MIF_S *mif, int urgent, int hold_line)
 	unsigned int chroma0_rpt_loop_end;
 	unsigned int chroma0_rpt_loop_pat;
 	unsigned int reset_on_gofield;
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	unsigned int bit_mode_val;
+#endif
 
 	if (mif->set_separate_en != 0 && mif->src_field_mode == 1) {
 		chro_rpt_lastl_ctrl = 1;
@@ -2262,7 +2276,15 @@ static void set_di_chan2_mif(struct DI_MIF_S *mif, int urgent, int hold_line)
 	}
 	#endif
 	demux_mode = mif->video_mode;
-
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	bit_mode_val = mif->video_mode;
+	dim_print("mif->bit8_flag:%d %d\n", mif->bit8_flag, mif->video_mode);
+	if (mif->bit8_flag == 1)
+		mif->bit_mode = 0;
+	else if (!mif->bit8_flag)
+		mif->bit_mode = 0x3;
+	dim_print("mif->bit_mode:%d\n", mif->bit_mode);
+#endif
 	/* ---------------------- */
 	/* General register */
 	/* ---------------------- */
@@ -2843,6 +2865,9 @@ void dimh_post_switch_buffer(struct DI_MIF_S *di_buf0_mif,
 			     bool mc_enable, int vskip_cnt)
 {
 	int ei_only, buf1_en;
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	unsigned int bit_val[3] = {3, 3, 3};
+#endif
 
 	ei_only = ei_en && !blend_en && (di_vpp_en || di_ddr_en);
 	buf1_en =  (!ei_only && (di_ddr_en || di_vpp_en));
@@ -2885,6 +2910,32 @@ void dimh_post_switch_buffer(struct DI_MIF_S *di_buf0_mif,
 						  di_mtnprd_mif->canvas_num, 16, 8);
 			/* current field mtn canvas index.*/
 		}
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+		if (DIM_IS_IC_TXHD2) {
+			/**
+			 ** post mif bitdepth follow nr mif change frame by frame
+			 ** 422 10bit: bit_val[*] = 0x3  422 8bit: bit_val[*] = 0x0
+			 ** post mif regs changed frame by frame due to the reference frame
+			 **/
+			if (di_buf2_mif->bit8_flag == 1 || di_buf2_mif->bit8_flag == 2)
+				bit_val[2] = 0;
+			if (di_buf0_mif->bit8_flag == 1)
+				bit_val[0] = 0;
+			if (di_buf1_mif->bit8_flag == 1)
+				bit_val[1] = 0;
+			if (!di_buf2_mif->bit8_flag)
+				bit_val[2] = 0x3;
+			if (!di_buf0_mif->bit8_flag)
+				bit_val[0] = 0x3;
+			if (!di_buf1_mif->bit8_flag)
+				bit_val[1] = 0x3;
+			DIM_DI_WR_REG_BITS(DI_IF0_GEN_REG3, bit_val[0] & 0x3, 8, 2);
+			DIM_DI_WR_REG_BITS(DI_IF1_GEN_REG3, bit_val[1] & 0x3, 8, 2);
+			DIM_DI_WR_REG_BITS(DI_IF2_GEN_REG3, bit_val[2] & 0x3, 8, 2);
+			DIM_DI_WR_REG_BITS(DI_DIWR_Y, bit_val[2] & 0x1, 14, 1);
+			DIM_DI_WR_REG_BITS(DI_DIWR_CTRL, bit_val[2] & 0x3, 22, 2);
+		}
+#endif
 	} else {
 		if ((VSYNC_RD_MPEG_REG(VIU_MISC_CTRL0) & 0x50000) != 0x50000)
 			DIM_VSC_WR_MPG_BT(VIU_MISC_CTRL0, 5, 16, 3);
@@ -3181,6 +3232,16 @@ void dimh_enable_di_post_2(struct DI_MIF_S		   *di_buf0_mif,
 						 di_diwr_mif->bit_mode);
 		} else {
 			dimh_pst_mif_set(di_diwr_mif, urgent, di_ddr_en);
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+			if (di_buf2_mif->bit8_flag == 1 || di_buf2_mif->bit8_flag == 2) {
+				di_buf2_mif->bit_mode = 0;
+				di_diwr_mif->bit_mode = 0;
+			}
+			if (di_buf0_mif->bit8_flag == 1)
+				di_buf0_mif->bit_mode = 0;
+			if (di_buf1_mif->bit8_flag == 1)
+				di_buf1_mif->bit_mode = 0;
+#endif
 			post_bit_mode_config(di_buf0_mif->bit_mode,
 					     di_buf1_mif->bit_mode,
 					     di_buf2_mif->bit_mode,
@@ -3201,6 +3262,16 @@ void dimh_enable_di_post_2(struct DI_MIF_S		   *di_buf0_mif,
 				      (urgent << 16)		|
 				      (2 << 26)			|
 				      (di_ddr_en << 30));
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+		if (di_buf2_mif->bit8_flag == 1 || di_buf2_mif->bit8_flag == 2) {
+			di_buf2_mif->bit_mode = 0;
+			di_diwr_mif->bit_mode = 0;
+		}
+		if (di_buf0_mif->bit8_flag == 1)
+			di_buf0_mif->bit_mode = 0;
+		if (di_buf1_mif->bit8_flag == 1)
+			di_buf1_mif->bit_mode = 0;
+#endif
 		post_bit_mode_config(di_buf0_mif->bit_mode,
 				     di_buf1_mif->bit_mode,
 				     di_buf2_mif->bit_mode,
@@ -5107,6 +5178,9 @@ static void dimh_wrmif_set(struct DI_SIM_MIF_S *cfg_mif,
 {
 	const unsigned int *reg;
 	unsigned int ctr;
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	unsigned int bit_mode_val;
+#endif
 
 	reg = &reg_mifs[mifsel][0];
 
@@ -5116,6 +5190,17 @@ static void dimh_wrmif_set(struct DI_SIM_MIF_S *cfg_mif,
 	if (!cfg_mif->ddr_en)
 		return;
 
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	if (DIM_IS_IC_TXHD2) {
+		bit_mode_val = cfg_mif->bit_mode;
+		if (cfg_mif->nr_wr_mif_8bit == 1 ||
+			cfg_mif->nr_wr_mif_8bit == 2) {
+			cfg_mif->bit_mode = 0;
+		} else if (cfg_mif->nr_wr_mif_8bit == 0)
+			cfg_mif->bit_mode = bit_mode_val;
+	}
+#endif
+
 	ops->wr(reg[EDI_MIFS_X],
 		(cfg_mif->l_endian		<< 31)	|
 		(cfg_mif->start_x	<< 16)	|	/* [29:16]*/
diff --git a/drivers/media/di_multi/deinterlace_hw.h b/drivers/media/di_multi/deinterlace_hw.h
index ff486bf9a..3e971681d 100644
--- a/drivers/media/di_multi/deinterlace_hw.h
+++ b/drivers/media/di_multi/deinterlace_hw.h
@@ -327,6 +327,9 @@ struct DI_MIF_S {
 	/**/
 	enum DI_MIF0_ID	mif_index; /* */
 	char *name;
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	unsigned int bit8_flag;
+#endif
 };
 
 struct DI_SIM_MIF_S {
@@ -380,6 +383,10 @@ struct DI_SIM_MIF_S {
 	unsigned short blend_en;		//20220126
 	unsigned short vecrd_offset;	//20220126
 	enum DI_MIFS_ID	mif_index; /* */
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	unsigned int nr_wr_mif_8bit	:3;
+	bool di_wr_bit8_flag;
+#endif
 };
 
 struct DI_MC_MIF_s {
diff --git a/drivers/media/di_multi/di_data_l.h b/drivers/media/di_multi/di_data_l.h
index 93ccc87d9..270613748 100644
--- a/drivers/media/di_multi/di_data_l.h
+++ b/drivers/media/di_multi/di_data_l.h
@@ -173,6 +173,9 @@ enum EDI_CFG_TOP_IDX {
 	EDI_CFG_EN_PRE_LINK,
 	EDI_CFG_AFBCE_LOSS_EN,
 	EDI_CFG_TB,
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	EDI_CFG_TEMP_CONTROL,
+#endif
 	EDI_CFG_END,
 };
 
@@ -1079,6 +1082,9 @@ enum EDI_MP_UI_T {
 	edi_mp_blend_mode,
 	edi_mp_tb_dump,
 	edi_mp_prelink_hold_line,
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	edi_mp_force_422_8bit,
+#endif
 	EDI_MP_SUB_DI_E,
 	/**************************************/
 	EDI_MP_SUB_NR_B,
@@ -2080,6 +2086,12 @@ struct di_ch_s {
 	bool en_tb; //
 	unsigned char tb_owner;	//
 	bool	tb_busy;//
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	bool record_8bit_flag;
+	bool record_10bit_flag;
+	unsigned int cur_index;
+	unsigned int switch_index;
+#endif
 };
 
 struct dim_policy_s {
diff --git a/drivers/media/di_multi/di_prc.c b/drivers/media/di_multi/di_prc.c
index 28c6f0dc6..6b420e883 100644
--- a/drivers/media/di_multi/di_prc.c
+++ b/drivers/media/di_multi/di_prc.c
@@ -291,6 +291,12 @@ const struct di_cfg_ctr_s di_cfg_top_ctr[K_DI_CFG_NUB] = {
 			EDI_CFG_TB,
 			0,
 			K_DI_CFG_T_FLG_DTS},
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	[EDI_CFG_TEMP_CONTROL]  = {"temp_control",
+			EDI_CFG_TEMP_CONTROL,
+			0,
+			K_DI_CFG_T_FLG_DTS},
+#endif
 	[EDI_CFG_END]  = {"cfg top end ", EDI_CFG_END, 0,
 			K_DI_CFG_T_FLG_NONE},
 
@@ -916,6 +922,10 @@ const struct di_mp_uit_s di_mp_ui_top[] = {
 				edi_mp_tb_dump, 0},//1400
 	[edi_mp_prelink_hold_line]	= {"pre_hold_line:ushort:8",
 				edi_mp_prelink_hold_line, 8},
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	[edi_mp_force_422_8bit]	= {"force_422_8bit:8",
+				edi_mp_force_422_8bit, -1},
+#endif
 	[EDI_MP_SUB_DI_E]  = {"di end-------",
 				EDI_MP_SUB_DI_E, 0},
 	/**************************************/
@@ -3188,6 +3198,10 @@ void dip_init_value_reg(unsigned int ch, struct vframe_s *vframe)
 		dimp_set(edi_mp_prog_proc_config, 0x23);
 		dimp_set(edi_mp_use_2_interlace_buff, 1);
 	}
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	pch->record_10bit_flag = 1;
+	pch->record_8bit_flag = 1;
+#endif
 	pch->src_type = vframe->source_type;
 	if ((vframe->flag & VFRAME_FLAG_DI_P_ONLY) || bget(&dim_cfg, 1))
 		ponly_enable = true;
diff --git a/drivers/media/di_multi/di_sys.c b/drivers/media/di_multi/di_sys.c
index 8a2576947..8091d9954 100644
--- a/drivers/media/di_multi/di_sys.c
+++ b/drivers/media/di_multi/di_sys.c
@@ -53,6 +53,10 @@
 /*dma_get_cma_size_int_byte*/
 #include <linux/amlogic/media/codec_mm/codec_mm.h>
 
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+#include <linux/amlogic/media_cooling.h>
+#endif
+
 #include "deinterlace_dbg.h"
 #include "deinterlace.h"
 #include "di_data_l.h"
@@ -2636,6 +2640,57 @@ unsigned int mem_release_free(struct di_ch_s *pch)
 	return rls_pst;
 }
 
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+
+struct media_cooling_device *cool_device;
+
+void register_media_cooling(void)
+{
+	struct thermal_cooling_device *ret = 0;
+
+	if (!cfgg(TEMP_CONTROL))
+		return;
+	cool_device = kzalloc(sizeof(*cool_device), GFP_KERNEL);
+	if  (!cool_device) {
+		PR_ERR("%s fail to register cool_device memory.\n", __func__);
+		return;
+	}
+	ret = media_cooling_register(cool_device);
+	if (!ret) {
+		PR_ERR("%s: failed to allocate major number\n", __func__);
+		goto fail_media_cooling_register;
+	}
+	cool_device->maxstep =	2;
+	cool_device->set_media_cooling_state = set_bitmode_from_state;
+
+fail_media_cooling_register:
+	kfree(cool_device);
+	cool_device = NULL;
+}
+
+void unregister_media_cooling(void)
+{
+	if (!cfgg(TEMP_CONTROL))
+		return;
+	kfree(cool_device);
+	cool_device = NULL;
+}
+
+int set_bitmode_from_state(int state)
+{
+	if (!cfgg(TEMP_CONTROL))
+		return 0;
+	if (state == 0) {
+		dimp_set(edi_mp_force_422_8bit, 0);
+		dim_print("bit_mode :10");
+	}
+	if (state == 1 || state == 2) {
+		dimp_set(edi_mp_force_422_8bit, 1);
+		dim_print("bit_mode :8");
+	}
+	return 1;
+}
+#endif
 /********************************************/
 /* post afbc table */
 
@@ -4052,7 +4107,9 @@ static int dim_probe(struct platform_device *pdev)
 	dim_debugfs_init();	/*2018-07-18 add debugfs*/
 
 	dimh_patch_post_update_mc_sw(DI_MC_SW_IC, true);
-
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+	register_media_cooling();
+#endif
 	PR_INF("%s:ok\n", __func__);
 	return ret;
 
@@ -4150,6 +4207,10 @@ static int dim_remove(struct platform_device *pdev)
 	di_pdev->local_ud_addr = NULL;
 	kfree(di_pdev);
 	di_pdev = NULL;
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+
+	unregister_media_cooling();
+#endif
 	PR_INF("%s:finish\n", __func__);
 	return 0;
 }
diff --git a/drivers/media/di_multi/di_sys.h b/drivers/media/di_multi/di_sys.h
index 47523283c..a8802219c 100644
--- a/drivers/media/di_multi/di_sys.h
+++ b/drivers/media/di_multi/di_sys.h
@@ -152,5 +152,11 @@ bool mm_codec_alloc(const char *owner, size_t count,
 			   struct dim_mm_s *o,
 			   bool tvp_flg);
 
+#ifdef CONFIG_AMLOGIC_MEDIA_THERMAL
+
+void unregister_media_cooling(void);
+int set_bitmode_from_state(int state);
+void register_media_cooling(void);
+#endif
 /*-------------------------*/
 #endif	/*__DI_SYS_H__*/