diff --git a/arch/arm64/boot/dts/amlogic/mesont7c_drm.dtsi b/arch/arm64/boot/dts/amlogic/mesont7c_drm.dtsi new file mode 100644 index 000000000..96121befd --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/mesont7c_drm.dtsi @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include +#include "mesont7c.dtsi" + +/ { + drm_amcvbsout: drm-amcvbsout { + status = "disabled"; + compatible = "amlogic, drm-cvbsout"; + dev_name = "meson-amcvbsout"; + ports { + port { + #address-cells = <1>; + #size-cells = <0>; + cvbs_to_drm: endpoint@0 { + reg = <0>; + remote-endpoint = <&drm_to_cvbs>; + }; + }; + }; + }; + + drm_vpu: drm-vpu@0xff900000 { + status = "disabled"; + compatible = "amlogic, meson-t7-vpu"; + osd_ver = /bits/ 8 ; + reg = <0x0 0xff900000 0x0 0x40000>, + <0x0 0xff63c000 0x0 0x2000>, + <0x0 0xff638000 0x0 0x2000>; + reg-names = "base", "hhi", "dmc"; + interrupts = , + , + ; + interrupt-names = "drm-viu-vsync", "drm-viu2-vsync", + "drm-viu3-vsync"; + clocks = <&clkc CLKID_VPU_CLKC_MUX>; + clock-names = "vpu_clkc"; + dma-coherent; + /*EXTERNAL port for driver outside of drm.*/ + connectors_dev: port@1 { + #address-cells = <1>; + #size-cells = <0>; + drm_to_hdmitx: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmitx_to_drm>; + }; + drm_to_cvbs: endpoint@1 { + reg = <1>; + remote-endpoint = <&cvbs_to_drm>; + }; + drm_to_lcd0: endpoint@2 { + reg = <2>; + remote-endpoint = <0>; + }; + drm_to_lcd1: endpoint@3 { + reg = <3>; + remote-endpoint = <0>; + }; + drm_to_lcd2: endpoint@4 { + reg = <4>; + remote-endpoint = <0>; + }; + }; + }; + + drm_subsystem: drm-subsystem { + status = "okay"; + compatible = "amlogic, drm-subsystem"; + ports = <&connectors_dev>; + fbdev_sizes = <1920 1080 1920 2160 32>; + osd_ver = /bits/ 8 ; + vfm_mode = <1>; /** 0:drm mode 1:composer mode */ + memory-region = <&logo_reserved>; + crtc_masks = <7 7 1>; /*for encoder: 0:hdmi 1:lcd 2:cvbs*/ + crtcmask_of_osd = <0 0 1 2>; /* indicate the crtc mask of osd plane */ + crtcmask_of_video = <0 1 2>; /* indicate the crtc mask of video plane */ + + vpu_topology: vpu_topology { + vpu_blocks { + osd1_block: block@0 { + id = /bits/ 8 ; + index = /bits/ 8 <0>; + type = /bits/ 8 <0>; + block_name = "osd1_block"; + num_in_links = /bits/ 8 <0x0>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &afbc1_block>; + }; + osd2_block: block@1 { + id = /bits/ 8 ; + index = /bits/ 8 <1>; + type = /bits/ 8 <0>; + block_name = "osd2_block"; + num_in_links = /bits/ 8 <0x0>; + num_out_links = /bits/ 8 <0x1>; + out_links = <1 &afbc1_block>; + }; + osd3_block: block@2 { + id = /bits/ 8 ; + index = /bits/ 8 <2>; + type = /bits/ 8 <0>; + block_name = "osd3_block"; + num_in_links = /bits/ 8 <0x0>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &afbc2_block>; + }; + osd4_block: block@3 { + id = /bits/ 8 ; + index = /bits/ 8 <3>; + type = /bits/ 8 <0>; + block_name = "osd4_block"; + num_in_links = /bits/ 8 <0x0>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &afbc3_block>; + }; + afbc1_block: block@4 { + id = /bits/ 8 ; + index = /bits/ 8 <0>; + type = /bits/ 8 <1>; + block_name = "afbc1_block"; + num_in_links = /bits/ 8 <0x2>; + in_links = <0 &osd1_block>, + <0 &osd2_block>; + num_out_links = /bits/ 8 <0x2>; + out_links = <0 &osd_blend_block>, + <0 &scaler2_block>; + }; + afbc2_block: block@5 { + id = /bits/ 8 ; + index = /bits/ 8 <1>; + type = /bits/ 8 <1>; + block_name = "afbc2_block"; + num_in_links = /bits/ 8 <0x1>; + in_links = <0 &osd3_block>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &scaler3_block>; + }; + afbc3_block: block@6 { + id = /bits/ 8 ; + index = /bits/ 8 <2>; + type = /bits/ 8 <1>; + block_name = "afbc3_block"; + num_in_links = /bits/ 8 <0x1>; + in_links = <0 &osd4_block>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &scaler4_block>; + }; + scaler1_block: block@7 { + id = /bits/ 8 ; + index = /bits/ 8 <0>; + type = /bits/ 8 <2>; + block_name = "scaler1_block"; + num_in_links = /bits/ 8 <0x1>; + in_links = <0 &hdr1_block>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &vpp1_postblend_block>; + }; + scaler2_block: block@8 { + id = /bits/ 8 ; + index = /bits/ 8 <1>; + type = /bits/ 8 <2>; + block_name = "scaler2_block"; + num_in_links = /bits/ 8 <0x1>; + in_links = <1 &afbc1_block>; + num_out_links = /bits/ 8 <0x1>; + out_links = <1 &osd_blend_block>; + }; + scaler3_block: block@9 { + id = /bits/ 8 ; + index = /bits/ 8 <2>; + type = /bits/ 8 <2>; + block_name = "scaler3_block"; + num_in_links = /bits/ 8 <0x1>; + in_links = <0 &afbc2_block>; + num_out_links = /bits/ 8 <0x2>; + out_links = <2 &osd_blend_block>, + <0 &hdr2_block>; + }; + scaler4_block: block@10 { + id = /bits/ 8 ; + index = /bits/ 8 <3>; + type = /bits/ 8 <2>; + block_name = "scaler4_block"; + num_in_links = /bits/ 8 <0x1>; + in_links = <0 &afbc3_block>; + num_out_links = /bits/ 8 <0x2>; + out_links = <3 &osd_blend_block>, + <0 &vpp3_postblend_block>; + }; + osd_blend_block: block@11 { + id = /bits/ 8 ; + block_name = "osd_blend_block"; + type = /bits/ 8 <3>; + num_in_links = /bits/ 8 <0x4>; + in_links = <0 &afbc1_block>, + <0 &scaler2_block>, + <0 &scaler3_block>, + <0 &scaler4_block>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &hdr1_block>; + }; + hdr1_block: block@12 { + id = /bits/ 8 ; + index = /bits/ 8 <0>; + block_name = "hdr1_block"; + type = /bits/ 8 <4>; + num_in_links = /bits/ 8 <0x1>; + in_links = <0 &osd_blend_block>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &scaler1_block>; + }; + hdr2_block: block@13 { + id = /bits/ 8 ; + index = /bits/ 8 <1>; + block_name = "hdr2_block"; + type = /bits/ 8 <4>; + num_in_links = /bits/ 8 <0x1>; + in_links = <1 &osd_blend_block>; + num_out_links = /bits/ 8 <0x1>; + out_links = <0 &vpp2_postblend_block>; + }; + vpp1_postblend_block: block@14 { + id = /bits/ 8 ; + index = /bits/ 8 <0>; + block_name = "vpp1_postblend_block"; + type = /bits/ 8 <6>; + num_in_links = /bits/ 8 <0x1>; + in_links = <0 &scaler1_block>; + num_out_links = <0x0>; + }; + vpp2_postblend_block: block@15 { + id = /bits/ 8 ; + index = /bits/ 8 <1>; + block_name = "vpp2_postblend_block"; + type = /bits/ 8 <6>; + num_in_links = /bits/ 8 <0x1>; + in_links = <1 &hdr2_block>; + num_out_links = <0x0>; + }; + vpp3_postblend_block: block@16 { + id = /bits/ 8 ; + index = /bits/ 8 <2>; + block_name = "vpp3_postblend_block"; + type = /bits/ 8 <6>; + num_in_links = /bits/ 8 <0x1>; + in_links = <0 &scaler4_block>; + num_out_links = <0x0>; + }; + video1_block: block@17 { + id = /bits/ 8 ; + index = /bits/ 8 <0>; + type = /bits/ 8 <7>; + block_name = "video1_block"; + num_in_links = /bits/ 8 <0x0>; + num_out_links = /bits/ 8 <0x0>; + }; + video2_block: block@18 { + id = /bits/ 8 ; + index = /bits/ 8 <1>; + type = /bits/ 8 <7>; + block_name = "video2_block"; + num_in_links = /bits/ 8 <0x0>; + num_out_links = /bits/ 8 <0x0>; + }; + video3_block: block@19 { + id = /bits/ 8 ; + index = /bits/ 8 <2>; + type = /bits/ 8 <7>; + block_name = "video3_block"; + num_in_links = /bits/ 8 <0x0>; + num_out_links = /bits/ 8 <0x0>; + }; + }; + }; + + vpu_hw_para: vpu_hw_para@0 { + osd_ver = /bits/ 8 ; + afbc_type = /bits/ 8 <0x2>; + has_deband = /bits/ 8 <0x1>; + has_lut = /bits/ 8 <0x1>; + has_rdma = /bits/ 8 <0x1>; + osd_fifo_len = /bits/ 8 <64>; + vpp_fifo_len = /bits/ 32 <0xfff>; + }; + }; +}; + +&amhdmitx { + ports { + port { + #address-cells = <1>; + #size-cells = <0>; + hdmitx_to_drm: endpoint@0 { + reg = <0>; + remote-endpoint = <&drm_to_hdmitx>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/t7c_a311d2_an400_4g.dts b/arch/arm64/boot/dts/amlogic/t7c_a311d2_an400_4g.dts index f1a30a0c6..846f88d0c 100644 --- a/arch/arm64/boot/dts/amlogic/t7c_a311d2_an400_4g.dts +++ b/arch/arm64/boot/dts/amlogic/t7c_a311d2_an400_4g.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "mesont7c.dtsi" +#include "mesont7c_drm.dtsi" #include "partition_mbox_ab.dtsi" #include #include "mesont7_an400-panel.dtsi" @@ -1630,7 +1631,7 @@ }; &fb { - status = "okay"; + status = "disabled"; display_size_default = <3840 2160 3840 4320 32>; mem_size = <0x00800000 0x4000000 0x100000 0x100000 0x100000>; 4k2k_fb = <1>; @@ -1640,6 +1641,61 @@ pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ }; +&drm_vpu { + status = "okay"; + logo_addr = "0x3f800000"; + + connectors_dev: port@1 { + drm_to_lcd0: endpoint@2 { + reg = <2>; + remote-endpoint = <&lcd0_to_drm>; + }; + drm_to_lcd1: endpoint@3 { + reg = <3>; + remote-endpoint = <&lcd1_to_drm>; + }; + drm_to_lcd2: endpoint@4 { + reg = <4>; + remote-endpoint = <&lcd2_to_drm>; + }; + }; +}; + +&lcd { + ports { + port { + #address-cells = <1>; + #size-cells = <0>; + lcd0_to_drm: endpoint@0 { + reg = <0>; + remote-endpoint = <&drm_to_lcd0>; + }; + }; + }; +}; + +&lcd1 { + ports { + port { + lcd1_to_drm: endpoint@0 { + reg = <0>; + remote-endpoint = <&drm_to_lcd1>; + }; + }; + }; +}; + +&lcd2 { + ports { + port { + lcd2_to_drm: endpoint@0 { + reg = <0>; + remote-endpoint = <&drm_to_lcd2>; + }; + }; + }; +}; + &amvideom { display_device_cnt = <2>; vpp0_layer_count = <2>;