From e4e5d4a5f88b3d23db76d800379aa9b03dcaedbe Mon Sep 17 00:00:00 2001 From: "congyang.huang" Date: Wed, 1 Nov 2023 19:59:24 +0800 Subject: [PATCH] drm: add osd security support [1/1] PD#SWPL-142625 Problem: Some chips that support security func have not added security func Solution: Add osd security func for all chips Verify: sc2 Test: DRM-OSD-110 Change-Id: If29741bfd9b4baee583922c9da023559426d1e45 Signed-off-by: congyang.huang --- drivers/drm/vpu-hw/meson_osd_afbc.c | 6 ++++++ drivers/drm/vpu-hw/meson_vpu_osd_mif.c | 24 ++++++++++++++++-------- drivers/drm/vpu-hw/meson_vpu_postblend.c | 9 +++++++++ 3 files changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/drm/vpu-hw/meson_osd_afbc.c b/drivers/drm/vpu-hw/meson_osd_afbc.c index 4656ad423..e4be3bf78 100644 --- a/drivers/drm/vpu-hw/meson_osd_afbc.c +++ b/drivers/drm/vpu-hw/meson_osd_afbc.c @@ -1093,6 +1093,9 @@ static void s5_osd_afbc_set_state(struct meson_vpu_block *vblk, afbc_reg = &afbc->afbc_regs[osd_index]; plane_info = &mvps->plane_info[osd_index]; + if (mvps->sec_src) + mvps->sec_src |= MALI_AFBCD_SECURE; + t7_osd_afbc_enable(vblk, reg_ops, afbc_stat_reg, osd_index, 1); aligned_32 = 1; @@ -1279,6 +1282,9 @@ static void t3x_osd_afbc_set_state(struct meson_vpu_block *vblk, afbc_reg = &afbc->afbc_regs[osd_index]; plane_info = &mvps->plane_info[osd_index]; + if (mvps->sec_src) + mvps->sec_src |= MALI_AFBCD_SECURE; + t7_osd_afbc_enable(vblk, reg_ops, afbc_stat_reg, osd_index, 1); aligned_32 = 1; diff --git a/drivers/drm/vpu-hw/meson_vpu_osd_mif.c b/drivers/drm/vpu-hw/meson_vpu_osd_mif.c index 24826e97c..57a45387b 100644 --- a/drivers/drm/vpu-hw/meson_vpu_osd_mif.c +++ b/drivers/drm/vpu-hw/meson_vpu_osd_mif.c @@ -315,7 +315,7 @@ static struct osd_mif_reg_s s5_osd_mif_reg[HW_OSD_MIF_NUM] = { static unsigned int osd_canvas[4][2]; static u32 osd_canvas_index[4] = {0, 0, 0, 0}; static u32 osd_secure_input_index[] = {OSD1_INPUT_SECURE, - OSD2_INPUT_SECURE, OSD3_INPUT_SECURE}; + OSD2_INPUT_SECURE, OSD3_INPUT_SECURE, OSD4_INPUT_SECURE}; /* * Internal function to query information for a given format. See @@ -1570,19 +1570,14 @@ static void osd_dump_register(struct drm_printer *p, struct meson_vpu_block *vbl "DIMM_CTRL", reg_addr, value); } -#ifndef CONFIG_AMLOGIC_ZAPPER_CUT #ifdef CONFIG_AMLOGIC_MEDIA_SECURITY static void osd_secure_cb(u32 arg) { // TODO } -#endif -#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY - void *osd_secure_op[VPP_TOP_MAX] = {meson_vpu_write_reg_bits, - meson_vpu1_write_reg_bits, - meson_vpu2_write_reg_bits}; -#endif +void *osd_secure_op[VPP_TOP_MAX] = {meson_vpu_write_reg_bits, + meson_vpu1_write_reg_bits, meson_vpu2_write_reg_bits}; #endif static void osd_hw_init(struct meson_vpu_block *vblk) @@ -1607,6 +1602,10 @@ static void osd_hw_init(struct meson_vpu_block *vblk) //osd_ctrl_init(vblk, pipeline->subs[0].reg_ops, osd->reg); osd->mif_acc_mode = CANVAS_MODE; +#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY + secure_register(OSD_MODULE, 0, osd_secure_op, osd_secure_cb); +#endif + MESON_DRM_BLOCK("%s hw_init done.\n", osd->base.name); } @@ -1680,6 +1679,11 @@ static void g12b_osd_hw_init(struct meson_vpu_block *vblk) DRM_INFO("%s hw_init end for %s, index:%d.\n", __func__, osd->base.name, vblk->index); } + +#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY + secure_register(OSD_MODULE, 0, osd_secure_op, osd_secure_cb); +#endif + MESON_DRM_BLOCK("%s hw_init done.\n", osd->base.name); } @@ -1736,6 +1740,10 @@ static void s5_osd_hw_init(struct meson_vpu_block *vblk) original_osd1_fifo_ctrl_stat_t3x = pipeline->subs[0].reg_ops->rdma_read_reg(osd->reg->viu_osd_fifo_ctrl_stat); +#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY + secure_register(OSD_MODULE, 0, osd_secure_op, osd_secure_cb); +#endif + MESON_DRM_BLOCK("%s hw_init done.\n", osd->base.name); } #endif diff --git a/drivers/drm/vpu-hw/meson_vpu_postblend.c b/drivers/drm/vpu-hw/meson_vpu_postblend.c index 0dbe06a11..7b4a773ab 100644 --- a/drivers/drm/vpu-hw/meson_vpu_postblend.c +++ b/drivers/drm/vpu-hw/meson_vpu_postblend.c @@ -592,6 +592,10 @@ static void s5_postblend_set_state(struct meson_vpu_block *vblk, scope.v_end = mvsps->blend_dout_vsize[0] - 1; } +#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY + secure_config(OSD_MODULE, mvps->sec_src, crtc_index); +#endif + vpp_osd1_blend_scope_set(vblk, reg_ops, reg, scope); if (amc->blank_enable) { @@ -631,6 +635,11 @@ static void t3x_postblend_set_state(struct meson_vpu_block *vblk, MESON_DRM_BLOCK("%s set_state called.\n", postblend->base.name); mvps = priv_to_pipeline_state(pipeline->obj.state); mvsps = &mvps->sub_states[0]; + +#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY + secure_config(OSD_MODULE, mvps->sec_src, crtc_index); +#endif + if (crtc_index == 0) { scope.h_start = 0; scope.v_start = 0;