From e9f2ca5dc20aa9013908e62ce7f26efb113eb785 Mon Sep 17 00:00:00 2001 From: "hai.cao" Date: Sun, 4 Jun 2023 12:09:39 +0800 Subject: [PATCH] video: can not dump whole regs [1/1] PD#SWPL-125823 Problem: can not dump whole regs sr and pps open together will error Solution: remove if it not support vd2 Verify: TXHD2 Change-Id: Ie3b29b474a3e7e91ce392eb04480086a1b4a847c Signed-off-by: hai.cao --- drivers/media/video_sink/video.c | 4 +- drivers/media/video_sink/video_common.c | 455 +++++++++++++----------- drivers/media/video_sink/video_hw.c | 2 + drivers/media/video_sink/video_priv.h | 2 + 4 files changed, 254 insertions(+), 209 deletions(-) diff --git a/drivers/media/video_sink/video.c b/drivers/media/video_sink/video.c index 208f6a984..bd09fae04 100644 --- a/drivers/media/video_sink/video.c +++ b/drivers/media/video_sink/video.c @@ -14050,11 +14050,11 @@ static struct amvideo_device_data_s amvideo_txhd2 = { .dv_support = 0, .sr0_support = 1, .sr1_support = 0, - .core_v_disable_width_max[0] = 1024, + .core_v_disable_width_max[0] = 2048, .core_v_disable_width_max[1] = 2048, .core_v_enable_width_max[0] = 1024, .core_v_enable_width_max[1] = 1024, - .supscl_path = PPS_CORE1_CM, + .supscl_path = CORE0_BEFORE_PPS, .fgrain_support[0] = 0, .fgrain_support[1] = 0, .fgrain_support[2] = 0, diff --git a/drivers/media/video_sink/video_common.c b/drivers/media/video_sink/video_common.c index b6ab439af..22bae35fb 100644 --- a/drivers/media/video_sink/video_common.c +++ b/drivers/media/video_sink/video_common.c @@ -907,231 +907,272 @@ static void dump_vpp_path_size_reg(void) { u32 reg_addr, reg_val = 0; - if (cur_dev->display_module == OLD_DISPLAY_MODULE) + if (legacy_vpp) return; pr_info("vpp path size reg:\n"); - reg_addr = vpp_path_size_reg.vd1_hdr_in_size; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd1_hdr_in_size[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vd2_hdr_in_size; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd2_hdr_in_size[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vd3_hdr_in_size; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd3_hdr_in_size[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vpp_line_in_length; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vpp_line_in_length[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vpp_pic_in_height; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vpp_pic_in_height[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vd1_sc_h_startp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd1_sc_h_startp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vd1_sc_h_endp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd1_sc_h_endp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vd1_sc_v_startp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd1_sc_v_startp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vd1_sc_v_endp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd1_sc_v_endp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vd2_sc_h_startp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd2_sc_h_startp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vd2_sc_h_endp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd2_sc_h_endp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vd2_sc_v_startp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd2_sc_v_startp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vd2_sc_v_endp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd2_sc_v_endp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vd3_sc_h_startp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd3_sc_h_startp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vd3_sc_h_endp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd3_sc_h_endp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vd3_sc_v_startp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd3_sc_v_startp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vd3_sc_v_endp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd3_sc_v_endp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.schn_sc_h_startp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("schn_sc_h_startp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.schn_sc_h_endp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("schn_sc_h_endp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.schn_sc_v_startp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("schn_sc_v_startp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.schn_sc_v_endp; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("schn_sc_v_endp[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.sr0_in_size; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("sr0_in_size[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.sr1_in_size; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("sr1_in_size[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.aisr_post_size; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("aisr_post_size[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vpp_preblend_h_size; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vpp_preblend_h_size[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.preblend_vd1_h_start_end; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("preblend_vd1_h_start_end[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.preblend_vd1_v_start_end; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("preblend_vd1_v_start_end[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vpp_ve_h_v_size; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vpp_ve_h_v_size[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vpp_postblend_h_size; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vpp_postblend_h_size[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.vpp_out_h_v_size; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vpp_out_h_v_size[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.postblend_vd1_h_start_end; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("postblend_vd1_h_start_end[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.postlend_vd1_v_start_end; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("postlend_vd1_v_start_end[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.blend_vd2_h_start_end; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("blend_vd2_h_start_end[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.blend_vd2_v_start_end; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("blend_vd2_v_start_end[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.blend_vd3_h_start_end; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("blend_vd3_h_start_end[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = vpp_path_size_reg.blend_vd3_v_start_end; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("blend_vd3_v_start_end[0x%x] = 0x%X\n", - reg_addr, reg_val); + if (glayer_info[0].layer_support) { + reg_addr = vpp_path_size_reg.vd1_hdr_in_size; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd1_hdr_in_size[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vpp_line_in_length; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vpp_line_in_length[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vpp_pic_in_height; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vpp_pic_in_height[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd1_sc_h_startp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd1_sc_h_startp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd1_sc_h_endp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd1_sc_h_endp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd1_sc_v_startp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd1_sc_v_startp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd1_sc_v_endp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd1_sc_v_endp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vpp_line_in_length; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vpp_line_in_length[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vpp_pic_in_height; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vpp_pic_in_height[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd1_sc_h_startp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd1_sc_h_startp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd1_sc_h_endp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd1_sc_h_endp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd1_sc_v_startp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd1_sc_v_startp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd1_sc_v_endp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd1_sc_v_endp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.schn_sc_h_startp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("schn_sc_h_startp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.schn_sc_h_endp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("schn_sc_h_endp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.schn_sc_v_startp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("schn_sc_v_startp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.schn_sc_v_endp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("schn_sc_v_endp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vpp_preblend_h_size; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vpp_preblend_h_size[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.preblend_vd1_h_start_end; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("preblend_vd1_h_start_end[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.preblend_vd1_v_start_end; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("preblend_vd1_v_start_end[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vpp_ve_h_v_size; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vpp_ve_h_v_size[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vpp_postblend_h_size; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vpp_postblend_h_size[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vpp_out_h_v_size; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vpp_out_h_v_size[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.postblend_vd1_h_start_end; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("postblend_vd1_h_start_end[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.postlend_vd1_v_start_end; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("postlend_vd1_v_start_end[0x%x] = 0x%X\n", + reg_addr, reg_val); + } else if (glayer_info[1].layer_support) { + reg_addr = vpp_path_size_reg.vd2_hdr_in_size; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd2_hdr_in_size[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd2_sc_h_startp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd2_sc_h_startp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd2_sc_h_endp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd2_sc_h_endp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd2_sc_v_startp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd2_sc_v_startp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd2_sc_v_endp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd2_sc_v_endp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.blend_vd2_h_start_end; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("blend_vd2_h_start_end[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.blend_vd2_v_start_end; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("blend_vd2_v_start_end[0x%x] = 0x%X\n", + reg_addr, reg_val); + } else if (glayer_info[2].layer_support) { + reg_addr = vpp_path_size_reg.vd3_hdr_in_size; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd3_hdr_in_size[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd3_sc_h_startp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd3_sc_h_startp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd3_sc_h_endp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd3_sc_h_endp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd3_sc_v_startp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd3_sc_v_startp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.vd3_sc_v_endp; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd3_sc_v_endp[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.blend_vd3_h_start_end; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("blend_vd3_h_start_end[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = vpp_path_size_reg.blend_vd3_v_start_end; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("blend_vd3_v_start_end[0x%x] = 0x%X\n", + reg_addr, reg_val); + } + if (cur_dev->sr0_support) { + reg_addr = vpp_path_size_reg.sr0_in_size; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("sr0_in_size[0x%x] = 0x%X\n", + reg_addr, reg_val); + } else if (cur_dev->sr1_support) { + reg_addr = vpp_path_size_reg.sr1_in_size; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("sr1_in_size[0x%x] = 0x%X\n", + reg_addr, reg_val); + } + if (cur_dev->aisr_support) { + reg_addr = vpp_path_size_reg.aisr_post_size; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("aisr_post_size[0x%x] = 0x%X\n", + reg_addr, reg_val); + } } static void dump_vpp_misc_reg(void) { u32 reg_addr, reg_val = 0; - if (cur_dev->display_module == OLD_DISPLAY_MODULE) + if (legacy_vpp) return; pr_info("vpp misc reg:\n"); - reg_addr = viu_misc_reg.mali_afbcd_top_ctrl; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("mali_afbcd_top_ctrl[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = viu_misc_reg.mali_afbcd1_top_ctrl; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("mali_afbcd1_top_ctrl[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = viu_misc_reg.mali_afbcd2_top_ctrl; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("mali_afbcd2_top_ctrl[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = viu_misc_reg.vpp_vd1_top_ctrl; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vpp_vd1_top_ctrl[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = viu_misc_reg.vpp_vd2_top_ctrl; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vpp_vd2_top_ctrl[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = viu_misc_reg.vpp_vd3_top_ctrl; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vpp_vd3_top_ctrl[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = viu_misc_reg.vd_path_misc_ctrl; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vd_path_misc_ctrl[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = viu_misc_reg.path_start_sel; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("path_start_sel[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = viu_misc_reg.vpp_misc; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vpp_misc[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = viu_misc_reg.vpp_misc1; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("vpp_misc1[0x%x] = 0x%X\n", - reg_addr, reg_val); + if (glayer_info[0].layer_support) { + reg_addr = viu_misc_reg.mali_afbcd_top_ctrl; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("mali_afbcd_top_ctrl[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = viu_misc_reg.mali_afbcd1_top_ctrl; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("mali_afbcd1_top_ctrl[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = viu_misc_reg.mali_afbcd2_top_ctrl; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("mali_afbcd2_top_ctrl[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = viu_misc_reg.vpp_vd1_top_ctrl; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vpp_vd1_top_ctrl[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = viu_misc_reg.vd_path_misc_ctrl; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vd_path_misc_ctrl[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = viu_misc_reg.path_start_sel; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("path_start_sel[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = viu_misc_reg.vpp_misc; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vpp_misc[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = viu_misc_reg.vpp_misc1; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vpp_misc1[0x%x] = 0x%X\n", + reg_addr, reg_val); + } else if (glayer_info[1].layer_support) { + reg_addr = viu_misc_reg.vpp_vd2_top_ctrl; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vpp_vd2_top_ctrl[0x%x] = 0x%X\n", + reg_addr, reg_val); + } else if (glayer_info[2].layer_support) { + reg_addr = viu_misc_reg.vpp_vd3_top_ctrl; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("vpp_vd3_top_ctrl[0x%x] = 0x%X\n", + reg_addr, reg_val); + } } static void dump_zorder_reg(void) { u32 reg_addr, reg_val = 0; - if (cur_dev->display_module == OLD_DISPLAY_MODULE) + if (legacy_vpp) return; pr_info("vpp zorder reg:\n"); - reg_addr = VD1_BLEND_SRC_CTRL; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("VD1_BLEND_SRC_CTRL[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = VD2_BLEND_SRC_CTRL; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("VD2_BLEND_SRC_CTRL[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = VD3_BLEND_SRC_CTRL; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("VD3_BLEND_SRC_CTRL[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = OSD1_BLEND_SRC_CTRL; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("OSD1_BLEND_SRC_CTRL[0x%x] = 0x%X\n", - reg_addr, reg_val); - reg_addr = OSD2_BLEND_SRC_CTRL; - reg_val = READ_VCBUS_REG(reg_addr); - pr_info("OSD2_BLEND_SRC_CTRL[0x%x] = 0x%X\n", - reg_addr, reg_val); + if (glayer_info[0].layer_support) { + reg_addr = VD1_BLEND_SRC_CTRL; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("VD1_BLEND_SRC_CTRL[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = OSD1_BLEND_SRC_CTRL; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("OSD1_BLEND_SRC_CTRL[0x%x] = 0x%X\n", + reg_addr, reg_val); + reg_addr = OSD2_BLEND_SRC_CTRL; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("OSD2_BLEND_SRC_CTRL[0x%x] = 0x%X\n", + reg_addr, reg_val); + } else if (glayer_info[1].layer_support) { + reg_addr = VD2_BLEND_SRC_CTRL; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("VD2_BLEND_SRC_CTRL[0x%x] = 0x%X\n", + reg_addr, reg_val); + } else if (glayer_info[2].layer_support) { + reg_addr = VD3_BLEND_SRC_CTRL; + reg_val = READ_VCBUS_REG(reg_addr); + pr_info("VD3_BLEND_SRC_CTRL[0x%x] = 0x%X\n", + reg_addr, reg_val); + } } static void dump_vppx_blend_reg(void) diff --git a/drivers/media/video_sink/video_hw.c b/drivers/media/video_sink/video_hw.c index dee67adfc..773482ca6 100644 --- a/drivers/media/video_sink/video_hw.c +++ b/drivers/media/video_sink/video_hw.c @@ -13525,6 +13525,8 @@ int video_early_init(struct amvideo_device_data_s *p_amvideo) vd_layer[0].dummy_alpha = 0x7fffffff; cur_dev->has_vpp1 = p_amvideo->has_vpp1; cur_dev->has_vpp2 = p_amvideo->has_vpp2; + cur_dev->sr0_support = p_amvideo->sr0_support; + cur_dev->sr1_support = p_amvideo->sr1_support; cur_dev->is_tv_panel = p_amvideo->is_tv_panel; cur_dev->mif_linear = p_amvideo->mif_linear; cur_dev->display_module = p_amvideo->display_module; diff --git a/drivers/media/video_sink/video_priv.h b/drivers/media/video_sink/video_priv.h index 23f8f2f40..b5d02b21a 100644 --- a/drivers/media/video_sink/video_priv.h +++ b/drivers/media/video_sink/video_priv.h @@ -278,6 +278,8 @@ struct video_dev_s { struct vpp_frame_par_s aisr_frame_parms; struct rdma_fun_s rdma_func[RDMA_INTERFACE_NUM]; u32 sr_in_size; + u8 sr0_support; + u8 sr1_support; u8 is_tv_panel; u8 prevsync_support; u8 pre_vsync_enable;