diff --git a/arch/arm64/boot/dts/amlogic/mesont6x.dtsi b/arch/arm64/boot/dts/amlogic/mesont6x.dtsi
index 73bdd8102..a76a4e566 100644
--- a/arch/arm64/boot/dts/amlogic/mesont6x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesont6x.dtsi
@@ -1200,19 +1200,21 @@
 				<&clkc CLKID_VAPB>,
 				<&clkc CLKID_VPU_0>,
 				<&clkc CLKID_VPU_1>,
-				<&clkc CLKID_VPU>;
+				<&clkc CLKID_VPU>,
+				<&clkc CLKID_GP1_PLL>;
 			clock-names =   "vapb_clk0",
 					"vapb_clk1",
 					"vapb_clk",
 					"vpu_clk0",
 					"vpu_clk1",
-					"vpu_clk";
+					"vpu_clk",
+					"gp_pll";
 			overclock_sel = <2>;
 			/* 0: force disable 1:force enable 2: adaptable */
-			clk_level = <10>;
+			clk_level = <9>;
 			/* 0: 24.0M  1: 100.0M    2: 166.7M    3: 200.0M    4: 250.0M */
 			/* 5: 333.3M    6: 400.0M    7: 500.0M    8: 666.7M  9: 800.0M*/
-			/* 10: 840M     11: 808M*/
+			/* 10: 840M     11: 808M  12:744M     13:888M*/
 		};
 
 		/*if you want to use vdin just modify status to "ok"*/
diff --git a/drivers/media/common/vpu/vpu.c b/drivers/media/common/vpu/vpu.c
index 1618112fc..47ef9091e 100644
--- a/drivers/media/common/vpu/vpu.c
+++ b/drivers/media/common/vpu/vpu.c
@@ -300,8 +300,8 @@ unsigned int rx_switch_vpu_clk(int over_clock_flag)
 	int vdin_status;
 	unsigned long new_freq;
 
-	if (vpu_conf.data->chip_type == VPU_CHIP_T6X) {
-		VPUPR("%s %d over_clock_flag:%d\n", __func__, __LINE__, over_clock_flag);
+	if (vpu_conf.data->chip_type == VPU_CHIP_T6X && vpu_conf.vpu_overclock == 2) {
+		VPUPR("over_clock_flag:%d\n", over_clock_flag);
 		if (vpu_conf.overclock_sel == 0) {
 			clk_level = 10;
 		} else if (vpu_conf.overclock_sel == 1) {
@@ -318,20 +318,19 @@ unsigned int rx_switch_vpu_clk(int over_clock_flag)
 				}
 			}
 		} else {
-			VPUERR("%s unknown overclock_sel:%d\n", __func__, vpu_conf.overclock_sel);
+			VPUERR("unknown overclock_sel:%d\n", vpu_conf.overclock_sel);
 		}
 
 		if (clk_level != vpu_conf.clk_level) {
 			new_freq = get_vpu_clk_freq(clk_level);
 			vpu_clk_info.new_freq = new_freq;
-			if (new_freq == 892000000) {
+			if (new_freq == 888000000) {
 				vd_signal_notifier_call_chain(VIDEO_VPU_CLK_CHANGED,
 								  &vpu_clk_info);
 				/* vdin_status 0:idle 1:vdin 0 worked 2:vdin1 worked */
 				vdin_status = get_vdin_status(1);
 				if (vdin_status || vpu_debug_print_flag)
-					VPUPR("%s, vdin_status:%d\n",
-						  __func__, vdin_status);
+					VPUPR("vdin_status:%d\n", vdin_status);
 				set_vpu_clk(clk_level);
 			} else if (new_freq == 840000000) {
 				set_vpu_clk(clk_level);
@@ -852,7 +851,12 @@ static void set_vpu_overclk(void)
 	if (vpu_conf.data->chip_type == VPU_CHIP_T6X) {
 		vpu_max_freq = efuse_amlogic_cali_item_read(EFUSE_CALI_SUBITEM_VPU_MAXFREQ);
 		VPUPR("%s vpu support max freq: %d\n", __func__, vpu_max_freq);
-		vpu_conf.vpu_overclock = (vpu_max_freq == 180) ? 1 : 0;
+		if (vpu_max_freq == 170)
+			vpu_conf.vpu_overclock = 1;
+		else if (vpu_max_freq == 180)
+			vpu_conf.vpu_overclock = 2;
+		else
+			vpu_conf.vpu_overclock = 0;
 	}
 }
 
@@ -1643,6 +1647,13 @@ static ssize_t vpu_debug_print_store(const struct class *class,
 	return count;
 }
 
+static ssize_t vpu_overclock_show(const struct class *class,
+				  const struct class_attribute *attr, char *buf)
+{
+	return sprintf(buf, "vpu overclock: %d\n",
+		vpu_conf.vpu_overclock);
+}
+
 static ssize_t vpu_arb_bind_store(const struct class *class,
 				     const struct class_attribute *attr,
 				     const char *buf, size_t count)
@@ -1917,6 +1928,7 @@ static struct class_attribute vpu_debug_class_attrs[] = {
 	__ATTR(sideband_level, 0644, vpu_sideband_level_show, vpu_sideband_level_store),
 	__ATTR(sideband_block_device, 0644, vpu_sideband_block_device_show,
 		vpu_sideband_block_device_store),
+	__ATTR(overclock,   0444, vpu_overclock_show, NULL),
 	__ATTR(help,        0444, vpu_debug_help, NULL),
 };
 
@@ -1976,6 +1988,9 @@ static int get_vpu_config(struct platform_device *pdev)
 			val = vpu_conf.data->clk_level_dft;
 		}
 
+		if (vpu_conf.data->chip_type == VPU_CHIP_T6X &&
+			vpu_conf.vpu_overclock)
+			val = 10;
 		vpu_conf.clk_level = val;
 	}
 	VPUPR("load vpu_clk: %uHz(%u)\n",
@@ -3216,7 +3231,7 @@ static struct vpu_data_s vpu_data_t6x = {
 	.power_init_check = vpu_power_init_check_dft,
 	.mempd_switch = vpu_vmod_mem_pd_switch_new,
 	.mempd_get = vpu_vmod_mem_pd_get_new,
-	.clk_apply = vpu_clk_apply_dft,
+	.clk_apply = vpu_clk_apply_t6x,
 	.clktree_init = vpu_clktree_init_dft,
 };
 
diff --git a/drivers/media/common/vpu/vpu.h b/drivers/media/common/vpu/vpu.h
index fed1f4e33..29450c6c7 100644
--- a/drivers/media/common/vpu/vpu.h
+++ b/drivers/media/common/vpu/vpu.h
@@ -204,6 +204,7 @@ unsigned long get_vpu_clk_freq(unsigned int clk_level);
 unsigned int get_vpu_clk_level_max_vmod(void);
 unsigned int get_vpu_clk_level_from_venc(unsigned int venc_clk);
 int vpu_clk_apply_dft(unsigned int clk_level);
+int vpu_clk_apply_t6x(unsigned int clk_level);
 int vpu_clk_apply_c3(unsigned int clk_level);
 int set_vpu_clk(unsigned int vclk);
 void vpu_clktree_init_dft(struct device *dev);
diff --git a/drivers/media/common/vpu/vpu_clk.c b/drivers/media/common/vpu/vpu_clk.c
index 656c90824..3c768df1f 100644
--- a/drivers/media/common/vpu/vpu_clk.c
+++ b/drivers/media/common/vpu/vpu_clk.c
@@ -359,6 +359,69 @@ int vpu_clk_apply_dft(unsigned int clk_level)
 	return ret;
 }
 
+int vpu_clk_apply_t6x(unsigned int clk_level)
+{
+	unsigned int clk;
+	int ret = 0;
+
+	ret = vpu_chip_valid_check();
+	if (ret) {
+		ret = 1;
+		goto error_out;
+	}
+
+	if (vpu_conf.data->clk_table[clk_level].mux == FCLK_DIV_MAX) {
+		ret = 2;
+		goto error_out;
+	}
+
+	if (IS_ERR_OR_NULL(vpu_conf.vpu_clk)) {
+		ret = 3;
+		goto error_out;
+	}
+
+	if (vpu_conf.data->chip_type == VPU_CHIP_T6X) {
+		if (IS_ERR_OR_NULL(vpu_conf.gp_pll)) {
+			ret = 4;
+			goto error_out;
+		}
+		/* step 1:  set vpu clk 800M */
+		if (clk_level == 10 || clk_level == 13) {
+			clk = vpu_conf.data->clk_table[vpu_conf.data->clk_level_dft].freq;
+			ret = clk_set_rate(vpu_conf.vpu_clk, clk);
+			if (ret) {
+				ret = 5;
+				goto error_out;
+			}
+		}
+
+		/* step 2:  set gpl pll clk */
+		if (clk_level == 10)
+			ret = clk_set_rate(vpu_conf.gp_pll, 1680000000);
+		else if (clk_level == 13)
+			ret = clk_set_rate(vpu_conf.gp_pll, 1776000000);
+		if (ret) {
+			ret = 6;
+			goto error_out;
+		}
+	}
+	clk = vpu_conf.data->clk_table[clk_level].freq;
+	ret = clk_set_rate(vpu_conf.vpu_clk, clk);
+	if (ret) {
+		ret = 7;
+		goto error_out;
+	}
+	clk = clk_get_rate(vpu_conf.vpu_clk);
+	VPUPR("set vpu clk: %uHz(%d), readback: %uHz(0x%x)\n",
+	      vpu_conf.data->clk_table[clk_level].freq, clk_level,
+	      clk, (vpu_clk_read(vpu_conf.data->vpu_clk_reg)));
+
+	return 0;
+error_out:
+	VPUERR("change vpu clk fail, ret = %d\n", ret);
+	return ret;
+}
+
 int vpu_clk_apply_c3(unsigned int clk_level)
 {
 	unsigned int clk;
diff --git a/drivers/media/common/vpu/vpu_ctrl.h b/drivers/media/common/vpu/vpu_ctrl.h
index 803ab3593..1c5a6a3fd 100644
--- a/drivers/media/common/vpu/vpu_ctrl.h
+++ b/drivers/media/common/vpu/vpu_ctrl.h
@@ -45,8 +45,8 @@
 #define CLK_LEVEL_DFT_T6W    10
 #define CLK_LEVEL_MAX_T6W    12
 
-#define CLK_LEVEL_DFT_T6X    10
-#define CLK_LEVEL_MAX_T6X    14
+#define CLK_LEVEL_DFT_T6X    9
+#define CLK_LEVEL_MAX_T6X    15
 
 #ifndef CONFIG_AMLOGIC_C3_REMOVE
 /* vpu clk setting */
@@ -124,7 +124,7 @@ static struct vpu_clk_s vpu_t6w_clk_table[] = {
 	{840000000,    GPLL_CLK1,    1}, /* 10 */ /* for t6w gp1 div gp1 1680 to 840M*/
 	{808000000,    GPLL_CLK2,    0}, /* 11 */ /* for t6w gp2 808M*/
 	{744000000,    GPLL_CLK,     0}, /* 12 */
-	{892000000,    GPLL_CLK2,    0}, /* 13 */ /* for t6x gp2 892M*/
+	{888000000,    GPLL_CLK1,    1}, /* 13 */ /* for t6x gp1 888M*/
 };
 #endif
 #endif