From f3cf68f448865ebbbee45f17bae7d4fe4fb53528 Mon Sep 17 00:00:00 2001 From: Zhuo Wang Date: Tue, 9 Jan 2024 16:00:16 +0800 Subject: [PATCH] eth: s7 bringup [1/1] PD#SWPL-152416 Problem: s7 bringup Solution: s7 bringup Verify: S905Y5-BH201_REF#023 Change-Id: Ib12ad0a5fbcb36d3e4c747f742a19a5267e96eaa Signed-off-by: Zhuo Wang --- arch/arm64/boot/dts/amlogic/meson-s7.dtsi | 41 ++++++++++--------- .../boot/dts/amlogic/s7_s905y5_bh201.dts | 3 +- .../boot/dts/amlogic/s7_s905y5_bh202.dts | 3 +- .../boot/dts/amlogic/s7_s905y5_bh209.dts | 3 +- drivers/net/mdio/mdio-mux-meson-g12a.c | 10 +++++ 5 files changed, 34 insertions(+), 26 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-s7.dtsi b/arch/arm64/boot/dts/amlogic/meson-s7.dtsi index 4c8c27267..3b9af2983 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s7.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s7.dtsi @@ -1125,18 +1125,20 @@ support-sysrq = <0>; /* 0 not support*/ }; - eth_phy: mdio-multiplexer@28000 { + eth_phy: mdio-multiplexer@360000 { compatible = "amlogic,g12a-mdio-mux"; - reg = <0x0 0x28000 0x0 0xa4>; - status = "disabled"; - //clocks = <&clkc CLKID_ETHPHY>, - // <&xtal>, - // <&clkc CLKID_MPLL_50M>; - //clock-names = "pclk", "clkin0", "clkin1"; + reg = <0x0 0x360000 0x0 0xa4>; + + clocks = <&clkc CLKID_SYS_ETHPHY>, + <&xtal>, + <&clkc CLKID_FCLK_CLK50M>; + clock-names = "pclk", "clkin0", "clkin1"; mdio-parent-bus = <&mdio0>; #address-cells = <1>; #size-cells = <0>; enet_type = <5>; + phy_pll_mode = <2>; + phy_mode = <3>; tx_amp_src = <0xFE010330>; ext_mdio: mdio@0 { @@ -1499,23 +1501,22 @@ nand_clk_ctrl = <0xfe08c000>; }; - ethmac: ethernet@fdc00000 { + ethmac: ethernet@fe368000 { compatible = "amlogic,meson-axg-dwmac", - "snps,dwmac-3.70a", - "snps,dwmac"; - reg = <0x0 0xfdc00000 0x0 0x10000>, - <0x0 0xfe024000 0x0 0x8>; + "snps,dwmac-4.00"; + reg = <0x0 0xfe368000 0x0 0x12ec>, + <0x0 0xfe364000 0x0 0x8>; interrupts = ; interrupt-names = "macirq"; - //power-domains = <&pwrdm PDID_S4_ETH>; - //clocks = <&clkc CLKID_ETH>, - // <&clkc CLKID_FCLK_DIV2>, - // <&clkc CLKID_MPLL2>; - //clock-names = "stmmaceth", "clkin0", "clkin1"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; + clocks = <&clkc CLKID_SYS_ETHPHY>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_CLK50M>; + clock-names = "stmmaceth", "clkin0", "clkin1"; +// mboxes = <&mbox_fifo S1A_REE2AO_ETH>; + snps,force_thresh_dma_mode; status = "disabled"; - + analog_version = <1>; + mc_val = <0x180c>; mdio0: mdio { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/amlogic/s7_s905y5_bh201.dts b/arch/arm64/boot/dts/amlogic/s7_s905y5_bh201.dts index c2b8cdb36..9c3fdc8b8 100644 --- a/arch/arm64/boot/dts/amlogic/s7_s905y5_bh201.dts +++ b/arch/arm64/boot/dts/amlogic/s7_s905y5_bh201.dts @@ -1531,10 +1531,9 @@ }; ðmac { - status = "disabled"; + status = "okay"; phy-handle = <&internal_ephy>; phy-mode = "rmii"; - keep-alive = <1>; }; &ir { diff --git a/arch/arm64/boot/dts/amlogic/s7_s905y5_bh202.dts b/arch/arm64/boot/dts/amlogic/s7_s905y5_bh202.dts index d56a719fe..da221abfd 100644 --- a/arch/arm64/boot/dts/amlogic/s7_s905y5_bh202.dts +++ b/arch/arm64/boot/dts/amlogic/s7_s905y5_bh202.dts @@ -1529,10 +1529,9 @@ }; ðmac { - status = "disabled"; + status = "okay"; phy-handle = <&internal_ephy>; phy-mode = "rmii"; - keep-alive = <1>; }; &ir { diff --git a/arch/arm64/boot/dts/amlogic/s7_s905y5_bh209.dts b/arch/arm64/boot/dts/amlogic/s7_s905y5_bh209.dts index 1bb0210a4..31ad04ae1 100644 --- a/arch/arm64/boot/dts/amlogic/s7_s905y5_bh209.dts +++ b/arch/arm64/boot/dts/amlogic/s7_s905y5_bh209.dts @@ -1531,10 +1531,9 @@ }; ðmac { - status = "disabled"; + status = "okay"; phy-handle = <&internal_ephy>; phy-mode = "rmii"; - keep-alive = <1>; }; &ir { diff --git a/drivers/net/mdio/mdio-mux-meson-g12a.c b/drivers/net/mdio/mdio-mux-meson-g12a.c index a65e4b935..cd88a3346 100644 --- a/drivers/net/mdio/mdio-mux-meson-g12a.c +++ b/drivers/net/mdio/mdio-mux-meson-g12a.c @@ -182,6 +182,16 @@ static int g12a_ephy_pll_init(struct clk_hw *hw) writel(0x508200a0, pll->base + ETH_PLL_CTL0); writel(0x00000110, pll->base + ETH_PLL_CTL2); } + /*s7*/ + if (phy_pll_mode == 2) { + writel(0x00510630, pll->base + ETH_PLL_CTL0); + writel(0x222210a0, pll->base + ETH_PLL_CTL1); + writel(0x00518630, pll->base + ETH_PLL_CTL0); + usleep_range(100, 200); + writel(0x222200a0, pll->base + ETH_PLL_CTL1); + usleep_range(100, 200); + writel(0x00118630, pll->base + ETH_PLL_CTL0); + } #else writel(0x29c0040a, pll->base + ETH_PLL_CTL0);