PD#SWPL-179542
Problem:
dirspi_async is designed for the ldim isr. Unfortunately, the
clk_set_rate and clk_get_rate it calls use a mutex lock, which
will lead to a mutex lock panic.
Solution:
Set spi speed in spi_setup only when controller_data use_dirspi=1
Pre-save the spi speed to avoid calling clk_get_rate
Verify:
t5m
Change-Id: I4fdf9d3be687901a5e8cffa1f838f99551b7d94a
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-174740
Problem:
SPISG driver sets clk rate twice for a transfer, one sets the clk rate
with the spi device max_speed_hz in prepare_message, and the other sets
the clk rate with the transfer speed_hz in one_transfer.
Normally, the subsequent clk rate setting would be ingored if the speed
doesn't change. But if the two speeds are different, it would bring about
the clk_set_rate calling twice, and each calling takes about 2~3 msec.
Solution:
Port from cl-434207
Remove the unnecessary clk rate setting of prepare_message
Verify:
s7 bh201
Change-Id: I655a03f166415a256b35739e898be29ae047082a
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-174740
Problem:
SPISG driver configure the mode/speed/timing etc for a slave device only
once in spi_setup. For multiple slave devices, the earlier configures
are
covered by the last one.
Solution:
Port from cl-431613
Configure the mode/speed/timing etc for a slave device in
prepare_message.
Verify:
s7 bh201
Change-Id: Ie23ec354d9b3026575c5e908ce9900a41ad857e1
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-174740
Problem:
SCLK rate range depends on the parent asssigned in dts;
SCLK rate is imprecise because of only one parent clk rate option;
Speed low than 1MHz unsupported;
Slave configurations achieved by spi_setup are cleared away later by
the controller initialization.
Solution:
Port from cl-431163;
Change to use clk-tree divider;
change controller min_speed_hz from 1MHz to 10000Hz;
Initialize controller configurations before devm_spi_register_master.
Verify:
s7 bh201
Change-Id: I4c6d91ad8381c30ba538c6136ab890e1f8223e6b
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-174740
Problem:
spisg descriptor dma address is 64 bits, but it is defined as
a dma_addr_t, which width is 32 bits in arm32.
Solution:
Port from cl-420129
Change the dma address type with u64.
Verify:
s7_bh201
Change-Id: I263dcd7bd8edf69411b536551d4ad0b4cdcab44d
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-174974
Problem:
ldim require a hw interface dirspi_xfer to run in interrupt handle
Solution:
add a hw interface dirspi_xfer for ldim
Verify:
t5m ay301
Change-Id: I26e1a9890cc45ac0420d15ebea5e0a4bf2f18a56
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-167197
Problem:
don't support ota the new boot layout (BOOT_DISCRETE_BL2)
Solution:
init support
Verify:
AW419-C308L-Socket #20
Change-Id: Ia2d1022f72a73f09f32c89fed4534795b0ecc49c
Signed-off-by: zhikui.cui <zhikui.cui@amlogic.com>
PD#SWPL-169271
Problem:
a label can only be part of a statement and a declaration is not a
statement.
Solution:
fix compile errors.
Verify:
s1a_bg201
Change-Id: I4794aea1816f22ba3b0b0f92b72a4de6e67c7406
Signed-off-by: Bichao Zheng <bichao.zheng@amlogic.com>
PD#SWPL-169271
Problem:
regmap_read() access 4B each time, but the length
of buffer passed from spi core is mismatch.
Solution:
NFC driver use the local variable to fix it.
Verify:
s1a_bg201
Change-Id: Id1377f03f594cbc249f85c8a9ab49ba827f47cf4
Signed-off-by: Liang Yang <liang.yang@amlogic.com>
PD#SWPL-165259
Problem:
1. T5W/T3 do not support SPI_LSB_FIRST.
2. T5W suspend/resume will reset the reg.
3. ldim_pwm_level is 0 when power on.
Solution:
1. ldim software implementation of big-endian
and little-endian data conversion.
2. ldim send mode base on spi controller.
3. When resume ldim_fw reset the reg value again.
4. Set ldim_set_duty_pwm after set pwm pinmux.
Verify:
T5W/T5M
Change-Id: I409c4d378fc972f7f643ee64a6588119e1494e1b
Signed-off-by: zijie.lin <zijie.lin@amlogic.com>
PD#SWPL-156043
Problem:
oob layout not switch when switch ecc.
Solution:
switch oob free layout when switch ecc.
Verify:
S1A
Change-Id: I23de5bf220371723d3adb1b0f7148bc10c02bd60
Signed-off-by: Bichao Zheng <bichao.zheng@amlogic.com>
PD#SWPL-156043
Problem:
need to select ecc mode according to the nand model.
Solution:
1. only MX35LF1G24AD select host ecc.
2. all info page use host ecc
Verify:
S1A
Change-Id: I833f4ca00b2b53c52afc57cca666762aeffc5671
Signed-off-by: Bichao Zheng <bichao.zheng@amlogic.com>
PD#SWPL-149033
Problem:
vsync trig xfer failed after suspend/resume
Solution:
change ldim to tx duty data only without rx;
change spicc to support tx only without rx;
stop dma trig unless spi complete;
reset fifo before start dma trig
Verify:
T5M T963D4_AY301
Change-Id: Icbac15138a3f7f33e1436047cd99a9882aaf2738
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-149033
Problem:
dirspi transferring error after str wake up,
- unexpected sclk rate
- unexpected sclk polarity
- SS pull up every word
Solution:
store/restore all registers when suspend/resume
Verify:
T5M T963D4_AY301, T7 A311D2_AN400
Change-Id: I313f7ad1dfbc38db8e92189f543eac4649f6810f
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-150135
Problem:
an unexpected 2 us sclk negative pulse in spi device setup.
first setup only
Solution:
inconformity between sclk-pullup and default sclk polarity 0.
Verify:
t5m ay301
Change-Id: I99f6889164bed2b1c12b74e1e05cd004c65982be
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-150135
Problem:
dmc violation because of spicc dma reading/writing address.
caused by a error configure for spicc ldim vsync mode
Solution:
set 0x28[8]=1 to load dma address from 0x30/0x34
Verify:
t5m ay301
Change-Id: I09fabbb9490674de1d02b38da0bc2bcb38c74a67
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-147512
Problem:
refactor test entry for spicc & spicc-v2
Solution:
Refactor test entry for spicc & spicc-v2;
Fix chip select issue to support more SPI devices.
Porting from 5.4 f55b06c4
Verify:
t3 t982
Change-Id: I113e3ac4f1926fd98e94ad8cf3cf2aebeeada970
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-147512
Problem:
LDIM requires a strict timing sequence to match with the vsync signal
Solution:
SPICC supports vsync/line-n triggering control, Add a interface to
start/stop the vsync triggering transfer for LDIM
Porting from 5.4 1f62b7d1
Verify:
t3 t982
Change-Id: Ida2f63cbe318dceebbe97514e41a588e4ea143d4
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-145604
Problem:
The cs-gpio pin can possibly be in other mux state, and yet
SPI HAL didn't request it into gpio state before use it.
Solution:
Request its cs-gpio into GPIO state in device setup
Verify:
C308L-AW419
Change-Id: Ie94ff7bda9f0f4fd2512d765e0698a5cea522183
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-140211
Problem:
need update spinand info page.
Solution:
update new info page, for compatibility with A1 S1A C3.
Verify:
A1 S1A C3
Change-Id: I73ce561dc716aedd18ac2887af00fa912818794b
Signed-off-by: Bichao Zheng <bichao.zheng@amlogic.com>
PD#SWPL-133609
Problem:
spicc(v2) clk works in poweroff state
Solution:
disable spicc(v2) clk when poweroff
Verify:
T3X BC309
Change-Id: Ie9c9ffd4ecc450b9a9e7b3f5bd3429c5b095c798
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-137044
Problem:
transfer timed out when spicc works at low speed(200K)
Solution:
TC is triggered by tx-fifo empty, but the last data is not yet transferred
at this time. we have to wait the last data which is sending/receiving.
Verify:
C1
Change-Id: I7e0fca3fdf6ed6c3b40a8399564eae2cf6d3a9b0
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-136205
Problem:
back sync with t5m openliux/tv/s-amlogic
Solution:
- configure spicc1 ss leading/trailing gap for local-dimming;
- add dirspi support in test entry;
- remove the limit of min_speed_hz.
Verify:
t5m
Change-Id: If84e2a5a5cac080f543c18988524da58fabeda0a
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-124874
Problem:
add dirspi interface for new spicc(v2) controller driver
Solution:
1. add dirspi interface for new spicc(v2) controller driver
2. remove dirspi EXPORT_SYMBOL of old spicc driver, replace with
callback APIs from controller_data
Verify:
T3X BC309
Change-Id: I407b5d3dfa7d88bbe834853817666c9234dabe60
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-122937
Problem:
xfer timed out or set clk rate failed on g12 serials,
because of SCLK parent clk missed
Solution:
Assign the async clk as the parent of SCLK
Verify:
t3
Change-Id: I02247d677c17705f4af413f74baf17625fbd8f41
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-115993
Problem:
spicc not work in android r release
Solution:
make spicc platform driver register
successfully in builtin way
Verify:
t5m
Change-Id: I35edfba35e05a13d895b421a98cebcbd07f4ef55
Signed-off-by: Feng Chen <feng.chen@amlogic.com>
Sunny Luo