PD#SWPL-252566
Problem:
after the system boots up, accessing the priority
registers inside the device may cause a panic
Solution:
1. no inside-device priority tuning by default
2. enable/disable priority access for inside devices
such as:
echo vpu p 1 > priority
echo vpu p 0 > priority
Verify:
local
Change-Id: I50a69883af89216a32a689d09c88f15181c4305e
Signed-off-by: Wanwei Jiang <wanwei.jiang@amlogic.com>
PD#SWPL-247872
Problem:
On the T6X board, priorities at all levels can be displayed and configured
Solution:
1. display all levels priorities;
2. configure dmc and device priorities;
3. the priority configuration inside the device requires module owner
support, and it will be gradually improved in the future
Verify:
t6x
Change-Id: Iff7c11ac00b2e359544146b5a73c8080832d3920
Signed-off-by: Wanwei Jiang <wanwei.jiang@amlogic.com>
PD#SWPL-241730
Problem:
too much print info
Solution:
remove unnecessary print info
Verify:
sc2
Change-Id: I1ecb473c3095a1be608336a9047e7beca31121d8
Signed-off-by: biao.sun <biao.sun@amlogic.com>
PD#SWPL-246871
Problem:
set the default sampling freq for DDR bandwidth to 1000 Hz
Solution:
1. rename the file irq_clock to sampling_freq
2. set the default sampling freq for DDR bandwidth to 1000 Hz
Verify:
sc2
Change-Id: I0d07d0fe0b49ed105280d24cb4c19fd5405d0682
Signed-off-by: Wanwei Jiang <wanwei.jiang@amlogic.com>
PD#SWPL-246564
Problem:
add t6x ddr ssr set node
Solution:
add node to user space access ddr ssr reg
Notice, Adding this node means any application can
use this node to modify ssr-related registers,
which can lead to system anomalies,
you need to take that risk and
enable CONFIG_AMLOGIC_DDR_SSR if you use it.
Verify:
t6x
Change-Id: Id43ac3999fda1de9e344a984987bd6ac2c8c4f5e
Signed-off-by: qinglin.li <qinglin.li@amlogic.com>
PD#SWPL-244211
Problem:
optimize interrupt handling time and fix atrace data misalignment
Solution:
optimize interrupt handling time and fix atrace data misalignment
Verify:
t6x
Change-Id: Ie9fdaf0db194ff8856a90004882dd5534bdd6332
Signed-off-by: Wanwei Jiang <wanwei.jiang@amlogic.com>
PD#SWPL-243386
Problem:
sec vio check print subid when sub not parse
Solution:
print subid when sub not parse
Verify:
local
Change-Id: I9292400fb5af535cd0c8210ff921b1fc32925958
Signed-off-by: qinglin.li <qinglin.li@amlogic.com>
PD#SWPL-238820
Problem:
old recheck not check page status
emmc continuous access not ignore
Solution:
recheck add page status check
if recheck access and page status not free ignore it
Verify:
local
Change-Id: I71498711263269c049b73d421e1e672a42348e93
Signed-off-by: qinglin.li <qinglin.li@amlogic.com>
PD#SWPL-237512
Problem:
t6x vpu sud id update
Solution:
t6x vpu sud id update
Verify:
local
Change-Id: I81acc8a88f622daada899580d98973b89177ca14
Signed-off-by: qinglin.li <qinglin.li@amlogic.com>
PD#SWPL-231748
Problem:
use dmc prot buf recheck
Solution:
when device access continuous
recheck can verify invalid when pagetrace is free
the function will be add 5-10us once irq
and check 2-3 continuous access
Verify:
local
Change-Id: I8073b9da2fa881f18540c15f83e72224cb7ffd0f
Signed-off-by: qinglin.li <qinglin.li@amlogic.com>
PD#SWPL-231117
Problem:
common_drivers/drivers/media/common/vpu/vpu_sideband.o: in function `set_vpu_sideband_enable':
(.text+0x82): undefined reference to `disable_side_band'
common_drivers/drivers/media/common/vpu/vpu_sideband.o: in function `dmc_reg_setting':
(.text+0x5d4): undefined reference to `enable_side_band'
Solution:
add depends on for ddr_tool
Verify:
t6x
Change-Id: Ifa6c5e759259018072ba1ba203e7822d879d70b6
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-229258
Problem:
some scenarios hope to dynamically modify the cma task priority.
Solution:
provide interface to set cma task priority.
Verify:
local.
Change-Id: Ic0ce3ef8d58923e8506789864553bde36afba4fe
Signed-off-by: Jianxiong Pan <jianxiong.pan@amlogic.com>
PD#SWPL-228047
Problem:
bandwidth overflow max due to crash
Solution:
multiple dmc need calculate after irq finish
reg data only be clear after irq finish
Verify:
local
Change-Id: I94d02d3ed8f01f62cdcda04482b20b150f8c957b
Signed-off-by: qinglin.li <qinglin.li@amlogic.com>
PD#SWPL-228573
Problem:
bus width auto recognition
Solution:
bus width auto recognition
Verify:
t6d t6x
Change-Id: I5f9fc3684839129882e0ff2dc6c6c0e5fbfbe95f
Signed-off-by: qinglin.li <qinglin.li@amlogic.com>
PD#SWPL-222462
Problem:
CCI will be trigger when alloc before pagetrace set
Solution:
t7 default exclude CCI and filter MALI1
fix cmdline show
Verify:
local
Change-Id: If9d8378c386132407932d11d72c64ab19f6dc823
Signed-off-by: qinglin.li <qinglin.li@amlogic.com>
PD#SWPL-223295
Problem:
dmc not print the function name.
Solution:
update the dmc_unpack_ip code.
Verify:
sc2.
Change-Id: If28612fa05c36f9fde2d79a91b8b5a6e385c39b2
Signed-off-by: Jianxiong Pan <jianxiong.pan@amlogic.com>
PD#SWPL-225004
Problem:
fix large ddr range arm32 build error
Solution:
default addr than 32bit is 0 when arm32 build
Verify:
local
Change-Id: I4716c6d695506918fcb890ae171f26bf1cdabcb3
Signed-off-by: qinglin.li <qinglin.li@amlogic.com>
PD#SWPL-224014
Problem:
virt_addr_valid only return true line addr
Solution:
save name and id point
Verify:
local
Change-Id: I256f8b9ec9c91a052b792bea6e9de9575ad1826a
Signed-off-by: qinglin.li <qinglin.li@amlogic.com>
PD#SWPL-218353
Problem:
other modules are unable to determine how many VPU buses this chip has
Solution:
add get_vpu_bus_num() for sideband
Verify:
local
Change-Id: Iccd1e2dc157fae98efa57df0b3543e06f779ead4
Signed-off-by: Wanwei Jiang <wanwei.jiang@amlogic.com>
PD#SWPL-218353
Problem:
1. extract repeated code into a separate function.
2. change the parameter type from unsigned long to unsigned int
since the register is 32 bits
Solution:
modify reg filed access interface
Verify:
t5m
Change-Id: Ie9db201eb84c3bf59299a6b5e382e988b6d8110c
Signed-off-by: Wanwei Jiang <wanwei.jiang@amlogic.com>
PD#SWPL-218353
Problem:
support side band function
Solution:
1. add debugfs file interface;
2. add side band function interface for other modules
Verify:
local
Change-Id: Iddcd236dbeaf443e97d7784bec3828a121ec5809
Signed-off-by: Wanwei Jiang <wanwei.jiang@amlogic.com>
PD#SWPL-191305
Problem:
the frequency and bandwidth of LPDDR5 are inaccurate
Solution:
the frequency calculation methods for LPDDR5 and DDR3/2 are different
Verify:
local
Change-Id: Idb7bc333383f094c5071c0ac71276672f92dd06f
Signed-off-by: Wanwei Jiang <wanwei.jiang@amlogic.com>
shinys000114
Wanwei Jiang