PD#SWPL-128802
Problem:
cpu_dyn_clk may change parent when setting the frequency,
but set_parent is not executed in the driver
Solution:
Add necessary ops drivers.
Verify:
sc2_ah212
Change-Id: I128f862b8f8201136c3bc92022cb1e5beb1c92b9
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-137041
Problem:
hifi pll crash lock after ESD test
Solution:
bypass hifi pll lock_f bit
and change source to 400m for higher performance
Verify:
txhd2
Change-Id: Iaab34549b28b03cc277caa12b731242f22451507
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
PD#SWPL-136279
Problem:
current clock source is not fixed and may switch to PLL
Solution:
1. fixed clock source to fix div2
2. set default clk to 83MHZ
Verify:
c3
Change-Id: I0cd26da7416884e6ad89033c023477e9c609f3a6
Signed-off-by: Bichao Zheng <bichao.zheng@amlogic.com>
PD#SWPL-133117
Problem:
1 adapts to the new driver
2 some clock descriptions are incorrect
3 unified clock naming Convention
Solution:
fixed
Verify:
s1a_bg209
Change-Id: I4a7296a81b4662978b9aab225bf615ef4ec8747e
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-120773
Problem:
clock tree bringup for s1a
Solution:
add support
Verify:
pxp
Change-Id: I21040ed89cbd969bf71c250ef97b55592e4a43cb
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-136018
Problem:
optimize sys pll setting
Solution:
1.remove the unused frequency
2.remove cpu_dyn_clk 1G settings, add
it in probe avoid cpu is 24M during dvfs
3.remove deadcode in clk-pll.c
Verify:
t3x
Change-Id: I64ee9483b1821410029d315f06b83f9748009db3
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-130649
Problem:
there is no gp1 pll
Solution:
add gp1 support
Verify:
t3x
Change-Id: I47954709035c28e20079de481a960924e68d3629
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-128494
Problem:
1 not support non-secure ops function for cpu_cyn_clk
2 When c1 describes the same frequency, the corresponding
defined frequency is different.
Solution:
1 add non-secure ops function for cpu_cyn_clk
2 unify frequency to 666666666Hz
Verify:
c1_ae400
Change-Id: Idec9a54d7010e18336be02fd488239dd7114986b
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#SWPL-124230
Problem:
1 fclk50m is not added to clock tree;
2 dsp clk failed to set the frequency;
3 clkid incorrectly defined.
Solution:
fixed
Verify:
c1_ae400
Change-Id: Ieef2f603f72a6b0104b295b37c4a9ec448923d7c
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-121112
Problem:
clock tree bringup for c1
Solution:
support
Verify:
c1_ae400
Change-Id: Iaeacc52b6ac8266604614c2394d4a867e6edc203
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-130072
Problem:
Zapper size increase after txhd2 merge back to trunk
Solution:
optimize some code and add macro to reduce size
module: pinctrl, clk-measure, adc, audio, tvin, dtv_demod
ddr_port_desc, and amvecm
Verify:
Zapper
Change-Id: I0c781a657811cf664ffdbb4d9c18060e9b39554e
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
PD#SWPL-125774
Problem:
there is no range driver on 32bit os
Solution:
support
Verify:
TXHD2 be319
Change-Id: Ie8e40ade1c577d62a5cb551a4b3b08dd9d6056ac
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
PD#SWPL-125774
Problem:
there is no dmux
Solution:
fix it
Verify:
TXHD2 be319
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
Change-Id: Idc946009ed96e9d718f191f2d6ec02b01a1e6894
PD#SWPL-125774
Problem:
mali clk need parent lock gp0
Solution:
add mali clk parent gp0 and lock it
Verify:
TXHD2 be319
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
Change-Id: Ib4132b2e913111c010b0a788246168aa9c34695a
PD#SWPL-118428
Problem:
there is no txhd2 clk driver
Solution:
need to support clk driver
Verify:
TXHD2 PXP
Change-Id: I15f13c03768185a36a6a0eb607ff3835eaacd5b0
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
PD#SWPL-118802
Problem:
1 not support non-secure ops function for cpu_cyn_clk
2 When each chip describes the same frequency, the corresponding
defined frequency is different.
Solution:
1 add non-secure ops function for cpu_cyn_clk
2 unify frequency to 666666666Hz
Verify:
all about board
Change-Id: Ia9fe27291ead5a56ed737c6f6aea97fbcddfd44f
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-124395
Problem:
hifi clk rate is zero on 32bit
Solution:
support 32bit clk
Verify:
local ar321 & ar301
Change-Id: Ibd5a86d3b27a32b5206b39cff3a78be784b3bc9a
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
PD#SWPL-121364
Problem:
some configs are set to y by default
Solution:
change to n by default in Kconfig files
Verify:
local
Change-Id: I36edad847fa0767d75202be89e749149761d44dc
Signed-off-by: Dezhen Wang <dezhen.wang@amlogic.com>
PD#SWPL-117193
Problem:
sys2 pll does not support 852M
Solution:
add sys2 pll random frequency support
Verify:
t3x bc302
Change-Id: Id8719e3687df5e161266f535a84aee3feb8feb8d
Signed-off-by: jian.hu <jian.hu@amlogic.com>
PD#SWPL-117193
Problem:
t3x sys pll does not work well for dvfs
Solution:
add cpu and sys pll support
Verify:
t3x
Change-Id: Ia615b66b1ebd8c04b6d66679b73e6261615767f6
Signed-off-by: jian.hu <jian.hu@amlogic.com>
PD#SWPL-111639
Problem:
need support t3x vpu top
Solution:
add t3x vpu top support
Verify:
t3x skt
Change-Id: Ic50ca73814b17f3a2e2dc0ef49899dfe525d0be5
Signed-off-by: Jian Cao <jian.cao@amlogic.com>
PD#SWPL-111593
Problem:
hevc clock does not work
Solution:
fix hevc clock
Verify:
t3x mimic
Change-Id: I8aab29d01fe57d2179a4acaf9e3454f7cb9f1a19
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-123421
Problem:
change opp 1920M to 1908M
Solution:
change opp 1920M to 1908M
Verify:
T5M
Change-Id: I8f3a42f482761d170cf93ceb1e6f63e32e4a121d
Signed-off-by: Xingxing Wang <xingxing.wang@amlogic.com>
PD#SH-13928
Problem:
gp0_pll is initialized in uboot and is re-initialized after entering
the kernel, LCD display is abnormal.
Solution:
don't init gp0_pll in kernel
Verify:
C308L-AW419
Change-Id: I5bade98e4f6009dec5437d960be2e3375c16e74e
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
junyi.zhao