PD#SWPL-139800
Problem:
SC2 far field voice need early suspend and record
with dsp.
Solution:
When DSP waked up by VAD, then:
1. DSP notify to AOCPU (would fail by unknown cmd) and ARM
during early suspend.
2. DSP notify to AOCPU (would fail by unknown cmd) and ARM
(would fail by timeout) and do retry after ARM deep sleep and
before AOCPU STR poweroff.
3. DSP notify to AOCPU after AOCPU STR poweroff.
4. when ffv not supported, dsp do not start vwe.
Verify:
sc2_ah212
Change-Id: I0e610ab7dd76c362c71a9ec98ce589bf7d04beda
Signed-off-by: bangzheng.liu <bangzheng.liu@amlogic.com>
PD#SWPL-175088
Problem:
new ioctl cmd for get chip id.
Solution:
add new ioctl cmd and flow.
Verify:
t982
Change-Id: If7384905cbad3b9ee2c770a837ba98cf4031cd34
Signed-off-by: qinghui.jiang <qinghui.jiang@amlogic.com>
PD#SWPL-176326
Problem:
s6 need to support 1080p120hz
Solution:
s6 need to support 1080p120hz
Verify:
S6
Test:
DRM-TX-130
Change-Id: I594f9671b36d3ea27c838bcf349a06cdcf2c707c
Signed-off-by: ruofei.zhao <ruofei.zhao@amlogic.com>
PD#SWPL-175926
Problem:
In DLG mode, display size is 3840x1080, aoi reg
is updated to 3840x1080, if disable/enable video
with no toggle, aoi reg will continue to be halved
Solution:
record the ori and updated AOI with new variables
Verify:
t5m
Change-Id: Idbc479a1d157fb35be131b7b9896e5cbf0ee3b67
Signed-off-by: yao liu <yao.liu@amlogic.com>
PD#SWPL-174927
Problem:
currently apk like netflix get hdcp status
from hdmitx driver instead of drm, need to
use unify interface of drm to get hdcp status.
hdcp mode/auth status api already exist in drm,
but hdcp topo info is not provided to drm.
Solution:
provide hdcp topo info for drm
Verify:
s7d
Test:
DRM-TX-126
Change-Id: Ifb8c4bafdccd66a4d81d73c4501d264c72ddc80e
Signed-off-by: hang cheng <hang.cheng@amlogic.com>
PD#SWPL-174549
Problem:
secure permission needs to be set for the pwm_clk register
related to voltage regulation. Relevant clk configurations
need to be stored in bl31. kernel configurations need to
be deleted.
Solution:
fix it
Verify:
s7
Change-Id: If3477940b33f4a612743cb1c5c58ce45e59a8505
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#SWPL-174021
Problem:
screen anomaly in dma_buf and vf frame data composition using composer.
Solution:
1.clear src_vf after completing the composition of a frame of data.
2.fix the issue vicp cannot perform compositing on dma_buf.
Verify:
T3X
Change-Id: Ibf5492d823a1f1e8540feae7d8e275487a83710c
Signed-off-by: zhenteng.tian <zhenteng.tian@amlogic.com>
PD#SWPL-172965
Problem:
1 The mclk0 power supply uses the power supply inside the mclk_pll, so the
mclk0 output must ensure that mclk_pll is also enabled.
mclk_pll_clk can output clocks mclk_pll_src and fclk50m. The existence of
these two clock sources is meaningless.
2 If mclk0 uses mclk_pll as the clock source, div2 must be selected for
the clock of the later stage; otherwise, the output clock waveform of
mclk0 is abnormal.
Solution:
1 Delete the mclk_pll_src and fclk50m clock sources and set mclk_pll_clk
as the clock source of mclk0.
2 mclk0 selects div2 by default.
Verify:
s6_bl201
Change-Id: I9a8e3e1616b4c9b3b9c86990f86dc337f9f9c877
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-172965
Problem:
1 All I2C Masters (i2c_m_a-f) in a chip share an APB bus, which is
provided by sys_i2c_m_a. PWM is designed with a similar architecture, and
the APB bus of PWM is clock provided by sys_pwm_a.
2 The CLKID definition of smart card is inconsistent.
Solution:
1 The parent of sys_i2c_m_b-f is set to sys_i2c_m_a.
2 The parent of sys_pwm_b-i is set to sys_pwm_a.
3 CLKID_SC_DIV was renamed CLKID_SC.
Verify:
s6_bl201
Change-Id: I94482625f3a9fe387113edce21ed16e9dc63a074
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-172976
Problem:
add aocpu alive detection and mailbox retry mechanism to
avoid mailbox message lost due to aocpu crash or mailbox
signal lost occasionally
Solution:
add aocpu alive detection and mailbox retry mechanism
Verify:
S6-BL201
Change-Id: Ia90380a7ead99e7f00eb82bcde02201f4636dd30
Signed-off-by: Yao Jie <jie.yao@amlogic.com>
PD#SWPL-172965
Problem:
1 mclk_pll and dspa_clk output are incorrect
2 mmc failed to insmod
3 Lost sys_i2c_s_a
Solution:
1 Update the table for mclk_pll
2 Update the parent table of the dspa
3 Ignore initializing gp0_pll
4 Added sys_i2c_s_a
Verify:
s6_bl201
Change-Id: I23586623d908ef871e178acf0da8883aabc12fc9
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-158289
Problem:
1 The register corresponding to oscin was updated;
2 Put some of the key clocks into bl31 for processing.
Solution:
fixed
Verify:
pxp
Change-Id: Ie5ea8b6c507ce136ba397e8e54362b72f05cf45c
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-153862
Problem:
s6 need power domain support.
Solution:
add power domain in kernel.
Verify:
pxp
Change-Id: I5ba46225cb08a4a92d43fe25d7f6385d65bf6efb
Signed-off-by: hongyu.chen1 <hongyu.chen1@amlogic.com>
PD#SWPL-172361
Problem:
bypass di according to compression ratio.
Solution:
Modify vc flow to implement this requirement.
Verify:
t5m
Change-Id: Iace3aec5f202369882793a42c66a6b590211cf29
Signed-off-by: qiyao.zhou <qiyao.zhou@amlogic.com>
PD#SWPL-175588
Problem:
Need support s7d revb
Solution:
1, add clk set for revb;
2, use clk interface for clk set
Verify:
S7D bm201
Change-Id: I168a942f6796208dd4dff67a13f065be14a40f0c
Signed-off-by: Tao Zeng <tao.zeng@amlogic.com>
PD#SWPL-170918
PD#SWPL-161717
Problem:
Sink may support only 4k120, but its QMS range may be from
24 to 120.
Or sink may support upto 4k60, but 1080p120hz.
Solution:
Add the qms/game vrr range and vic lists to DRM group
Don't clear the EDID when forced_edid is true
Skip BRR 120 check when QMS tfr_max is false
Verify:
s7d/ross
Test:
DRM-TX-75
Change-Id: Ia65fa38bf18ae7399c9c4178665f8a3f18a03a74
Signed-off-by: zongdong.jiao <zongdong.jiao@amlogic.com>
PD#SWPL-160981
Problem:
The CQE v1 does not support placing tasks in memory
and does not support data encryption.
Solution:
support CQE v2
Verify:
S7 ax201
Change-Id: I0737d7b2b9e955838a9f3294d1f5faf5fd84aa17
Signed-off-by: Long <long.yu@amlogic.com>
PD#SWPL-168860
Problem:
add vpp afd info for hdmi and atv
Solution:
1. add vpp afd info for hdmi and atv
2. add crop info into afd input param
Verify:
t5m
Change-Id: I882a2d59c8738e3844d0ccc72e41a267a4463c62
Signed-off-by: Pengcheng Chen <pengcheng.chen@amlogic.com>
PD#SWPL-168849
PD#SWPL-168856
Problem:
AFD feature development
Solution:
vdin pass afd info to vpp
Verify:
t5m
Change-Id: I3264ef109e560590b3da1c5ae0d2ab6355c8ea19
Signed-off-by: haitao.liu <haitao.liu@amlogic.com>
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-172344
Problem:
use video_composer to set the FRC working mode.
Solution:
use video_composer to set the FRC working mode.
Verify:
T5M
Change-Id: I70ad264105144ae07b2c8336e722c7369c025f74
Signed-off-by: zhenteng.tian <zhenteng.tian@amlogic.com>
bangzheng.liu