Bichao Zheng 474b6b0d3c spinand: c3 fixed clock source to fix div2 [1/1] ...

PD#SWPL-136279

Problem:
current clock source is not fixed and may switch to PLL

Solution:
1. fixed clock source to fix div2
2. set default clk to 83MHZ

Verify:
c3

Change-Id: I0cd26da7416884e6ad89033c023477e9c609f3a6
Signed-off-by: Bichao Zheng <bichao.zheng@amlogic.com>

2023-08-15 04:19:36 -07:00

..

arm

spinand: c3 fixed clock source to fix div2 [1/1]

2023-08-15 04:19:36 -07:00

arm64

spi: back sync with t5m openliux/tv/s-amlogic [1/1]

2023-08-15 04:19:20 -07:00

riscv

dump_stack: optimize dts property [1/1]

2023-04-16 21:24:26 -07:00