mirror of
https://github.com/hardkernel/kernel_common_drivers.git
synced 2026-06-25 12:03:48 +09:00
Tao Zeng
c2ce371c4a
PD#SWPL-137614 PD#SWPL-163213 Problem: No amfc driver Solution: add it: 1, basic driver for AMFC 2, EROFS support 3, kernel compressed by ZSTD support Verify: pxp Change-Id: I45d2e308d209e35edba626619072aae93c4d0f56 Signed-off-by: Tao Zeng <tao.zeng@amlogic.com>
185 lines
5.2 KiB
C
185 lines
5.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _AMFC_REGS_H_
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#define _AMFC_REGS_H_
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#define CLKCTRL_AMFC_CLK_CTRL ((0x0065 << 2))
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#define AMFC_GL_VERSION ((0x0 << 2))
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//Bit 31:16 reserved
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//Bit 15:8 ro_major_version
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//Bit 7:0 ro_minor_version
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#define AMFC_GL_MISC ((0x1 << 2))
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//Bit 31:1 reserved
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//Bit 0 reg_global_irq_en
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#define AMFC_GL_CMD0_DESC_BASE_ADDR ((0x2 << 2))
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//Bit 31: 0 reg_cmd0_desc_base_addr
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#define AMFC_GL_CMD0_CURR_DESC_ADDR ((0x3 << 2))
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//Bit 31: 0 ro_cmd0_cur_desc_addr
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#define AMFC_GL_CMD0_CONTROL ((0x4 << 2))
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//Bit 31 reg_cmd0_sw_rst
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//Bit 30: 2 reserved
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//Bit 1 reg_cmd0_sw_terminate
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//Bit 0 reg_cmd0_sw_start
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#define AMFC_GL_CMD0_CONFIG ((0x5 << 2))
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//Bit 31: 0 reg_cmd0_config
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#define AMFC_GL_CMD0_STATUS ((0x6 << 2))
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//Bit 31: 24 ro_cmd0_irq
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//Bit 23: 16 reserved
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//Bit 15: 8 ro_cmd0_err_code
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//Bit 7 : 0 ro_cmd0_status
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#define AMFC_GL_CMD0_FEATURE ((0x7 << 2))
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//Bit 31: 5 reserved
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//Bit 4 ro_cmd0_feat_zlib
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//Bit 3 ro_cmd0_feat_deflate
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//Bit 2 ro_cmd0_feat_gzip
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//Bit 1 ro_cmd0_feat_lz4
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//Bit 0 ro_cmd0_feat_zstd
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#define AMFC_GL_CMD0_IRQCLR ((0x8 << 2))
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//Bit 31: 8 reserved
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//Bit 7 : 0 reg_cmd0_irq_clr
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//--------------------------
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#define AMFC_GL_CMD1_DESC_BASE_ADDR ((0x12 << 2))
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//Bit 31: 0 reg_cmd1_desc_base_addr
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#define AMFC_GL_CMD1_CURR_DESC_ADDR ((0x13 << 2))
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//Bit 31: 0 ro_cmd1_cur_desc_addr
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#define AMFC_GL_CMD1_CONTROL ((0x14 << 2))
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//Bit 31 reg_cmd1_sw_rst
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//Bit 30: 2 reserved
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//Bit 1 reg_cmd1_sw_terminate
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//Bit 0 reg_cmd1_sw_start
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#define AMFC_GL_CMD1_CONFIG ((0x15 << 2))
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//Bit 31: 0 reg_cmd1_config
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#define AMFC_GL_CMD1_STATUS ((0x16 << 2))
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//Bit 31: 24 ro_cmd1_irq
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//Bit 23: 16 reserved
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//Bit 15: 8 ro_cmd1_err_code
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//Bit 7 : 0 ro_cmd1_status
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#define AMFC_GL_CMD1_FEATURE ((0x17 << 2))
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//Bit 31: 5 reserved
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//Bit 4 ro_cmd1_feat_zlib
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//Bit 3 ro_cmd1_feat_deflate
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//Bit 2 ro_cmd1_feat_gzip
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//Bit 1 ro_cmd1_feat_lz4
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//Bit 0 ro_cmd1_feat_zstd
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#define AMFC_GL_CMD1_IRQCLR ((0x18 << 2))
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//Bit 31: 8 reserved
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//Bit 7 : 0 reg_cmd1_irq_clr
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#define AMFC_CMD0_TIME_MEASURE ((0x001c << 2))
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#define AMFC_CMD1_TIME_MEASURE ((0x001d << 2))
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#define AMFC_DECOMPR_STATUS4 ((0x002e << 2))
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//---------------------------------------------
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//Gate clock control
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#define AMFC_CMD_GATE_CLK_CTRL ((0x20 << 2))
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//Bit 31: 0 reg_cmd_gclk_ctrl
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#define AMFC_ENC_GATE_CTRL_CTRL_0 ((0x21 << 2))
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//Bit 31: 0 reg_enc_gclk_ctrl_0
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#define AMFC_ENC_GATE_CTRL_CTRL_1 ((0x22 << 2))
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//Bit 31: 0 reg_enc_gclk_ctrl_1
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#define AMFC_DEC_GATE_CTRL_CTRL_0 ((0x23 << 2))
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//Bit 31: 0 reg_dec_gclk_ctrl_0
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#define AMFC_DEC_GATE_CTRL_CTRL_1 ((0x24 << 2))
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//Bit 31: 0 reg_dec_gclk_ctrl_1
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//CODEC
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#define AMFC_CODEC_CTRL ((0x28 << 2))
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//Bit 31:8 reserved
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//Bit 7:6 reg_cmd1_dst_end_mode
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//Bit 5:4 reg_cmd0_dst_end_mode
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//Bit 3 reserved
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//Bit 2 reg_cmds_split_mode
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//Bit 1 reg_decmpr_enable
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//Bit 0 reg_cmpr_enable
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#define AMFC_COMPR_STATUS ((0x29 << 2))
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//Bit 31:0 ro_cmpr_status
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#define AMFC_DECOMPR_STATUS ((0x2a << 2))
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//Bit 31:0 ro_decmpr_status
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//----------------------------------
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#define AMFC_ZSTD_MODE_MISC ((0x30 << 2))
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//Bit 31:2 reserved
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//Bit 1 reg_enc_lz77_disable
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//Bit 0 reg_fse_default_allowed
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#define AMFC_ZSTD_HASH_TBL_INIT ((0x31 << 2))
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//Bit 31:6 reserved
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//Bit 5:4 reg_hash_tbl_init_mode
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//Bit 3:1 reserved
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//------------------------------------------
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//MIF register
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#define AMFC_WR_MIF_CTRL ((0x40 << 2))
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//Bit 31:24 reserved
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//Bit 23:16 reg_wrmif_canvas_id
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//Bit 15:11 reserved
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//Bit 10:8 reg_wrmif_burst_len
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//Bit 7:6 reserved
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//Bit 5 reg_wrmif_swap_64bit
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//Bit 4 reg_wrmif_little_endian
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//Bit 3:1 reserved
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//Bit 0 reg_wrmif_enable
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#define AMFC_WR_MIF_STATUS ((0x41 << 2))
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//Bit 31:0 ro_wrmif_status
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#define AMFC_RD_MIF_CTRL ((0x42 << 2))
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//Bit 31:24 reserved
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//Bit 23:16 reg_rdmif_canvas_id
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//Bit 15:11 reserved
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//Bit 10:8 reg_rdmif_burst_len
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//Bit 7:6 reserved
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//Bit 5 reg_rdmif_swap_64bit
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//Bit 4 reg_rdmif_little_endian
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//Bit 3:1 reserved
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//Bit 0 reg_rdmif_enable
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#define AMFC_RD_MIF_STATUS ((0x43 << 2))
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//Bit 31:0 ro_rdmif_status
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#define AMFC_MIF_QOS_UGT ((0x44 << 2))
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//Bit 31:16 reserved
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//Bit 15 reg_decmpr_arugt
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//Bit 14 reg_decmpr_arqos
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//Bit 13 reg_decmpr_awugt
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//Bit 12 reg_decmpr_awqos
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//Bit 11 reg_cmpr_arugt
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//Bit 10 reg_cmpr_arqos
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//Bit 9 reg_cmpr_awugt
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//Bit 8 reg_cmpr_awqos
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//Bit 7 reg_cmd1_arugt
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//Bit 6 reg_cmd1_arqos
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//Bit 5 reg_cmd1_awugt
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//Bit 4 reg_cmd1_awqos
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//Bit 3 reg_cmd0_arugt
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//Bit 2 reg_cmd0_arqos
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//Bit 1 reg_cmd0_awugt
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//Bit 0 reg_cmd0_awqos
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#endif
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