mirror of
https://github.com/hardkernel/kernel_common_drivers.git
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dian.shao
fb2db42f7f
PD#SWPL-180337 Problem: S6 usb2t controller clks need update. Solution: Add clk mux codes & dts nodes. Verify: br201. Change-Id: I5342898a9864601f58f3ba6aa49f113ca1e81642 Signed-off-by: dian.shao <dian.shao@amlogic.com>
124 lines
3.0 KiB
C
124 lines
3.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __USB_V2_COMMON_HEADER_
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#define __USB_V2_COMMON_HEADER_
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#include <linux/usb/phy.h>
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#include <linux/platform_device.h>
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#include <linux/workqueue.h>
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#include <linux/clk.h>
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#include <linux/amlogic/usb-v2.h>
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enum aml_usb_phy_mode {
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AML_USB_PHY_MODE_INVALID,
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AML_USB_PHY_MODE_USB_HOST,
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AML_USB_PHY_MODE_USB_DEVICE,
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AML_USB_PHY_MODE_USB_LS,
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AML_USB_PHY_MODE_USB_FS,
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AML_USB_PHY_MODE_USB_HS,
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AML_USB_PHY_MODE_USB_HSP,
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AML_USB_PHY_MODE_USB_SS,
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AML_USB_PHY_MODE_USB_OTG,
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};
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#define USB_PHY_MAX_NUMBER 0x8
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#define AML_USB_PHY_MAX_CLK_NUMBER 0x3
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struct amlogic_usb_v2 {
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struct usb_phy phy;
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struct device *dev;
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const void *pdata;
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void __iomem *regs;
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void __iomem *reset_regs;
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void __iomem *phy_cfg[4];
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void __iomem *phy3_cfg;
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void __iomem *phy3_cfg_r1;
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void __iomem *phy3_cfg_r2;
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void __iomem *phy3_cfg_r4;
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void __iomem *phy3_cfg_r5;
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void __iomem *phy31_cfg;
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void __iomem *phy31_cfg_r1;
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void __iomem *phy31_cfg_r2;
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void __iomem *phy31_cfg_r4;
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void __iomem *phy31_cfg_r5;
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void __iomem *usb2_phy_cfg;
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void __iomem *xhci_port_a_addr;
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struct u2p_aml_regs_m_v2 __iomem *u2p_aml_regs[USB_PHY_MAX_NUMBER];
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u32 pll_setting[8];
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u32 pll_ver;
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u32 ic_ver;
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u32 pll_dis_thred_enhance;
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int phy_cfg_state[4];
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int phy_trim_initvalue[8];
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int phy_0xc_initvalue[8];
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int phy_trim_state[4];
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/* Set VBus Power though GPIO */
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int vbus_power_pin;
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int vbus_power_pin_work_mask;
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int otg;
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u32 version;
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int portspeed;
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struct delayed_work work;
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struct delayed_work id_gpio_work;
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struct gpio_desc *usb_gpio_desc;
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struct gpio_desc *idgpiodesc;
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int portnum;
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int suspend_flag;
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int phy_version;
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u32 phy_reset_level_bit[USB_PHY_MAX_NUMBER];
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u32 phy_reg_reset_level_bit[USB_PHY_MAX_NUMBER];
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u32 usb_reset_bit;
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u32 usb_comb_reset_bit;
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bool pm_controller;
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u32 otg_phy_index;
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u32 reset_level;
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struct clk_bulk_data clks[AML_USB_PHY_MAX_CLK_NUMBER];
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int clk_num;
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u32 clk_mux;
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struct clk *clk;
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struct clk *usb_clk;
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struct clk *gate0_clk;
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struct clk *gate1_clk;
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struct clk *hcsl_clk;
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struct clk *pcie_bgp;
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u32 portconfig_31;
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u32 portconfig_30;
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void __iomem *usb_phy_trim_reg;
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u32 phy_id;
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struct clk *general_clk;
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u32 usb3_apb_reset_bit;
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u32 usb3_phy_reset_bit;
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u32 usb3_reset_shift;
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void (*resume_xhci_p_a)(void);
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void (*disable_port_a)(void);
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void (*usb2_phy_init)(void);
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int (*usb2_get_mode)(void);
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void (*phy_trim_tuning)(struct usb_phy *x,
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int port, int default_val);
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void (*set_usb_pll)(struct amlogic_usb_v2 *phy,
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void __iomem *reg);
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};
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static inline void
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usb_phy_trim_tuning(struct usb_phy *x, int port, int default_val)
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{
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struct amlogic_usb_v2 *aml_phy;
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if (x) {
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if (x->label)
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if (!strncmp(x->label, "amlogic-usbm31phy3", 18) ||
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!strncmp(x->label, "amlogic-usb2-m31-phy", 20))
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return;
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aml_phy = container_of(x, struct amlogic_usb_v2, phy);
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if (aml_phy->phy_trim_tuning)
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aml_phy->phy_trim_tuning(x, port, default_val);
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}
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}
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#endif
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