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https://github.com/hardkernel/kernel_common_drivers.git
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yiting.deng
03b97b46a5
PD#SWPL-195087 Problem: integrate rtc and vrtc, optimize rtc driver Solution: fix it Verify: s7, s6, t5m, txhd2, sc2, t7c, a5 Change-Id: I62c3cc23bb848c6ba0e3e44305c725b07ee108f7 Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
98 lines
2.8 KiB
C
98 lines
2.8 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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/*******************************************************************/
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#include <linux/types.h>
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#include <linux/regmap.h>
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#include <linux/alarmtimer.h>
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#include <linux/clk-provider.h>
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/* rtc oscillator rate */
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#define OSC_32K (32768)
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#define OSC_24M (24000000)
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#define RTC_CTRL_REG (0x0 << 2) /* Control RTC -RW*/
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#define RTC_ALRM0_EN BIT(0)
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#define RTC_ALRM1_EN BIT(1)
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#define RTC_ALRM2_EN BIT(2)
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#define RTC_ALRM3_EN BIT(3)
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#define RTC_OSC_SEL BIT(8)
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#define RTC_ENABLE BIT(12)
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#define RTC_COUNTER_REG (0x1 << 2) /* Program RTC counter initial value -RW*/
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#define RTC_ALARM0_REG (0x2 << 2) /* Program RTC alarm0 value -RW*/
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#define RTC_ALARM1_REG (0x3 << 2) /* Program RTC alarm1 value -RW*/
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#define RTC_ALARM2_REG (0x4 << 2) /* Program RTC alarm2 value -RW*/
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#define RTC_ALARM3_REG (0x5 << 2) /* Program RTC alarm3 value -RW*/
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#define RTC_SEC_ADJUST_REG (0x6 << 2) /* Control second-based timing adjustment -RW*/
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#define RTC_MATCH_COUNTER GENMASK(18, 0)
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#define RTC_SEC_ADJUST_CTRL GENMASK(20, 19)
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#define RTC_ADJ_VALID BIT(23)
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#define RTC_DIV256_ADJ_VAL BIT(24)
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#define RTC_DIV256_ADJ_DSR BIT(25)
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#define RTC_INT_MASK (0x8 << 2) /* RTC interrupt mask -RW*/
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#define RTC_ALRM0_IRQ_MSK BIT(0)
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#define RTC_ALRM1_IRQ_MSK BIT(1)
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#define RTC_ALRM2_IRQ_MSK BIT(2)
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#define RTC_ALRM3_IRQ_MSK BIT(3)
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#define RTC_INT_CLR (0x9 << 2) /* Clear RTC interrupt -RW*/
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#define RTC_ALRM0_IRQ_CLR BIT(0)
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#define RTC_ALRM1_IRQ_CLR BIT(1)
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#define RTC_ALRM2_IRQ_CLR BIT(2)
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#define RTC_ALRM3_IRQ_CLR BIT(3)
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#define RTC_OSCIN_CTRL0 (0xa << 2) /* Control RTC clk from 24M -RW*/
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#define RTC_OSCIN_CTRL1 (0xb << 2) /* Control RTC clk from 24M -RW*/
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#define RTC_OSCIN_IN_EN BIT(31)
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#define RTC_OSCIN_OUT_CFG GENMASK(29, 28)
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#define RTC_OSCIN_OUT_N0M0 GENMASK(11, 0)
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#define RTC_OSCIN_OUT_N1M1 GENMASK(23, 12)
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#define RTC_INT_STATUS (0xc << 2) /* RTC interrupt status -R*/
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#define RTC_ALRM0_IRQ_STATUS BIT(0)
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#define RTC_ALRM1_IRQ_STATUS BIT(1)
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#define RTC_ALRM2_IRQ_STATUS BIT(2)
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#define RTC_ALRM3_IRQ_STATUS BIT(3)
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#define RTC_REAL_TIME (0xd << 2) /* RTC counter value -R*/
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#define RTC_OSCIN_OUT_32K_N0 0x2dc
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#define RTC_OSCIN_OUT_32K_N1 0x2db
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#define RTC_OSCIN_OUT_32K_M0 0x1
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#define RTC_OSCIN_OUT_32K_M1 0x2
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#define RTC_SWALLOW_SECOND 0x2
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#define RTC_INSERT_SECOND 0x3
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/* vrtc alarm reg */
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#define VRTC_ALARM_REG (0x0 << 2)
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static struct regmap_config aml_rtc_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.name = "aml_rtc",
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};
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struct aml_rtc_data {
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struct regmap *map;
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struct rtc_device *rtc_dev;
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struct mbox_chan *mbox_chan;
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int irq;
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bool rtc_virtual;
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struct clk *rtc_clk;
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struct clk *sys_clk;
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bool alarm_enabled;
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bool wakealrm_enabled;
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bool time_storage_format;
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};
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