Chuan Liu 0d479df10f c3: update clk tree code [2/2] ...

PD#SWPL-83827

Problem:
1 add clk_notifier
2 pll clock register is incorrectly configured
3 pwm clk source of pwm defined error

Solution:
1 update clk tree code
2 optimize pll timing(https://scgit.amlogic.com/#/c/231673/)

Verify:
AW419-C308L

Change-Id: I7e2f1cc9143b37a493bfaba3163f1a173c164935
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>

2022-06-30 18:09:28 +08:00

..

drm

drm: add drm driver support [1/1]

2022-06-07 04:47:30 -07:00

dt-bindings

c3: update clk tree code [2/2]

2022-06-30 18:09:28 +08:00

linux/amlogic

C3: usb: c3 usb driver [1/1]

2022-06-30 18:09:28 +08:00

trace/events

debug_lockup: add support [2/2]

2022-02-22 03:18:28 -07:00

uapi/amlogic

drm: add drm driver support [1/1]

2022-06-07 04:47:30 -07:00