PD#SWPL-174740
Problem:
SPISG driver sets clk rate twice for a transfer, one sets the clk rate
with the spi device max_speed_hz in prepare_message, and the other sets
the clk rate with the transfer speed_hz in one_transfer.
Normally, the subsequent clk rate setting would be ingored if the speed
doesn't change. But if the two speeds are different, it would bring about
the clk_set_rate calling twice, and each calling takes about 2~3 msec.
Solution:
Port from cl-434207
Remove the unnecessary clk rate setting of prepare_message
Verify:
s7 bh201
Change-Id: I655a03f166415a256b35739e898be29ae047082a
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
Sunny Luo
f62b139bbe