jian.hu b97695c773 clk: correct eth phy clock name [1/1] ...

PD#SWPL-180321

Problem:
there is no eth phy clock

Solution:
correct eth phy clock name

Verify:
t6d br301

Change-Id: Ie8ff90cf998c4a8064f01e4e52d63b7e284b4dd3
Signed-off-by: jian.hu <jian.hu@amlogic.com>

2024-08-22 14:27:51 +08:00

..

drm

drm: optimize qms_brr_viclist function [1/1]

2024-08-15 04:00:48 -07:00

dt-bindings

clk: correct eth phy clock name [1/1]

2024-08-22 14:27:51 +08:00

linux/amlogic

usb: t6d bringup [1/1]

2024-08-22 14:27:51 +08:00

trace/events

drm: add rdma table for drm osd registers [1/1]

2024-07-17 23:57:23 -07:00

uapi/amlogic

amvecm: t6d bringup [1/1]

2024-08-22 14:27:51 +08:00