mirror of
https://github.com/hardkernel/kernel_common_drivers.git
synced 2026-06-25 12:03:48 +09:00
Jian Cao
93e7a3e838
PD#SWPL-120646 Problem: add osd vpp1 display Solution: add this support Verify: t3x Change-Id: Ic1093328f423a3447f085218b16be29b59b6c97f Signed-off-by: Jian Cao <jian.cao@amlogic.com>
920 lines
30 KiB
C
920 lines
30 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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/* Linux Headers */
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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/* Amlogic Headers */
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#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
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#include <linux/amlogic/media/canvas/canvas.h>
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#include <linux/amlogic/media/canvas/canvas_mgr.h>
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#endif
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#ifdef CONFIG_AMLOGIC_MEDIA_GE2D
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#include <linux/amlogic/media/ge2d/ge2d.h>
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#endif
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/* Local Headers */
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#include "osd_canvas.h"
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#include "osd_log.h"
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#include "osd_reg.h"
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#include "osd_io.h"
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#include "osd_hw.h"
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#ifdef CONFIG_AMLOGIC_MEDIA_SW_SYNC
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#include "../common/sw_sync/osd_sw_sync.h"
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#endif
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#define OSD_TEST_DURATION 200
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#ifdef CONFIG_AMLOGIC_MEDIA_GE2D
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static struct config_para_s ge2d_config;
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static struct config_para_ex_s ge2d_config_ex;
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static struct ge2d_context_s *ge2d_context;
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#endif
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char osd_debug_help[] = "Usage:\n"
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" echo [i | info] > debug ; Show osd pan/display/scale information\n"
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" echo [t | test] > debug ; Start osd auto test\n"
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" echo [r | read] reg > debug ; Read VCBUS register\n"
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" echo [w | write] reg val > debug ; Write VCBUS register\n"
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" echo [d | dump] {start end} > debug ; Dump VCBUS register\n\n";
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static void osd_debug_dump_value(void)
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{
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u32 index = 0;
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struct hw_para_s *hwpara = NULL;
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struct pandata_s *pdata = NULL;
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osd_get_hw_para(&hwpara);
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if (!hwpara)
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return;
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osd_log_info("--- OSD ---\n");
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osd_log_info("bot_type: %d\n", hwpara->bot_type);
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osd_log_info("field_out_en: %d\n", hwpara->field_out_en[VIU1]);
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if (osd_hw.osd_meson_dev.has_viu2)
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osd_log_info("field_out_en: %d\n", hwpara->field_out_en[VIU2]);
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if (hwpara->osd_meson_dev.osd_ver == OSD_HIGH_ONE) {
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struct hw_osd_blending_s *blend_para = NULL;
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osd_get_blending_para(&blend_para);
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if (blend_para) {
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osd_log_info("OSD LAYER: %d\n", blend_para->layer_cnt);
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osd_log_info("|index\t|order\t|src axis\t|dst axis\n");
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for (index = 0; index < HW_OSD_COUNT; index++) {
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osd_log_info("%2d\t%2d\t(%4d,%4d,%4d,%4d)\t(%4d,%4d,%4d,%4d)\n",
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index,
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hwpara->order[index],
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hwpara->src_data[index].x,
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hwpara->src_data[index].y,
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hwpara->src_data[index].w,
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hwpara->src_data[index].h,
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hwpara->dst_data[index].x,
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hwpara->dst_data[index].y,
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hwpara->dst_data[index].w,
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hwpara->dst_data[index].h);
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}
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}
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}
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for (index = 0; index < HW_OSD_COUNT; index++) {
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osd_log_info("\n--- OSD%d ---\n", index);
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osd_log_info("order: %d\n", hwpara->order[index]);
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osd_log_info("scan_mode: %d\n", hwpara->scan_mode[index]);
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osd_log_info("enable: %d\n", hwpara->enable[index]);
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osd_log_info("2x-scale enable.h:%d .v: %d\n",
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hwpara->scale[index].h_enable,
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hwpara->scale[index].v_enable);
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osd_log_info("free-scale-mode: %d\n",
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hwpara->free_scale_mode[index]);
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osd_log_info("free-scale enable.h:%d .v: %d\n",
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hwpara->free_scale[index].h_enable,
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hwpara->free_scale[index].v_enable);
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pdata = &hwpara->pandata[index];
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osd_log_info("pan data:\n");
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osd_log_info("\tx_start: 0x%08x, x_end: 0x%08x\n",
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pdata->x_start, pdata->x_end);
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osd_log_info("\ty_start: 0x%08x, y_end: 0x%08x\n",
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pdata->y_start, pdata->y_end);
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pdata = &hwpara->dispdata[index];
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osd_log_info("disp data:\n");
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osd_log_info("\tx_start: 0x%08x, x_end: 0x%08x\n",
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pdata->x_start, pdata->x_end);
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osd_log_info("\ty_start: 0x%08x, y_end: 0x%08x\n",
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pdata->y_start, pdata->y_end);
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pdata = &hwpara->scaledata[index];
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osd_log_info("2x-scale data:\n");
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osd_log_info("\tx_start: 0x%08x, x_end: 0x%08x\n",
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pdata->x_start, pdata->x_end);
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osd_log_info("\ty_start: 0x%08x, y_end: 0x%08x\n",
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pdata->y_start, pdata->y_end);
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pdata = &hwpara->free_src_data[index];
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osd_log_info("free-scale src data:\n");
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osd_log_info("\tx_start: 0x%08x, x_end: 0x%08x\n",
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pdata->x_start, pdata->x_end);
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osd_log_info("\ty_start: 0x%08x, y_end: 0x%08x\n",
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pdata->y_start, pdata->y_end);
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pdata = &hwpara->free_dst_data[index];
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osd_log_info("free-scale dst data:\n");
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osd_log_info("\tx_start: 0x%08x, x_end: 0x%08x\n",
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pdata->x_start, pdata->x_end);
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osd_log_info("\ty_start: 0x%08x, y_end: 0x%08x\n",
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pdata->y_start, pdata->y_end);
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}
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}
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static void osd_debug_dump_register_all(void)
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{
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u32 reg = 0;
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u32 index = 0;
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u32 count = osd_hw.osd_meson_dev.osd_count;
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struct hw_osd_reg_s *osd_reg = NULL;
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struct hw_osd_blend_reg_s *blend_reg = &hw_osd_reg_blend;
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reg = VPU_VIU_VENC_MUX_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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if (osd_dev_hw.display_type != C3_DISPLAY) {
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reg = VPU_VIU_VENC_MUX_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = VPP_MISC;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = VPP_OFIFO_SIZE;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = VPP_HOLD_LINES;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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}
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if (osd_dev_hw.s5_display) {
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reg = S5_VPP_MISC;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = S5_VPP_OFIFO_SIZE;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = VPP_INTF_OSD3_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(2mux1)\n", reg, osd_reg_read(reg));
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reg = OSD_PROC_1MUX3_SEL;
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osd_log_info("reg[0x%x]: 0x%08x(1mux3)\n", reg, osd_reg_read(reg));
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reg = OSD_PI_BYPASS_EN;
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osd_log_info("reg[0x%x]: 0x%08x(PI)\n", reg, osd_reg_read(reg));
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reg = OSD_SYS_5MUX4_SEL;
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osd_log_info("reg[0x%x]: 0x%08x(5mux4)\n", reg, osd_reg_read(reg));
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} else {
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reg = VPP_MISC;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = VPP_OFIFO_SIZE;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = VPP_HOLD_LINES;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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}
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if (osd_dev_hw.display_type == T7_DISPLAY) {
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reg = PATH_START_SEL;
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osd_log_info("reg[0x%x]: 0x%08x(osd vsync sel)\n", reg, osd_reg_read(reg));
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reg = OSD_PATH_MISC_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(vpp mux)\n", reg, osd_reg_read(reg));
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reg = MALI_AFBCD_TOP_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd1/2 dv bypass bit14/20)\n",
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reg, osd_reg_read(reg));
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reg = MALI_AFBCD1_TOP_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd3 dv bypass bit20)\n", reg, osd_reg_read(reg));
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reg = MALI_AFBCD2_TOP_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd4 dv bypass bit20)\n", reg, osd_reg_read(reg));
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reg = VPP_WRAP_OSD1_MATRIX_EN_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd1 matrix en)\n", reg, osd_reg_read(reg));
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reg = VPP_WRAP_OSD2_MATRIX_EN_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd2 matrix en)\n", reg, osd_reg_read(reg));
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reg = VIU_OSD3_MATRIX_EN_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd3 matrix en)\n", reg, osd_reg_read(reg));
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reg = VIU_OSD4_MATRIX_EN_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd4 matrix en)\n", reg, osd_reg_read(reg));
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reg = OSD1_HDR_IN_SIZE;
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osd_log_info("reg[0x%x]: 0x%08x(osd1 hdr size)\n", reg, osd_reg_read(reg));
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reg = OSD2_HDR_IN_SIZE;
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osd_log_info("reg[0x%x]: 0x%08x(osd2 hdr size)\n", reg, osd_reg_read(reg));
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reg = OSD3_HDR_IN_SIZE;
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osd_log_info("reg[0x%x]: 0x%08x(osd3 hdr size)\n", reg, osd_reg_read(reg));
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reg = OSD4_HDR_IN_SIZE;
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osd_log_info("reg[0x%x]: 0x%08x(osd4 hdr size)\n", reg, osd_reg_read(reg));
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reg = OSD1_HDR2_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd1 hdr ctrl)\n", reg, osd_reg_read(reg));
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reg = _OSD2_HDR2_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd2 hdr ctrl)\n", reg, osd_reg_read(reg));
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reg = OSD3_HDR2_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd3 hdr ctrl)\n", reg, osd_reg_read(reg));
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reg = OSD4_HDR2_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd4 hdr ctrl)\n", reg, osd_reg_read(reg));
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reg = OSD1_HDR2_MATRIXI_EN_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd1 csc matrixi ctrl)\n", reg, osd_reg_read(reg));
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reg = OSD1_HDR2_MATRIXO_EN_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd1 csc matrixo ctrl)\n", reg, osd_reg_read(reg));
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reg = _OSD2_HDR2_MATRIXI_EN_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd2 csc matrixi ctrl)\n", reg, osd_reg_read(reg));
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reg = _OSD2_HDR2_MATRIXO_EN_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd2 csc matrixo ctrl)\n", reg, osd_reg_read(reg));
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reg = OSD3_HDR2_MATRIXI_EN_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd3 csc matrixi ctrl)\n", reg, osd_reg_read(reg));
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reg = OSD3_HDR2_MATRIXO_EN_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd3 csc matrixo ctrl)\n", reg, osd_reg_read(reg));
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reg = OSD4_HDR2_MATRIXI_EN_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd4 csc matrixi ctrl)\n", reg, osd_reg_read(reg));
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reg = OSD4_HDR2_MATRIXO_EN_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd4 csc matrixo ctrl)\n", reg, osd_reg_read(reg));
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if (osd_dev_hw.path_ctrl_independ) {
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reg = VIU_OSD1_PATH_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd1 path)\n",
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reg, osd_reg_read(reg));
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reg = VIU_OSD2_PATH_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd2 path)\n",
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reg, osd_reg_read(reg));
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reg = VIU_OSD3_PATH_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x(osd3 path)\n",
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reg, osd_reg_read(reg));
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}
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}
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if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) {
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if (!osd_dev_hw.s5_display) {
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reg = OSD_PATH_MISC_CTRL;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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}
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reg = blend_reg->osd_blend_ctrl;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd_blend_din0_scope_h;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd_blend_din0_scope_v;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd_blend_din1_scope_h;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd_blend_din1_scope_v;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd_blend_din2_scope_h;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd_blend_din2_scope_v;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd_blend_din3_scope_h;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd_blend_din3_scope_v;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd_blend_dummy_data0;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd_blend_dummy_alpha;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd_blend_blend0_size;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd_blend_blend1_size;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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if (!osd_dev_hw.s5_display) {
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reg = VPP_OSD1_IN_SIZE;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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} else {
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reg = blend_reg->osd_blend_dout0_size;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd_blend_dout1_size;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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}
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reg = blend_reg->vpp_osd1_bld_h_scope;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->vpp_osd1_bld_v_scope;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->vpp_osd2_bld_h_scope;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->vpp_osd2_bld_v_scope;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->vd1_blend_src_ctrl;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->vd2_blend_src_ctrl;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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if (osd_dev_hw.display_type == T7_DISPLAY ||
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osd_dev_hw.s5_display) {
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reg = blend_reg->vd3_blend_src_ctrl;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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}
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reg = blend_reg->osd1_blend_src_ctrl;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd2_blend_src_ctrl;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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reg = blend_reg->osd_blend_ctrl1;
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osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
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if (!osd_dev_hw.s5_display) {
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reg = VPP_POSTBLEND_H_SIZE;
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|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = VPP_OUT_H_V_SIZE;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = OSD1_HDR2_MATRIXI_EN_CTRL;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = OSD1_HDR2_MATRIXO_EN_CTRL;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = VPP_OSD2_MATRIX_EN_CTRL;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
} else {
|
|
reg = S5_VPP_OUT_H_V_SIZE;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
}
|
|
/* avoid crash for reading viu2 osd regs */
|
|
if (!osd_hw.powered[count - 1] && osd_hw.osd_meson_dev.has_viu2)
|
|
count--;
|
|
}
|
|
if (osd_hw.osd_meson_dev.osd_ver == OSD_NORMAL) {
|
|
reg = VPP_OSD_SC_CTRL0;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = VPP_OSD_SCI_WH_M1;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = VPP_OSD_SCO_H_START_END;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = VPP_OSD_SCO_V_START_END;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n\n", reg, osd_reg_read(reg));
|
|
}
|
|
for (index = 0; index < count; index++) {
|
|
osd_reg = &hw_osd_reg_array[index];
|
|
reg = osd_reg->osd_fifo_ctrl_stat;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_ctrl_stat;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_ctrl_stat2;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_blk0_cfg_w0;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_blk0_cfg_w1;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_blk0_cfg_w2;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_blk0_cfg_w3;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_blk0_cfg_w4;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n\n", reg, osd_reg_read(reg));
|
|
|
|
if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE ||
|
|
osd_dev_hw.display_type == C3_DISPLAY) {
|
|
reg = osd_reg->osd_blk1_cfg_w4;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_blk2_cfg_w4;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_prot_ctrl;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_mali_unpack_ctrl;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_dimm_ctrl;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_matrix_en_ctrl;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_vsc_phase_step;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_vsc_init_phase;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_vsc_ctrl0;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_hsc_phase_step;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_hsc_init_phase;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_hsc_ctrl0;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_sc_dummy_data;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_sc_ctrl0;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_sci_wh_m1;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_sco_h_start_end;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->osd_sco_v_start_end;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n\n",
|
|
reg, osd_reg_read(reg));
|
|
}
|
|
if (osd_hw.osd_meson_dev.afbc_type == MALI_AFBC &&
|
|
osd_hw.osd_afbcd[index].enable) {
|
|
reg = osd_reg->afbc_header_buf_addr_low_s;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->afbc_header_buf_addr_high_s;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->afbc_format_specifier_s;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->afbc_buffer_width_s;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->afbc_buffer_hight_s;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->afbc_bounding_box_x_start_s;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->afbc_bounding_box_x_end_s;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->afbc_bounding_box_y_start_s;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->afbc_bounding_box_y_end_s;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->afbc_output_buf_addr_low_s;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->afbc_output_buf_addr_high_s;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->afbc_output_buf_stride_s;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = osd_reg->afbc_prefetch_cfg_s;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
}
|
|
}
|
|
|
|
if (osd_hw.osd_meson_dev.cpu_id >= __MESON_CPU_MAJOR_ID_G12B) {
|
|
if (osd_hw.osd_meson_dev.has_viu2 &&
|
|
osd_hw.powered[osd_hw.osd_meson_dev.viu2_index]) {
|
|
reg = VPP2_MISC;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VPU_VIU_VENC_MUX_CTRL;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VIU2_RMIF_CTRL1;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VIU2_RMIF_SCOPE_X;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VIU2_RMIF_SCOPE_Y;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VIU2_ROT_BLK_SIZE;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VIU2_ROT_LBUF_SIZE;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VIU2_ROT_FMT_CTRL;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VIU2_ROT_OUT_VCROP;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VPP2_OFIFO_SIZE;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
}
|
|
}
|
|
if (osd_hw.osd_meson_dev.afbc_type == MESON_AFBC) {
|
|
reg = VIU_MISC_CTRL1;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
for (reg = OSD1_AFBCD_ENABLE;
|
|
reg <= OSD1_AFBCD_PIXEL_VSCOPE; reg++)
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
} else if (osd_hw.osd_meson_dev.afbc_type == MALI_AFBC &&
|
|
!osd_dev_hw.s5_display) {
|
|
reg = OSD_PATH_MISC_CTRL;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n\n",
|
|
reg, osd_reg_read(reg));
|
|
}
|
|
|
|
if (osd_hw.osd_meson_dev.osd_ver == OSD_SIMPLE ||
|
|
osd_dev_hw.display_type == C3_DISPLAY) {
|
|
reg = hw_osd_reg_array[OSD1].osd_blk1_cfg_w4;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
|
|
reg = hw_osd_reg_array[OSD1].osd_blk2_cfg_w4;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
}
|
|
|
|
if (osd_dev_hw.display_type == T7_DISPLAY) {
|
|
osd_log_info("--- vpp1 osd ---\n");
|
|
for (reg = VPP1_BLD_CTRL; reg <= VPP1_BLD_DIN2_VSCOPE; reg++)
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VPP1_BLEND_BLEND_DUMMY_DATA;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VPP1_BLEND_DUMMY_ALPHA;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n\n",
|
|
reg, osd_reg_read(reg));
|
|
|
|
for (reg = VPP2_BLD_CTRL; reg <= VPP2_BLD_DIN2_VSCOPE; reg++)
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VPP2_BLEND_BLEND_DUMMY_DATA;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VPP2_BLEND_DUMMY_ALPHA;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
} else if (osd_dev_hw.display_type == C3_DISPLAY) {
|
|
reg = VPU_VOUT_IRQ_CTRL;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VPU_VOUT_BLEND_CTRL;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VPU_VOUT_BLEND_DUMDATA;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VPU_VOUT_BLEND_SIZE;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VPU_VOUT_BLD_SRC0_HPOS;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VPU_VOUT_BLD_SRC0_VPOS;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VPU_VOUT_BLD_SRC1_HPOS;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = VPU_VOUT_BLD_SRC1_VPOS;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
} else if (osd_dev_hw.display_type == S5_DISPLAY ||
|
|
osd_hw.osd_meson_dev.has_vpp1) {
|
|
osd_log_info("--- vpp1 osd ---\n");
|
|
for (reg = T3X_VPP1_BLEND_H_V_SIZE;
|
|
reg <= T3X_VPP1_OSD3_BLD_V_SCOPE; reg++)
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = T3X_VPP1_BLEND_BLEND_DUMMY_DATA;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = T3X_VPP1_BLEND_DUMMY_ALPHA;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n\n",
|
|
reg, osd_reg_read(reg));
|
|
reg = T3X_VPP1_BLEND_DUMMY_ALPHA1;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n\n",
|
|
reg, osd_reg_read(reg));
|
|
}
|
|
|
|
if (osd_hw.osd_meson_dev.has_slice2ppc) {
|
|
osd_log_info("--- slice2ppc ---\n");
|
|
reg = hw_osd_reg_slice2ppc.osd_2slice2ppc_in_size;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = hw_osd_reg_slice2ppc.osd_2slice2ppc_mode;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = hw_osd_reg_slice2ppc.osd_sys_hwin0_cut;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = hw_osd_reg_slice2ppc.osd_sys_hwin1_cut;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = hw_osd_reg_slice2ppc.osd_sys_pad_ctrl;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = hw_osd_reg_slice2ppc.osd_sys_pad_dummy_data0;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = hw_osd_reg_slice2ppc.osd_sys_pad_dummy_data1;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = hw_osd_reg_slice2ppc.osd_sys_pad_h_size;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = hw_osd_reg_slice2ppc.osd_sys_pad_v_size;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
reg = hw_osd_reg_slice2ppc.osd_sys_2slice_hwin_cut;
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
}
|
|
}
|
|
|
|
static void osd_debug_dump_register_region(u32 start, u32 end)
|
|
{
|
|
u32 reg = 0;
|
|
|
|
for (reg = start; reg <= end; reg += 1)
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
}
|
|
|
|
static void osd_debug_dump_register(u32 output_index, int argc, char **argv)
|
|
{
|
|
int reg_start, reg_end;
|
|
int ret;
|
|
|
|
if (!(osd_hw.osd_meson_dev.osd_ver == OSD_SIMPLE) &&
|
|
osd_hw.hw_rdma_en)
|
|
read_rdma_table(output_index);
|
|
if (argc == 3 && argv[1] && argv[2]) {
|
|
ret = kstrtoint(argv[1], 16, ®_start);
|
|
ret = kstrtoint(argv[2], 16, ®_end);
|
|
osd_debug_dump_register_region(reg_start, reg_end);
|
|
} else {
|
|
osd_debug_dump_register_all();
|
|
}
|
|
}
|
|
|
|
static void osd_debug_read_register(int argc, char **argv)
|
|
{
|
|
int reg;
|
|
int ret;
|
|
|
|
if (argc == 2 && argv[1]) {
|
|
ret = kstrtoint(argv[1], 16, ®);
|
|
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
|
|
} else {
|
|
osd_log_err("read: arg error\n");
|
|
}
|
|
}
|
|
|
|
static void osd_debug_write_register(int argc, char **argv)
|
|
{
|
|
int reg, val;
|
|
int ret;
|
|
|
|
if (argc == 3 && argv[1] && argv[2]) {
|
|
ret = kstrtoint(argv[1], 16, ®);
|
|
ret = kstrtoint(argv[2], 16, &val);
|
|
osd_reg_write(reg, val);
|
|
osd_log_info("reg[0x%x]: 0x%08x =0x%08x\n",
|
|
reg, val, osd_reg_read(reg));
|
|
} else {
|
|
osd_log_err("write: arg error\n");
|
|
}
|
|
}
|
|
|
|
static void osd_test_colorbar(void)
|
|
{
|
|
#define HHI_GCLK_OTHER 0x1054
|
|
u32 gclk_other = 0;
|
|
u32 encp_video_adv = 0;
|
|
|
|
if (osd_hw.osd_meson_dev.cpu_id <
|
|
__MESON_CPU_MAJOR_ID_SC2) {
|
|
gclk_other = osd_cbus_read(HHI_GCLK_OTHER);
|
|
encp_video_adv = osd_reg_read(ENCP_VIDEO_MODE_ADV);
|
|
|
|
/* start test mode */
|
|
osd_log_info("--- OSD TEST COLORBAR ---\n");
|
|
osd_cbus_write(HHI_GCLK_OTHER, 0xFFFFFFFF);
|
|
osd_reg_write(ENCP_VIDEO_MODE_ADV, 0);
|
|
osd_reg_write(VENC_VIDEO_TST_EN, 1);
|
|
/* TST_MODE COLORBAR */
|
|
osd_log_info("- COLORBAR -\n");
|
|
osd_reg_write(VENC_VIDEO_TST_MDSEL, 1);
|
|
msleep(OSD_TEST_DURATION);
|
|
|
|
/* TST_MODE THINLINE */
|
|
osd_log_info("- THINLINE -\n");
|
|
osd_reg_write(VENC_VIDEO_TST_MDSEL, 2);
|
|
msleep(OSD_TEST_DURATION);
|
|
/* TST_MODE DOTGRID */
|
|
osd_log_info("- DOTGRID -\n");
|
|
osd_reg_write(VENC_VIDEO_TST_MDSEL, 3);
|
|
msleep(OSD_TEST_DURATION);
|
|
|
|
/* stop test mode */
|
|
osd_cbus_write(HHI_GCLK_OTHER, gclk_other);
|
|
osd_reg_write(ENCP_VIDEO_MODE_ADV, encp_video_adv);
|
|
osd_reg_write(VENC_VIDEO_TST_EN, 0);
|
|
osd_reg_write(VENC_VIDEO_TST_MDSEL, 0);
|
|
}
|
|
}
|
|
|
|
static void osd_reset(void)
|
|
{
|
|
osd_set_free_scale_enable_hw(0, 0);
|
|
osd_enable_hw(0, 1);
|
|
}
|
|
|
|
static void osd_test_dummydata(void)
|
|
{
|
|
u32 dummy_data = 0;
|
|
|
|
dummy_data = osd_reg_read(VPP_DUMMY_DATA1);
|
|
osd_reset();
|
|
osd_log_info("--- OSD TEST DUMMYDATA ---\n");
|
|
osd_reg_write(VPP_DUMMY_DATA1, 0xFF);
|
|
msleep(OSD_TEST_DURATION);
|
|
osd_reg_write(VPP_DUMMY_DATA1, 0);
|
|
msleep(OSD_TEST_DURATION);
|
|
osd_reg_write(VPP_DUMMY_DATA1, 0xFF00);
|
|
msleep(OSD_TEST_DURATION);
|
|
osd_reg_write(VPP_DUMMY_DATA1, dummy_data);
|
|
}
|
|
|
|
static void osd_test_rect(void)
|
|
{
|
|
#ifdef CONFIG_AMLOGIC_MEDIA_GE2D
|
|
u32 x = 0;
|
|
u32 y = 0;
|
|
u32 w = 0;
|
|
u32 h = 0;
|
|
u32 color = 0;
|
|
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
|
|
struct canvas_s cs;
|
|
#endif
|
|
ulong cs_addr;
|
|
u32 cs_width, cs_height;
|
|
struct config_para_s *cfg = &ge2d_config;
|
|
struct config_para_ex_s *cfg_ex = &ge2d_config_ex;
|
|
struct ge2d_context_s *context = ge2d_context;
|
|
|
|
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
|
|
if (!(osd_hw.osd_meson_dev.osd_ver == OSD_SIMPLE)) {
|
|
canvas_read(OSD1_CANVAS_INDEX, &cs);
|
|
cs_addr = cs.addr;
|
|
cs_width = cs.width;
|
|
cs_height = cs.height;
|
|
} else {
|
|
osd_get_info(0, &cs_addr,
|
|
&cs_width, &cs_height);
|
|
}
|
|
#else
|
|
osd_get_info(0, &cs_addr,
|
|
&cs_width, &cs_height);
|
|
#endif
|
|
context = create_ge2d_work_queue();
|
|
if (!context) {
|
|
osd_log_err("create work queue error\n");
|
|
return;
|
|
}
|
|
|
|
memset(cfg, 0, sizeof(struct config_para_s));
|
|
cfg->src_dst_type = OSD0_OSD0;
|
|
cfg->src_format = GE2D_FORMAT_S32_ARGB;
|
|
cfg->src_planes[0].addr = cs_addr;
|
|
cfg->src_planes[0].w = cs_width / 4;
|
|
cfg->src_planes[0].h = cs_height;
|
|
cfg->dst_planes[0].addr = cs_addr;
|
|
cfg->dst_planes[0].w = cs_width / 4;
|
|
cfg->dst_planes[0].h = cs_height;
|
|
|
|
if (ge2d_context_config(context, cfg) < 0) {
|
|
osd_log_err("ge2d config error.\n");
|
|
return;
|
|
}
|
|
|
|
x = 0;
|
|
y = 0;
|
|
w = cs_width / 4;
|
|
h = cs_height;
|
|
color = 0x0;
|
|
osd_log_info("- BLACK -");
|
|
osd_log_info("- (%d, %d)-(%d, %d) -\n", x, y, w, h);
|
|
fillrect(context, x, y, w, h, color);
|
|
msleep(OSD_TEST_DURATION);
|
|
|
|
x = 100;
|
|
y = 0;
|
|
w = 100;
|
|
h = 100;
|
|
color = 0xFF0000FF;
|
|
osd_log_info("- RED -\n");
|
|
osd_log_info("- (%d, %d)-(%d, %d) -\n", x, y, w, h);
|
|
fillrect(context, x, y, w, h, color);
|
|
msleep(OSD_TEST_DURATION);
|
|
|
|
x += 100;
|
|
color = 0x00FF00FF;
|
|
osd_log_info("- GREEN -\n");
|
|
osd_log_info("- (%d, %d)-(%d, %d) -\n", x, y, w, h);
|
|
fillrect(context, x, y, w, h, color);
|
|
msleep(OSD_TEST_DURATION);
|
|
|
|
x += 100;
|
|
color = 0x0000FFFF;
|
|
osd_log_info("- BlUE -\n");
|
|
osd_log_info("- (%d, %d)-(%d, %d) -\n", x, y, w, h);
|
|
fillrect(context, x, y, w, h, color);
|
|
msleep(OSD_TEST_DURATION);
|
|
|
|
memset(cfg_ex, 0, sizeof(struct config_para_ex_s));
|
|
cfg_ex->src_planes[0].addr = cs_addr;
|
|
cfg_ex->src_planes[0].w = cs_width / 4;
|
|
cfg_ex->src_planes[0].h = cs_height;
|
|
cfg_ex->dst_planes[0].addr = cs_addr;
|
|
cfg_ex->dst_planes[0].w = cs_width / 4;
|
|
cfg_ex->dst_planes[0].h = cs_height;
|
|
|
|
cfg_ex->src_para.canvas_index = OSD1_CANVAS_INDEX;
|
|
cfg_ex->src_para.mem_type = CANVAS_OSD0;
|
|
cfg_ex->src_para.format = GE2D_FORMAT_S32_ARGB;
|
|
cfg_ex->src_para.fill_color_en = 0;
|
|
cfg_ex->src_para.fill_mode = 0;
|
|
cfg_ex->src_para.x_rev = 0;
|
|
cfg_ex->src_para.y_rev = 0;
|
|
cfg_ex->src_para.color = 0xffffffff;
|
|
cfg_ex->src_para.top = 0;
|
|
cfg_ex->src_para.left = 0;
|
|
cfg_ex->src_para.width = cs_width / 4;
|
|
cfg_ex->src_para.height = cs_height;
|
|
|
|
cfg_ex->dst_para.canvas_index = OSD1_CANVAS_INDEX;
|
|
cfg_ex->dst_para.mem_type = CANVAS_OSD0;
|
|
cfg_ex->dst_para.format = GE2D_FORMAT_S32_ARGB;
|
|
cfg_ex->dst_para.top = 0;
|
|
cfg_ex->dst_para.left = 0;
|
|
cfg_ex->dst_para.width = cs_width / 4;
|
|
cfg_ex->dst_para.height = cs_height;
|
|
cfg_ex->dst_para.fill_color_en = 0;
|
|
cfg_ex->dst_para.fill_mode = 0;
|
|
cfg_ex->dst_para.color = 0;
|
|
cfg_ex->dst_para.x_rev = 0;
|
|
cfg_ex->dst_para.y_rev = 0;
|
|
cfg_ex->dst_xy_swap = 0;
|
|
|
|
if (ge2d_context_config_ex(context, cfg_ex) < 0) {
|
|
osd_log_err("ge2d config error.\n");
|
|
return;
|
|
}
|
|
|
|
stretchblt(context, 100, 0, 400, 100, 100, 200, 700, 200);
|
|
|
|
destroy_ge2d_work_queue(ge2d_context);
|
|
#endif
|
|
}
|
|
|
|
static void osd_debug_auto_test(void)
|
|
{
|
|
if (!(osd_hw.osd_meson_dev.osd_ver == OSD_SIMPLE))
|
|
osd_test_colorbar();
|
|
|
|
osd_test_dummydata();
|
|
|
|
osd_test_rect();
|
|
}
|
|
|
|
char *osd_get_debug_hw(void)
|
|
{
|
|
return osd_debug_help;
|
|
}
|
|
|
|
int osd_set_debug_hw(u32 index, const char *buf)
|
|
{
|
|
int argc;
|
|
char *buffer, *p, *para;
|
|
char *argv[4];
|
|
char cmd;
|
|
u32 output_index = get_output_device_id(index);
|
|
|
|
buffer = kstrdup(buf, GFP_KERNEL);
|
|
p = buffer;
|
|
for (argc = 0; argc < 4; argc++) {
|
|
para = strsep(&p, " ");
|
|
if (!para)
|
|
break;
|
|
argv[argc] = para;
|
|
}
|
|
|
|
if (argc < 1 || argc > 4) {
|
|
kfree(buffer);
|
|
return -EINVAL;
|
|
}
|
|
|
|
cmd = argv[0][0];
|
|
switch (cmd) {
|
|
case 'i':
|
|
osd_debug_dump_value();
|
|
break;
|
|
case 'd':
|
|
osd_debug_dump_register(output_index, argc, argv);
|
|
break;
|
|
case 'r':
|
|
osd_debug_read_register(argc, argv);
|
|
break;
|
|
case 'w':
|
|
osd_debug_write_register(argc, argv);
|
|
break;
|
|
case 't':
|
|
osd_debug_auto_test();
|
|
break;
|
|
case 's':
|
|
output_save_info();
|
|
break;
|
|
case 'f':
|
|
#ifdef CONFIG_SYNC_FILE
|
|
output_fence_info();
|
|
#endif
|
|
break;
|
|
default:
|
|
osd_log_err("arg error\n");
|
|
break;
|
|
}
|
|
|
|
kfree(buffer);
|
|
return 0;
|
|
}
|