mirror of
https://github.com/hardkernel/kernel_common_drivers.git
synced 2026-06-25 12:03:48 +09:00
hao.shi
04b1f3a147
PD#SWPL-78946 Problem: Dosbus registers new management Solution: Dosbus registers new management Verify: s4 Signed-off-by: hao.shi <hao.shi@amlogic.com> Change-Id: Id729a804b336c008cf378303b79f55bb3e245388
193 lines
7.2 KiB
C
193 lines
7.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef VDEC_REG_H
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#define VDEC_REG_H
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/amlogic/media/registers/register.h>
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#include <linux/amlogic/media/registers/register_ops.h>
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#include <linux/amlogic/media/registers/register_map.h>
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#define READ_DMCREG(r) aml_read_dmcbus(r)
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#define WRITE_DMCREG(r, val) aml_write_dmcbus(r, val)
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#define READ_AOREG(r) aml_read_aobus(r)
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#define WRITE_AOREG(r, val) aml_write_aobus(r, val)
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#define READ_DOSREG(r) aml_read_dosbus(r)
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#define WRITE_DOSREG(r, val) aml_write_dosbus(r, val)
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#define BASE_IRQ 32
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#define AM_IRQ(reg) ((reg) + BASE_IRQ)
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#define INT_DOS_MAILBOX_0 AM_IRQ(43)
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#define INT_DOS_MAILBOX_1 AM_IRQ(44)
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#define INT_DOS_MAILBOX_2 AM_IRQ(45)
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#define INT_VIU_VSYNC AM_IRQ(3)
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#define INT_DEMUX AM_IRQ(23)
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#define INT_DEMUX_1 AM_IRQ(5)
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#define INT_DEMUX_2 AM_IRQ(53)
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#define INT_ASYNC_FIFO_FILL AM_IRQ(18)
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#define INT_ASYNC_FIFO_FLUSH AM_IRQ(19)
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#define INT_ASYNC_FIFO2_FILL AM_IRQ(24)
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#define INT_ASYNC_FIFO2_FLUSH AM_IRQ(25)
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#define INT_PARSER AM_IRQ(32)
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#define INT_VDEC INT_DOS_MAILBOX_1
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#define INT_VDEC2 INT_DOS_MAILBOX_0
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/*
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#define WRITE_VREG_BITS(r, val, start, len) \
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codec_set_dosbus_bits(r, val, start, len)
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#define SET_VREG_MASK(r, mask) codec_set_dosbus_mask(r, mask)
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#define CLEAR_VREG_MASK(r, mask) codec_clear_dosbus_mask(r, mask)
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#define READ_HREG(r) aml_read_dosbus((r) | 0x1000)
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#define WRITE_HREG(r, val) aml_write_dosbus((r) | 0x1000, val)
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#define WRITE_HREG_BITS(r, val, start, len) \
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codec_set_dosbus_bits((r) | 0x1000, val, start, len)
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#define SET_HREG_MASK(r, mask) codec_set_dosbus_mask((r) | 0x1000, mask)
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#define CLEAR_HREG_MASK(r, mask) codec_clear_dosbus_mask((r) | 0x1000, mask)
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*/
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/*TODO */
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#define READ_SEC_REG(r)
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#define WRITE_SEC_REG(r, val)
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#define WRITE_MPEG_REG(r, val) aml_write_cbus(r, val)
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#define READ_MPEG_REG(r) aml_read_cbus(r)
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#define WRITE_MPEG_REG_BITS(r, val, start, len) \
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codec_set_cbus_bits(r, val, start, len)
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#define CLEAR_MPEG_REG_MASK(r, mask)\
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codec_clear_cbus_mask(r, mask)
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#define SET_MPEG_REG_MASK(r, mask)\
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codec_set_cbus_mask(r, mask)
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#define WRITE_PARSER_REG(r, val) codec_parsbus_write(r, val)
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#define READ_PARSER_REG(r) codec_parsbus_read(r)
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#define WRITE_PARSER_REG_BITS(r, val, start, len) \
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codec_set_parsbus_bits(r, val, start, len)
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#define CLEAR_PARSER_REG_MASK(r, mask)\
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codec_clear_parsbus_mask(r, mask)
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#define SET_PARSER_REG_MASK(r, mask)\
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codec_set_parsbus_mask(r, mask)
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#define WRITE_HHI_REG(r, val) codec_hhibus_write(r, val)
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#define READ_HHI_REG(r) codec_hhibus_read(r)
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#define WRITE_HHI_REG_BITS(r, val, start, len) \
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codec_set_hhibus_bits(r, val, start, len)
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#define WRITE_AIU_REG(r, val) codec_aiubus_write(r, val)
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#define READ_AIU_REG(r) codec_aiubus_read(r)
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#define WRITE_AIU_REG_BITS(r, val, start, len) \
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codec_set_aiubus_bits(r, val, start, len)
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#define CLEAR_AIU_REG_MASK(r, mask)\
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codec_clear_aiubus_mask(r, mask)
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#define SET_AIU_REG_MASK(r, mask)\
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codec_set_aiubus_mask(r, mask)
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#define WRITE_DEMUX_REG(r, val) codec_demuxbus_write(r, val)
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#define READ_DEMUX_REG(r) codec_demuxbus_read(r)
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#define WRITE_DEMUX_REG_BITS(r, val, start, len) \
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codec_set_demuxbus_bits(r, val, start, len)
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#define CLEAR_DEMUX_REG_MASK(r, mask)\
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codec_clear_demuxbus_mask(r, mask)
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#define SET_DEMUX_REG_MASK(r, mask)\
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codec_set_demuxbus_mask(r, mask)
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#define WRITE_RESET_REG(r, val) codec_resetbus_write(r, val)
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#define READ_RESET_REG(r) codec_resetbus_read(r)
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#define WRITE_RESET_REG_BITS(r, val, start, len) \
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codec_set_resetbus_bits(r, val, start, len)
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#define CLEAR_RESET_REG_MASK(r, mask)\
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codec_clear_resetbus_mask(r, mask)
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#define SET_RESET_REG_MASK(r, mask)\
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codec_set_resetbus_mask(r, mask)
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#define WRITE_EFUSE_REG(r, val) codec_efusebus_write(r, val)
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#define READ_EFUSE_REG(r) codec_efusebus_read(r)
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#define WRITE_EFUSE_REG_BITS(r, val, start, len) \
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codec_set_efusebus_bits(r, val, start, len)
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#define CLEAR_EFUSE_REG_MASK(r, mask)\
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codec_clear_efusebus_mask(r, mask)
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#define SET_EFUSE_REG_MASK(r, mask)\
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codec_set_efusebus_mask(r, mask)
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#define ASSIST_MBOX1_CLR_REG VDEC_ASSIST_MBOX1_CLR_REG
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#define ASSIST_MBOX1_MASK VDEC_ASSIST_MBOX1_MASK
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#define ASSIST_AMR1_INT0 VDEC_ASSIST_AMR1_INT0
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#define ASSIST_AMR1_INT1 VDEC_ASSIST_AMR1_INT1
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#define ASSIST_AMR1_INT2 VDEC_ASSIST_AMR1_INT2
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#define ASSIST_AMR1_INT3 VDEC_ASSIST_AMR1_INT3
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#define ASSIST_AMR1_INT4 VDEC_ASSIST_AMR1_INT4
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#define ASSIST_AMR1_INT5 VDEC_ASSIST_AMR1_INT5
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#define ASSIST_AMR1_INT6 VDEC_ASSIST_AMR1_INT6
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#define ASSIST_AMR1_INT7 VDEC_ASSIST_AMR1_INT7
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#define ASSIST_AMR1_INT8 VDEC_ASSIST_AMR1_INT8
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#define ASSIST_AMR1_INT9 VDEC_ASSIST_AMR1_INT9
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/*TODO reg*/
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#define READ_VCBUS_REG(r) aml_read_vcbus(r)
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#define WRITE_VCBUS_REG(r, val) aml_write_vcbus(r, val)
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#define WRITE_VCBUS_REG_BITS(r, val, start, len)\
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codec_set_vcbus_bits(r, val, start, len)
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#define CLEAR_VCBUS_REG_MASK(r, mask)\
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codec_clear_vcbus_mask(r, mask)
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#define SET_VCBUS_REG_MASK(r, mask)\
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codec_set_vcbus_mask(r, mask)
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/****************logo relative part *****************************************/
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#define ASSIST_MBOX1_CLR_REG VDEC_ASSIST_MBOX1_CLR_REG
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#define ASSIST_MBOX1_MASK VDEC_ASSIST_MBOX1_MASK
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#define RESET_PSCALE BIT(4)
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#define RESET_IQIDCT BIT(2)
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#define RESET_MC BIT(3)
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//#define MEM_BUFCTRL_MANUAL BIT(1)
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//#define MEM_BUFCTRL_INIT BIT(0)
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#define MEM_LEVEL_CNT_BIT 18
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#define MEM_FIFO_CNT_BIT 16
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//#define MEM_FILL_ON_LEVEL BIT(10)
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//#define MEM_CTRL_EMPTY_EN BIT(2)
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//#define MEM_CTRL_FILL_EN BIT(1)
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//#define MEM_CTRL_INIT BIT(0)
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#ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
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#define VSYNC_WR_MPEG_REG(adr, val) WRITE_VCBUS_REG(adr, val)
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#define VSYNC_RD_MPEG_REG(adr) READ_VCBUS_REG(adr)
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#define VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \
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WRITE_VCBUS_REG_BITS(adr, val, start, len)
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#define VSYNC_WR_MPEG_REG_VPP1(adr, val) WRITE_VCBUS_REG(adr, val)
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#define VSYNC_RD_MPEG_REG_VPP1(adr) READ_VCBUS_REG(adr)
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#define VSYNC_WR_MPEG_REG_BITS_VPP1(adr, val, start, len) \
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WRITE_VCBUS_REG_BITS(adr, val, start, len)
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#define VSYNC_WR_MPEG_REG_VPP2(adr, val) WRITE_VCBUS_REG(adr, val)
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#define VSYNC_RD_MPEG_REG_VPP2(adr) READ_VCBUS_REG(adr)
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#define VSYNC_WR_MPEG_REG_BITS_VPP2(adr, val, start, len) \
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WRITE_VCBUS_REG_BITS(adr, val, start, len)
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#define PRE_VSYNC_WR_MPEG_REG(adr, val) WRITE_VCBUS_REG(adr, val)
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#define PRE_VSYNC_RD_MPEG_REG(adr) READ_VCBUS_REG(adr)
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#define PRE_VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \
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WRITE_VCBUS_REG_BITS(adr, val, start, len)
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#else
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int VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len);
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u32 VSYNC_RD_MPEG_REG(u32 adr);
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int VSYNC_WR_MPEG_REG(u32 adr, u32 val);
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int VSYNC_WR_MPEG_REG_BITS_VPP1(u32 adr, u32 val, u32 start, u32 len);
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u32 VSYNC_RD_MPEG_REG_VPP1(u32 adr);
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int VSYNC_WR_MPEG_REG_VPP1(u32 adr, u32 val);
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int VSYNC_WR_MPEG_REG_BITS_VPP2(u32 adr, u32 val, u32 start, u32 len);
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u32 VSYNC_RD_MPEG_REG_VPP2(u32 adr);
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int VSYNC_WR_MPEG_REG_VPP2(u32 adr, u32 val);
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int PRE_VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len);
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u32 PRE_VSYNC_RD_MPEG_REG(u32 adr);
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int PRE_VSYNC_WR_MPEG_REG(u32 adr, u32 val);
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#endif
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#endif /* VDEC_REG_H */
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