mirror of
https://github.com/hardkernel/kernel_common_drivers.git
synced 2026-06-25 12:03:48 +09:00
junyi.zhao
d86df601fb
PD#SWPL-99829 Problem: need to optimize pwm code Solution: fix clk get/set rate problem in irq add pwm get state func Verify: sc2_ah212 t7_an400 t5m_ay301 Change-Id: Ib1a2ba64c6066409bbc66b03b0bae9df89fbdcd0 Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
166 lines
4.1 KiB
C
166 lines
4.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _PWM_MESON_H
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#define _PWM_MESON_H
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#include <linux/bitops.h>
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#include <linux/export.h>
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#include <linux/io.h>
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#include <linux/mutex.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/time.h>
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#include <linux/of_address.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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/* for pwm channel index*/
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#include <dt-bindings/pwm/meson.h>
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#define MESON_NUM_PWMS 2
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#define MESON_DOUBLE_NUM_PWMS 4
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#define DEFAULT_CLK 24000000
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#define OSIN_CLK 24000000
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#define FCLK_DIV4_CLK 500000000
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#define FCLK_DIV3_CLK 667000000
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/*a group pwm registers offset address
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* for example:
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* PWM A B
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* PWM C D
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* PWM E F
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* PWM AO A
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* PWM AO B
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*/
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#define REG_PWM_A 0x0
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#define REG_PWM_B 0x4
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#define REG_MISC_AB 0x8
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#define REG_DS_AB 0xc
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#define REG_TIME_AB 0x10
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#define REG_PWM_A2 0x14
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#define REG_PWM_B2 0x18
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#define REG_BLINK_AB 0x1c
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#define PWM_LOW_MASK GENMASK(15, 0)
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#define PWM_HIGH_MASK GENMASK(31, 16)
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/* pwm output enable */
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#define MISC_A_EN BIT(0)
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#define MISC_B_EN BIT(1)
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#define MISC_A2_EN BIT(25)
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#define MISC_B2_EN BIT(24)
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/* pwm polarity enable */
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#define MISC_A_INVERT BIT(26)
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#define MISC_B_INVERT BIT(27)
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/* when you want 0% or 100% waveform
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* constant bit should be set.
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*/
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#define MISC_A_CONSTANT BIT(28)
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#define MISC_B_CONSTANT BIT(29)
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/*
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* pwm a and b clock enable/disable
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*/
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#define MISC_A_CLK_EN BIT(15)
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#define MISC_B_CLK_EN BIT(23)
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/*
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* blink control bit
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*/
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#define BLINK_A BIT(8)
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#define BLINK_B BIT(9)
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#define PWM_HIGH_SHIFT 16
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#define MISC_CLK_DIV_MASK 0x7f
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#define MISC_B_CLK_DIV_SHIFT 16
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#define MISC_A_CLK_DIV_SHIFT 8
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#define MISC_B_CLK_SEL_SHIFT 6
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#define MISC_A_CLK_SEL_SHIFT 4
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#define MISC_CLK_SEL_WIDTH 2
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#define PWM_CHANNELS_PER_GROUP 2
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#define PWM_DISABLE 0
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#define MISC_CLK_SEL_MASK 0x3
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/*
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* external clk reg field
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*/
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#define EXT_CLK_A_EN BIT(8)
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#define EXT_CLK_B_EN BIT(24)
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#define EXT_CLK_A_DIV_SHIFT 0
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#define EXT_CLK_B_DIV_SHIFT 16
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#define EXT_CLK_A_SEL_SHIFT 9
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#define EXT_CLK_B_SEL_SHIFT 25
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#define EXT_CLK_DIV_MASK 0xff
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#define EXT_CLK_SEL_MASK 0x3
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static const unsigned int mux_reg_shifts[] = {
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MISC_A_CLK_SEL_SHIFT,
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MISC_B_CLK_SEL_SHIFT,
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MISC_A_CLK_SEL_SHIFT,
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MISC_B_CLK_SEL_SHIFT
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};
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/*pwm register att*/
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struct meson_pwm_variant {
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unsigned int times;
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unsigned int constant;
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unsigned int blink_enable;
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unsigned int blink_times;
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};
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/*for soc data:
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*double channel enable
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* double_channel = false ,could use PWM A
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* double_channel = true , could use PWM A and PWM A2
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* extern_clk = false , clk div, gate, mux in pwm controller
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* extern_clk = true , clk div, gate, mux in external clk controller
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*/
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struct meson_pwm_data {
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char **parent_names;
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unsigned int num_parents;
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unsigned int double_channel;
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unsigned int extern_clk;
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};
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struct meson_pwm_channel {
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unsigned int hi;
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unsigned int lo;
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unsigned int clk_rate;
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u8 clk_div;
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u8 pre_div;
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struct clk *clk_parent;
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struct clk_mux mux;
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struct clk *clk;
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};
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struct meson_pwm {
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struct pwm_chip chip;
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struct meson_pwm_data *data;
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struct meson_pwm_channel channels[MESON_DOUBLE_NUM_PWMS];
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struct meson_pwm_variant variant;
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void __iomem *base;
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void __iomem *ext_clk_base;
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/*
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* Protects register (write) access to the REG_MISC_AB register
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* that is shared between the two PWMs.
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*/
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spinlock_t lock;
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struct regmap *regmap_base;
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};
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/*the functions only use for meson pwm driver*/
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int meson_pwm_sysfs_init(struct device *dev);
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void meson_pwm_sysfs_exit(struct device *dev);
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/*the functions use for special function in meson pwm driver*/
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int pwm_register_debug(struct meson_pwm *meson);
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struct meson_pwm *to_meson_pwm(struct pwm_chip *chip);
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int pwm_constant_enable(struct meson_pwm *meson, int index);
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int pwm_constant_disable(struct meson_pwm *meson, int index);
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int pwm_blink_enable(struct meson_pwm *meson, int index);
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int pwm_blink_disable(struct meson_pwm *meson, int index);
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int pwm_set_blink_times(struct meson_pwm *meson, int index, int value);
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int pwm_set_times(struct meson_pwm *meson, int index, int value);
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#endif /* _PWM_MESON_H_ */
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