mirror of
https://github.com/hardkernel/kernel_common_drivers.git
synced 2026-06-25 12:03:48 +09:00
yufei.huan
cfdb95cb0e
PD#SWPL-127313 Problem: move pq_api to uapi path Solution: move pq_api to uapi path Verify: verify on t5m Change-Id: I253a8fce92feb84b630ea5d1199b2b1c724b57b3 Signed-off-by: yufei.huan <yufei.huan@amlogic.com>
643 lines
18 KiB
C
643 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef AMVECM_H_
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#define AMVECM_H_
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#include <linux/types.h>
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#define _VE_CM 'C'
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#define _DI_ 'D'
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#define DNLP_SCURV_LEN 65
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#define GAIN_VAR_LUT_LEN 49
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#define WEXT_GAIN_LEN 48
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#define ADP_THRD_LEN 33
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#define REG_BLK_BOOST_LEN 13
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#define REG_ADP_OFSET_LEN 20
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#define REG_MONO_PROT_LEN 6
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#define TREND_WHT_EXP_LUT_LEN 9
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#define C_HIST_GAIN_LEN 65
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#define S_HIST_GAIN_LEN 65
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#define DNLP_PARM_MAX_NUM 100
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#define DNLP_VPP_HIST_BIN_NUM 64
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#define HDR_HIST_BIN_NUM 128
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#define HUE_HIST_BIN_NUM 32
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#define SAT_HIST_BIN_NUM 32
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#define UNKNOWN_SOURCE 0
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#define HDR10_SOURCE 1
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#define HDR10PLUS_SOURCE 2
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#define DOVI_SOURCE 3
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#define PRIMESL_SOURCE 4
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#define HLG_SOURCE 5
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#define SDR_SOURCE 6
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#define MVC_SOURCE 7
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#define CUVA_HDR_SOURCE 8
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#define CUVA_HLG_SOURCE 9
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#define MAX_SOURCE 10
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#define FREESYNC_DYNAMIC_GAMMA_NUM 10
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#define FREESYNC_DYNAMIC_GAMMA_CHANNEL 3
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/* Register table structure */
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struct am_reg_s {
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unsigned int type; /* 32-bits; 0: CBUS; 1: APB BUS... */
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unsigned int addr; /* 32-bits; Register address */
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unsigned int mask; /* 32-bits; Valid bits */
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unsigned int val; /* 32-bits; Register Value */
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};
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#define am_reg_size 900
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struct am_regs_s {
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unsigned int length; /* Length of total am_reg */
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struct am_reg_s am_reg[am_reg_size];
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};
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struct ve_hist_s {
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unsigned int sum;
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int width;
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int height;
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int ave;
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};
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struct ve_dnlp_curve_param_s {
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unsigned int ve_dnlp_scurv_low[DNLP_SCURV_LEN];
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unsigned int ve_dnlp_scurv_mid1[DNLP_SCURV_LEN];
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unsigned int ve_dnlp_scurv_mid2[DNLP_SCURV_LEN];
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unsigned int ve_dnlp_scurv_hgh1[DNLP_SCURV_LEN];
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unsigned int ve_dnlp_scurv_hgh2[DNLP_SCURV_LEN];
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unsigned int ve_gain_var_lut49[GAIN_VAR_LUT_LEN];
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unsigned int ve_wext_gain[WEXT_GAIN_LEN];
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unsigned int ve_adp_thrd[ADP_THRD_LEN];
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unsigned int ve_reg_blk_boost_12[REG_BLK_BOOST_LEN];
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unsigned int ve_reg_adp_ofset_20[REG_ADP_OFSET_LEN];
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unsigned int ve_reg_mono_protect[REG_MONO_PROT_LEN];
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unsigned int ve_reg_trend_wht_expand_lut8[TREND_WHT_EXP_LUT_LEN];
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unsigned int ve_c_hist_gain[C_HIST_GAIN_LEN];
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unsigned int ve_s_hist_gain[S_HIST_GAIN_LEN];
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unsigned int param[DNLP_PARM_MAX_NUM];
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};
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struct vpp_hist_param_s {
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unsigned int vpp_hist_pow;
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unsigned int vpp_luma_sum;
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unsigned int vpp_pixel_sum;
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unsigned short vpp_histgram[DNLP_VPP_HIST_BIN_NUM];
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unsigned short vpp_dark_hist[DNLP_VPP_HIST_BIN_NUM];
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unsigned int hdr_histgram[HDR_HIST_BIN_NUM];
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unsigned int hue_histgram[HUE_HIST_BIN_NUM];
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unsigned int sat_histgram[SAT_HIST_BIN_NUM];
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};
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struct vframe_content_light_level_ss {
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__u32 present_flag;
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__u32 max_content;
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__u32 max_pic_average;
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}; /* content_light_level from SEI */
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/* master_display_info for display device */
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struct hdr_metadata_info_s {
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__u32 primaries[3][2]; /* normalized 50000 in G,B,R order */
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__u32 white_point[2]; /* normalized 50000 */
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__u32 luminance[2]; /* max/min lumin, normalized 10000 */
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struct vframe_content_light_level_ss content_light_level;
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};
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enum color_primary_e {
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VPP_COLOR_PRI_NULL = 0,
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VPP_COLOR_PRI_BT601,
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VPP_COLOR_PRI_BT709,
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VPP_COLOR_PRI_BT2020,
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VPP_COLOR_PRI_MAX,
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};
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struct tcon_gamma_table_s {
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__u16 data[257];
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} /*tcon_gamma_table_t */;
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struct tcon_rgb_ogo_s {
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unsigned int en;
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int r_pre_offset; /* s11.0, range -1024~+1023, default is 0 */
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int g_pre_offset; /* s11.0, range -1024~+1023, default is 0 */
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int b_pre_offset; /* s11.0, range -1024~+1023, default is 0 */
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unsigned int r_gain; /* u1.10, range 0~2047, default is 1024 (1.0x) */
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unsigned int g_gain; /* u1.10, range 0~2047, default is 1024 (1.0x) */
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unsigned int b_gain; /* u1.10, range 0~2047, default is 1024 (1.0x) */
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int r_post_offset; /* s11.0, range -1024~+1023, default is 0 */
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int g_post_offset; /* s11.0, range -1024~+1023, default is 0 */
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int b_post_offset; /* s11.0, range -1024~+1023, default is 0 */
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} /*tcon_rgb_ogo_t */;
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struct gm_tbl_s {
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struct tcon_gamma_table_s gm_tb[FREESYNC_DYNAMIC_GAMMA_NUM][FREESYNC_DYNAMIC_GAMMA_CHANNEL];
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};
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enum pq_table_name_e {
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TABLE_NAME_SHARPNESS0 = 0x1,/*in vpp*/
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TABLE_NAME_SHARPNESS1 = 0x2,/*in vpp*/
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TABLE_NAME_DNLP = 0x4, /*in vpp*/
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TABLE_NAME_CM = 0x8, /*in vpp*/
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TABLE_NAME_BLK_BLUE_EXT = 0x10,/*in vpp*/
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TABLE_NAME_BRIGHTNESS = 0x20,/*in vpp*/
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TABLE_NAME_CONTRAST = 0x40, /*in vpp*/
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TABLE_NAME_SATURATION_HUE = 0x80,/*in vpp*/
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TABLE_NAME_CVD2 = 0x100, /*in tvafe*/
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TABLE_NAME_DI = 0x200, /*in di*/
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TABLE_NAME_NR = 0x400, /*in di*/
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TABLE_NAME_MCDI = 0x800, /*in di*/
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TABLE_NAME_DEBLOCK = 0x1000, /*in di*/
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TABLE_NAME_DEMOSQUITO = 0x2000,/*in di*/
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TABLE_NAME_WB = 0X4000, /*in vpp*/
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TABLE_NAME_GAMMA = 0X8000, /*in vpp*/
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TABLE_NAME_XVYCC = 0x10000, /*in vpp*/
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TABLE_NAME_HDR = 0x20000, /*in vpp*/
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TABLE_NAME_DOLBY_VISION = 0x40000,/*in vpp*/
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TABLE_NAME_OVERSCAN = 0x80000,
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TABLE_NAME_SMOOTHPLUS = 0x100000, /*in di*/
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TABLE_NAME_RESERVED2 = 0x200000,
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TABLE_NAME_RESERVED3 = 0x400000,
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TABLE_NAME_RESERVED4 = 0x800000,
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TABLE_NAME_MAX,
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};
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struct am_pq_parm_s {
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unsigned int table_name;
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unsigned int table_len;
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union {
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void *table_ptr;
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long long l_table;
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};
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union {
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void *reserved;
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long long l_reserved;
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};
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};
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struct ve_pq_load_s {
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enum pq_table_name_e param_id;
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unsigned int length;
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union {
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void *param_ptr;
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long long param_ptr_len;
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};
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union {
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void *reserved;
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long long reserved_len;
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};
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};
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enum dnlp_state_e {
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DNLP_OFF = 0,
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DNLP_ON,
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};
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enum pc_mode_e {
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PCMODE_OFF = 0,
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PCMODE_ON,
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};
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enum vpp_matrix_csc_e {
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VPP_MATRIX_NULL = 0,
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VPP_MATRIX_RGB_YUV601 = 0x1,
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VPP_MATRIX_RGB_YUV601F = 0x2,
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VPP_MATRIX_RGB_YUV709 = 0x3,
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VPP_MATRIX_RGB_YUV709F = 0x4,
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VPP_MATRIX_YUV601_RGB = 0x10,
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VPP_MATRIX_YUV601_YUV601F = 0x11,
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VPP_MATRIX_YUV601_YUV709 = 0x12,
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VPP_MATRIX_YUV601_YUV709F = 0x13,
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VPP_MATRIX_YUV601F_RGB = 0x14,
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VPP_MATRIX_YUV601F_YUV601 = 0x15,
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VPP_MATRIX_YUV601F_YUV709 = 0x16,
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VPP_MATRIX_YUV601F_YUV709F = 0x17,
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VPP_MATRIX_YUV709_RGB = 0x20,
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VPP_MATRIX_YUV709_YUV601 = 0x21,
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VPP_MATRIX_YUV709_YUV601F = 0x22,
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VPP_MATRIX_YUV709_YUV709F = 0x23,
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VPP_MATRIX_YUV709F_RGB = 0x24,
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VPP_MATRIX_YUV709F_YUV601 = 0x25,
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VPP_MATRIX_YUV709F_YUV709 = 0x26,
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VPP_MATRIX_YUV601L_YUV709L = 0x27,
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VPP_MATRIX_YUV709L_YUV601L = 0x28,
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VPP_MATRIX_YUV709F_YUV601F = 0x29,
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VPP_MATRIX_BT2020YUV_BT2020RGB = 0x40,
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VPP_MATRIX_BT2020RGB_709RGB,
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VPP_MATRIX_BT2020RGB_CUSRGB,
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VPP_MATRIX_BT2020YUV_BT2020RGB_DYNAMIC = 0x50,
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VPP_MATRIX_BT2020YUV_BT2020RGB_CUVA = 0x51,
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VPP_MATRIX_DEFAULT_CSCTYPE = 0xffff,
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};
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struct am_vdj_mode_s {
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int flag;
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int brightness;
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int brightness2;
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int saturation_hue;
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int saturation_hue_post;
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int contrast;
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int contrast2;
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int vadj1_en; /*vadj1 enable: 1 enable 0 disable*/
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int vadj2_en;
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};
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enum hdr_type_e {
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HDRTYPE_NONE = UNKNOWN_SOURCE,
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HDRTYPE_SDR = SDR_SOURCE,
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HDRTYPE_HDR10 = HDR10_SOURCE,
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HDRTYPE_HLG = HLG_SOURCE,
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HDRTYPE_HDR10PLUS = HDR10PLUS_SOURCE,
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HDRTYPE_DOVI = DOVI_SOURCE,
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HDRTYPE_MVC = MVC_SOURCE,
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HDRTYPE_CUVA_HDR = CUVA_HDR_SOURCE,
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HDRTYPE_CUVA_HLG = CUVA_HLG_SOURCE,
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HDRTYPE_PRIMESL = PRIMESL_SOURCE,
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};
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struct ve_lc_curve_parm_s {
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unsigned int ve_lc_saturation[63];
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unsigned int ve_lc_yminval_lmt[16];
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unsigned int ve_lc_ypkbv_ymaxval_lmt[16];
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unsigned int ve_lc_ymaxval_lmt[16];
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unsigned int ve_lc_ypkbv_lmt[16];
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unsigned int ve_lc_ypkbv_ratio[4];
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unsigned int param[100];
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};
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enum lut_type_e {
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HLG_LUT = 1,
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HDR_LUT = 2,
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LUT_MAX
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};
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/*tone mapping struct*/
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struct hdr_tone_mapping_s {
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enum lut_type_e lut_type;
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unsigned int lutlength;
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union {
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void *tm_lut;
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long long tm_lut_len;
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};
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};
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enum ecm_color_type {
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cm_9_color = 0,
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cm_14_color,
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cm_color_max,
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};
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enum ecm2colormode {
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ecm2colormode_purple = 0,
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ecm2colormode_red,
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ecm2colormode_skin,
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ecm2colormode_yellow,
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ecm2colormode_yellow_green,
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ecm2colormode_green,
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ecm2colormode_blue_green,
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ecm2colormode_cyan,
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ecm2colormode_blue,
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ecm2colormode_max,
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};
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enum ecm_14_color_md {
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cm_14_ecm2colormode_blue_purple = 0,
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cm_14_ecm2colormode_purple,
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cm_14_ecm2colormode_purple_red,
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cm_14_ecm2colormode_red,
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cm_14_ecm2colormode_skin_cheeks,
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cm_14_ecm2colormode_skin_hair_cheeks,
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cm_14_ecm2colormode_skin_yellow,
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cm_14_ecm2colormode_yellow,
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cm_14_ecm2colormode_yellow_green,
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cm_14_ecm2colormode_green,
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cm_14_ecm2colormode_green_cyan,
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cm_14_ecm2colormode_cyan,
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cm_14_ecm2colormode_cyan_blue,
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cm_14_ecm2colormode_blue,
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cm_14_ecm2colormode_max,
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};
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struct cm_color_md {
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enum ecm_color_type color_type;//0: 9 color; 1: 14 color
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enum ecm2colormode cm_9_color_md;
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enum ecm_14_color_md cm_14_color_md;
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int color_value;
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};
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struct vpp_pq_ctrl_s {
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unsigned int length;
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union {
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void *ptr;/*point to pq_ctrl_s*/
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long long ptr_length;
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};
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};
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enum meson_cpu_ver_e {
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VER_NULL = 0,
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VER_A,
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VER_B,
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VER_C,
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VER_MAX
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};
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struct aipq_load_s {
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unsigned int height;
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unsigned int width;
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union {
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void *table_ptr;
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long long table_len;
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};
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};
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/*G12A vpp matrix*/
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enum vpp_matrix_e {
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MTX_NULL = 0,
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VD1_MTX = 0x1,
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POST2_MTX = 0x2,
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POST_MTX = 0x4,
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VPP1_POST2_MTX = 0x8,
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VPP2_POST2_MTX = 0x10
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};
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struct matrix_coef_s {
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__u16 pre_offset[3];
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__u16 matrix_coef[3][3];
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__u16 post_offset[3];
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__u16 right_shift;
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__u16 en;
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};
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struct vpp_mtx_info_s {
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enum vpp_matrix_e mtx_sel;
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struct matrix_coef_s mtx_coef;
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};
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struct pre_gamma_table_s {
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unsigned int en;
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unsigned int lut_r[65];
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unsigned int lut_g[65];
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unsigned int lut_b[65];
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};
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/*adjust for user*/
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struct hdr_tmo_sw {
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int tmo_en; // 0 1
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int reg_highlight; //u10: control overexposure level
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int reg_hist_th; //u7
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int reg_light_th;
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int reg_highlight_th1;
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int reg_highlight_th2;
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int reg_display_e; //u10
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int reg_middle_a; //u7
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int reg_middle_a_adj; //u10
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int reg_middle_b; //u7
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int reg_middle_s; //u7
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int reg_max_th1; //u10
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int reg_middle_th; //u10
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int reg_thold1; //u10
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int reg_thold2; //u10
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int reg_thold3; //u10
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int reg_thold4; //u10
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int reg_max_th2; //u10
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int reg_pnum_th; //u16
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int reg_hl0;
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int reg_hl1; //u7
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int reg_hl2; //u7
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int reg_hl3; //u7
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int reg_display_adj; //u7
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int reg_avg_th;
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int reg_avg_adj;
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int reg_low_adj; //u7
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int reg_high_en; //u3
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int reg_high_adj1; //u7
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int reg_high_adj2; //u7
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int reg_high_maxdiff; //u7
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int reg_high_mindiff; //u7
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unsigned int alpha;
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int reg_ratio; //u10
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int reg_max_th3; //s11
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int oo_init_lut[13]; //u10
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};
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struct db_cabc_aad_param_s {
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unsigned int length;
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union {
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void *cabc_aad_param_ptr;
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long long cabc_aad_param_ptr_len;
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};
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};
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struct db_cabc_param_s {
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int cabc_param_cabc_en;
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int cabc_param_hist_mode;
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int cabc_param_tf_en;
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int cabc_param_sc_flag;
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int cabc_param_bl_map_mode;
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int cabc_param_bl_map_en;
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int cabc_param_temp_proc;
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int cabc_param_max95_ratio;
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int cabc_param_hist_blend_alpha;
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int cabc_param_init_bl_min;
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int cabc_param_init_bl_max;
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int cabc_param_tf_alpha;
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int cabc_param_sc_hist_diff_thd;
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int cabc_param_sc_apl_diff_thd;
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int cabc_param_patch_bl_th;
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int cabc_param_patch_on_alpha;
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int cabc_param_patch_bl_off_th;
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int cabc_param_patch_off_alpha;
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struct db_cabc_aad_param_s db_o_bl_cv;
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struct db_cabc_aad_param_s db_maxbin_bl_cv;
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|
};
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|
|
|
struct db_aad_param_s {
|
|
int aad_param_cabc_aad_en;
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|
int aad_param_aad_en;
|
|
int aad_param_tf_en;
|
|
int aad_param_force_gain_en;
|
|
int aad_param_sensor_mode;
|
|
int aad_param_mode;
|
|
int aad_param_dist_mode;
|
|
int aad_param_tf_alpha;
|
|
int aad_param_sensor_input[3];
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|
struct db_cabc_aad_param_s db_LUT_Y_gain;
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|
struct db_cabc_aad_param_s db_LUT_RG_gain;
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|
struct db_cabc_aad_param_s db_LUT_BG_gain;
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|
struct db_cabc_aad_param_s db_gain_lut;
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|
struct db_cabc_aad_param_s db_xy_lut;
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|
};
|
|
|
|
struct eye_protect_s {
|
|
int en;
|
|
int mtx_ep[4][4];
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|
};
|
|
|
|
/*Freerun type ioctl enum*/
|
|
enum freerun_type_e {
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|
GAME_MODE = 0,
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|
FREERUN_MODE,
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|
FREERUN_TYPE_MAX
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|
};
|
|
|
|
struct blue_str_parm_s {
|
|
int blue_stretch_en;
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|
int blue_stretch_cr_inc;
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|
int blue_stretch_cb_inc;
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|
int blue_stretch_gain;
|
|
int blue_stretch_gain_cb4cr;
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|
int blue_stretch_error_crp;
|
|
int blue_stretch_error_crp_inv;
|
|
int blue_stretch_error_crn;
|
|
int blue_stretch_error_crn_inv;
|
|
int blue_stretch_error_cbp;
|
|
int blue_stretch_error_cbp_inv;
|
|
int blue_stretch_error_cbn;
|
|
int blue_stretch_error_cbn_inv;
|
|
int blue_stretch_luma_high;
|
|
};
|
|
|
|
struct color_tune_parm_s {
|
|
int en;
|
|
int rgain_r;
|
|
int rgain_g;
|
|
int rgain_b;
|
|
|
|
int ggain_r;
|
|
int ggain_g;
|
|
int ggain_b;
|
|
|
|
int bgain_r;
|
|
int bgain_g;
|
|
int bgain_b;
|
|
|
|
int cgain_r;
|
|
int cgain_g;
|
|
int cgain_b;
|
|
|
|
int mgain_r;
|
|
int mgain_g;
|
|
int mgain_b;
|
|
|
|
int ygain_r;
|
|
int ygain_g;
|
|
int ygain_b;
|
|
};
|
|
|
|
struct primary_s {
|
|
__u32 src[8];
|
|
__u32 dest[8];
|
|
};
|
|
|
|
enum gamut_conv_enable_e {
|
|
gamut_conv_off,
|
|
gamut_conv_on,
|
|
};
|
|
|
|
struct video_color_matrix {
|
|
__u32 data[3][3];
|
|
};
|
|
|
|
struct ve_ble_whe_param_s {
|
|
int blk_adj_en;
|
|
int blk_end;
|
|
int blk_slp;
|
|
int brt_adj_en;
|
|
int brt_start;
|
|
int brt_slp;
|
|
};
|
|
|
|
#define AMVECM_IOC_G_HIST_AVG _IOW(_VE_CM, 0x22, struct ve_hist_s)
|
|
#define AMVECM_IOC_VE_DNLP_EN _IO(_VE_CM, 0x23)
|
|
#define AMVECM_IOC_VE_DNLP_DIS _IO(_VE_CM, 0x24)
|
|
#define AMVECM_IOC_VE_NEW_DNLP _IOW(_VE_CM, 0x25, struct ve_dnlp_curve_param_s)
|
|
#define AMVECM_IOC_G_HIST_BIN _IOW(_VE_CM, 0x26, struct vpp_hist_param_s)
|
|
#define AMVECM_IOC_G_HDR_METADATA _IOW(_VE_CM, 0x27, struct hdr_metadata_info_s)
|
|
/*vpp get color primary*/
|
|
#define AMVECM_IOC_G_COLOR_PRI _IOR(_VE_CM, 0x28, enum color_primary_e)
|
|
/* VPP.CM IOCTL command list */
|
|
#define AMVECM_IOC_LOAD_REG _IOW(_VE_CM, 0x30, struct am_regs_s)
|
|
/* VPP.GAMMA IOCTL command list */
|
|
#define AMVECM_IOC_GAMMA_TABLE_EN _IO(_VE_CM, 0x40)
|
|
#define AMVECM_IOC_GAMMA_TABLE_DIS _IO(_VE_CM, 0x41)
|
|
#define AMVECM_IOC_GAMMA_TABLE_R _IOW(_VE_CM, 0x42, struct tcon_gamma_table_s)
|
|
#define AMVECM_IOC_GAMMA_TABLE_G _IOW(_VE_CM, 0x43, struct tcon_gamma_table_s)
|
|
#define AMVECM_IOC_GAMMA_TABLE_B _IOW(_VE_CM, 0x44, struct tcon_gamma_table_s)
|
|
#define AMVECM_IOC_S_RGB_OGO _IOW(_VE_CM, 0x45, struct tcon_rgb_ogo_s)
|
|
#define AMVECM_IOC_G_RGB_OGO _IOR(_VE_CM, 0x46, struct tcon_rgb_ogo_s)
|
|
/*VPP.VLOCK IOCTL command list*/
|
|
#define AMVECM_IOC_VLOCK_EN _IO(_VE_CM, 0x47)
|
|
#define AMVECM_IOC_VLOCK_DIS _IO(_VE_CM, 0x48)
|
|
/*VPP.3D-SYNC IOCTL command list*/
|
|
#define AMVECM_IOC_3D_SYNC_EN _IO(_VE_CM, 0x49)
|
|
#define AMVECM_IOC_GAMMA_SET _IOW(_VE_CM, 0X4a, struct gm_tbl_s)
|
|
#define AMVECM_IOC_3D_SYNC_DIS _IO(_VE_CM, 0x50)
|
|
#define AMDI_IOC_SET_PQ_PARM _IOW(_DI_, 0x51, struct am_pq_parm_s)
|
|
#define AMVECM_IOC_SET_OVERSCAN _IOW(_VE_CM, 0x52, struct ve_pq_load_s)
|
|
/*DNLP IOCTL command list*/
|
|
#define AMVECM_IOC_G_DNLP_STATE _IOR(_VE_CM, 0x53, enum dnlp_state_e)
|
|
#define AMVECM_IOC_S_DNLP_STATE _IOW(_VE_CM, 0x54, enum dnlp_state_e)
|
|
/*PCMODE IOCTL command list*/
|
|
#define AMVECM_IOC_G_PQMODE _IOR(_VE_CM, 0x55, enum pc_mode_e)
|
|
#define AMVECM_IOC_S_PQMODE _IOW(_VE_CM, 0x56, enum pc_mode_e)
|
|
/*CUR_CSCTYPE IOCTL command list*/
|
|
#define AMVECM_IOC_G_CSCTYPE _IOR(_VE_CM, 0x57, enum vpp_matrix_csc_e)
|
|
#define AMVECM_IOC_S_CSCTYPE _IOW(_VE_CM, 0x58, enum vpp_matrix_csc_e)
|
|
/*PIC_MODE IOCTL command list*/
|
|
#define AMVECM_IOC_G_PIC_MODE _IOR(_VE_CM, 0x59, struct am_vdj_mode_s)
|
|
#define AMVECM_IOC_S_PIC_MODE _IOW(_VE_CM, 0x60, struct am_vdj_mode_s)
|
|
/*HDR TYPE command list*/
|
|
#define AMVECM_IOC_G_HDR_TYPE _IOR(_VE_CM, 0x61, enum hdr_type_e)
|
|
/*Local contrast command list*/
|
|
#define AMVECM_IOC_S_LC_CURVE _IOW(_VE_CM, 0x62, struct ve_lc_curve_parm_s)
|
|
#define AMVECM_IOC_S_HDR_TM _IOW(_VE_CM, 0x63, struct hdr_tone_mapping_s)
|
|
#define AMVECM_IOC_G_HDR_TM _IOR(_VE_CM, 0x64, struct hdr_tone_mapping_s)
|
|
#define AMVECM_IOC_S_CMS_LUMA _IOW(_VE_CM, 0x65, struct cm_color_md)
|
|
#define AMVECM_IOC_S_CMS_SAT _IOW(_VE_CM, 0x66, struct cm_color_md)
|
|
#define AMVECM_IOC_S_CMS_HUE _IOW(_VE_CM, 0x67, struct cm_color_md)
|
|
#define AMVECM_IOC_S_CMS_HUE_HS _IOW(_VE_CM, 0x68, struct cm_color_md)
|
|
#define AMVECM_IOC_S_PQ_CTRL _IOW(_VE_CM, 0x69, struct vpp_pq_ctrl_s)
|
|
#define AMVECM_IOC_G_PQ_CTRL _IOR(_VE_CM, 0x6a, struct vpp_pq_ctrl_s)
|
|
/*cpu ver ioc*/
|
|
#define AMVECM_IOC_S_MESON_CPU_VER _IOW(_VE_CM, 0x6b, enum meson_cpu_ver_e)
|
|
#define AMVECM_IOC_S_AIPQ_TABLE _IOW(_VE_CM, 0x6c, struct aipq_load_s)
|
|
#define AMVECM_IOC_SET_3D_LUT _IO(_VE_CM, 0x6d)
|
|
#define AMVECM_IOC_LOAD_3D_LUT _IO(_VE_CM, 0x6e)
|
|
#define AMVECM_IOC_SET_3D_LUT_ORDER _IO(_VE_CM, 0x6f)
|
|
#define AMVECM_IOC_S_MTX_COEF _IOW(_VE_CM, 0x70, struct vpp_mtx_info_s)
|
|
#define AMVECM_IOC_G_MTX_COEF _IOR(_VE_CM, 0x71, struct vpp_mtx_info_s)
|
|
#define AMVECM_IOC_S_PRE_GAMMA _IOW(_VE_CM, 0x72, struct pre_gamma_table_s)
|
|
#define AMVECM_IOC_G_PRE_GAMMA _IOR(_VE_CM, 0x73, struct pre_gamma_table_s)
|
|
/*hdr10_tmo ioc*/
|
|
#define AMVECM_IOC_S_HDR_TMO _IOW(_VE_CM, 0x74, struct hdr_tmo_sw)
|
|
#define AMVECM_IOC_G_HDR_TMO _IOR(_VE_CM, 0x75, struct hdr_tmo_sw)
|
|
/*cabc command list*/
|
|
#define AMVECM_IOC_S_CABC_PARAM _IOW(_VE_CM, 0x76, struct db_cabc_param_s)
|
|
/*aad command list*/
|
|
#define AMVECM_IOC_S_AAD_PARAM _IOW(_VE_CM, 0x77, struct db_aad_param_s)
|
|
#define AMVECM_IOC_S_EYE_PROT _IOW(_VE_CM, 0x78, struct eye_protect_s)
|
|
#define AMVECM_IOC_S_FREERUN_TYPE _IOW(_VE_CM, 0x79, enum freerun_type_e)
|
|
#define AMVECM_IOC_S_BLUE_STR _IOW(_VE_CM, 0x7a, struct blue_str_parm_s)
|
|
#define AMVECM_IOC_S_COLOR_TUNE _IOW(_VE_CM, 0x7b, struct color_tune_parm_s)
|
|
#define AMVECM_IOC_3D_LUT_EN _IO(_VE_CM, 0x7c)
|
|
#define AMVECM_IOC_COLOR_PRI_EN _IO(_VE_CM, 0x7d)
|
|
#define AMVECM_IOC_COLOR_PRIMARY _IOW(_VE_CM, 0x7e, struct primary_s)
|
|
#define AMVECM_IOC_S_GAMUT_CONV_EN _IOW(_VE_CM, 0x7f, enum gamut_conv_enable_e)
|
|
#define AMVECM_IOC_COLOR_MTX_EN _IO(_VE_CM, 0x80)
|
|
#define AMVECM_IOC_S_COLOR_MATRIX_DATA _IOW(_VE_CM, 0x81, struct video_color_matrix)
|
|
#define AMVECM_IOC_G_COLOR_MATRIX_DATA _IOR(_VE_CM, 0x82, struct video_color_matrix)
|
|
#define AMVECM_IOC_S_BLE_WHE _IOW(_VE_CM, 0x83, struct ve_ble_whe_param_s)
|
|
|
|
/*t7 vpp1 command list*/
|
|
#define AMVECM_IOC_S_RGB_OGO_SUB _IOW(_VE_CM, 0x84, struct tcon_rgb_ogo_s)
|
|
#define AMVECM_IOC_G_RGB_OGO_SUB _IOR(_VE_CM, 0x85, struct tcon_rgb_ogo_s)
|
|
#define AMVECM_IOC_GAMMA_TABLE_EN_SUB _IO(_VE_CM, 0x86)
|
|
#define AMVECM_IOC_GAMMA_TABLE_DIS_SUB _IO(_VE_CM, 0x87)
|
|
#define AMVECM_IOC_GAMMA_TABLE_R_SUB _IOW(_VE_CM, 0x88, struct tcon_gamma_table_s)
|
|
#define AMVECM_IOC_GAMMA_TABLE_G_SUB _IOW(_VE_CM, 0x89, struct tcon_gamma_table_s)
|
|
#define AMVECM_IOC_GAMMA_TABLE_B_SUB _IOW(_VE_CM, 0x8a, struct tcon_gamma_table_s)
|
|
|
|
#endif
|