mirror of
https://github.com/hardkernel/kernel_common_drivers.git
synced 2026-06-25 12:03:48 +09:00
haitao.liu
11a126ffde
PD#SWPL-133608 Problem: fixed some issues on projects,need sync back into trunk 1.vdin vf lost when game mode change from game 2 to game 1 cause video freezing 2.keeper failed when using scatter memory 3.The first frame of vdin1 abnormal on g12b 4.latency may unstable in game mode 5,due to CPU schedule 5.vdin write is low priority cause video abnormal in some situation 6.request memory form codec_mm may takes long time cause av out of sync 7.new feature, dmc notifier debug method 8.1440x480p60 and 1440x480p50,vdin and hdmirx repeated decimation cause video abnormal Solution: 1.recycle all vf in write mode list when game mode change 2.set the right right hand to mem_handle in vf 3.drop the first frame 4.use one fixed phy address,eliminate software scheduling effects 5.set vdin write priority to super urgent 6.notify app after codec_mm_alloc 7.add dmc notifier debug method 8.1440x480p60 and 1440x480p50,hdmirx do not notify vdin decimation, and 1440x480p60 and 1440x480p50,hdmirx do not notify vdin decimation Verify: t7/t5m Change-Id: I40d6c56fe64e389e0ee6e493e8b7d1e1503f686b Signed-off-by: haitao.liu <haitao.liu@amlogic.com>
621 lines
20 KiB
C
621 lines
20 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _TVIN_H_
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#define _TVIN_H_
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#include <linux/types.h>
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#include "amvecm_ext.h"
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/* *********************************************************************** */
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/* * TVIN general definition/enum/struct *********************************** */
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/* ************************************************************************ */
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/* tvin input port select */
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enum tvin_port_e {
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TVIN_PORT_NULL = 0x00000000,
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TVIN_PORT_MPEG0 = 0x00000100,
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TVIN_PORT_BT656 = 0x00000200,
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TVIN_PORT_BT601,
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TVIN_PORT_CAMERA,
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TVIN_PORT_BT656_HDMI,
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TVIN_PORT_BT601_HDMI,
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TVIN_PORT_CVBS0 = 0x00001000,
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TVIN_PORT_CVBS1,
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TVIN_PORT_CVBS2,
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TVIN_PORT_CVBS3,
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TVIN_PORT_HDMI0 = 0x00004000,
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TVIN_PORT_HDMI1,
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TVIN_PORT_HDMI2,
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TVIN_PORT_HDMI3,
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TVIN_PORT_HDMI4,
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TVIN_PORT_HDMI5,
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TVIN_PORT_HDMI6,
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TVIN_PORT_HDMI7,
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TVIN_PORT_HDMI_MAX,
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TVIN_PORT_DVIN0 = 0x00008000,
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TVIN_PORT_VIU1 = 0x0000a000,
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TVIN_PORT_VIU1_VIDEO, /* vpp0 preblend vd1 */
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TVIN_PORT_VIU1_WB0_VD1, /* vpp0 vadj1 output */
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TVIN_PORT_VIU1_WB0_VD2, /* vpp0 vd2 postblend input */
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TVIN_PORT_VIU1_WB0_VD3,
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TVIN_PORT_VIU1_WB0_OSD1, /* vpp0 osd1 postblend input */
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TVIN_PORT_VIU1_WB0_OSD2, /* vpp0 osd2 postblend input */
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TVIN_PORT_VIU1_WB0_OSD3,
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TVIN_PORT_VIU1_WB0_VPP, /* vpp0 output */
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TVIN_PORT_VIU1_WB0_POST_BLEND, /* vpp0 postblend output */
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TVIN_PORT_VIU1_WB1_VDIN_BIST,
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TVIN_PORT_VIU1_WB1_VIDEO,
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TVIN_PORT_VIU1_WB1_VD1,
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TVIN_PORT_VIU1_WB1_VD2,
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TVIN_PORT_VIU1_WB1_VD3,
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TVIN_PORT_VIU1_WB1_OSD1,
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TVIN_PORT_VIU1_WB1_OSD2,
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TVIN_PORT_VIU1_WB1_OSD3,
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TVIN_PORT_VIU1_WB1_VPP,
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TVIN_PORT_VIU1_WB1_POST_BLEND,
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TVIN_PORT_VIU1_MAX,
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TVIN_PORT_VIU2 = 0x0000C000,
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TVIN_PORT_VIU2_ENCL,
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TVIN_PORT_VIU2_ENCI,
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TVIN_PORT_VIU2_ENCP,
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TVIN_PORT_VIU2_VD1, /* vpp1 vd1 output */
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TVIN_PORT_VIU2_OSD1, /* vpp1 osd1 output */
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TVIN_PORT_VIU2_VPP, /* vpp1 output */
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TVIN_PORT_VIU2_MAX,
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TVIN_PORT_VIU3 = 0x0000D000,
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TVIN_PORT_VIU3_VD1, /* vpp2 vd1 output */
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TVIN_PORT_VIU3_OSD1, /* vpp2 osd1 output */
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TVIN_PORT_VIU3_VPP, /* vpp2 output */
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TVIN_PORT_VIU3_MAX,
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TVIN_PORT_VENC = 0x0000E000,
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TVIN_PORT_VENC0,
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TVIN_PORT_VENC1,
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TVIN_PORT_VENC2,
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TVIN_PORT_VENC_MAX,
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TVIN_PORT_MIPI = 0x00010000,
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TVIN_PORT_ISP = 0x00020000,
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TVIN_PORT_MAX = 0x80000000,
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};
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/* tvin signal format table */
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enum tvin_sig_fmt_e {
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TVIN_SIG_FMT_NULL = 0,
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/* HDMI Formats */
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TVIN_SIG_FMT_HDMI_640X480P_60HZ = 0x401,
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TVIN_SIG_FMT_HDMI_720X480P_60HZ = 0x402,
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TVIN_SIG_FMT_HDMI_1280X720P_60HZ = 0x403,
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TVIN_SIG_FMT_HDMI_1920X1080I_60HZ = 0x404,
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TVIN_SIG_FMT_HDMI_1440X480I_60HZ = 0x405,
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TVIN_SIG_FMT_HDMI_1440X240P_60HZ = 0x406,
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TVIN_SIG_FMT_HDMI_2880X480I_60HZ = 0x407,
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TVIN_SIG_FMT_HDMI_2880X240P_60HZ = 0x408,
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TVIN_SIG_FMT_HDMI_1440X480P_60HZ = 0x409,
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TVIN_SIG_FMT_HDMI_1920X1080P_60HZ = 0x40a,
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TVIN_SIG_FMT_HDMI_720X576P_50HZ = 0x40b,
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TVIN_SIG_FMT_HDMI_1280X720P_50HZ = 0x40c,
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TVIN_SIG_FMT_HDMI_1920X1080I_50HZ_A = 0x40d,
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TVIN_SIG_FMT_HDMI_1440X576I_50HZ = 0x40e,
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TVIN_SIG_FMT_HDMI_1440X288P_50HZ = 0x40f,
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TVIN_SIG_FMT_HDMI_2880X576I_50HZ = 0x410,
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TVIN_SIG_FMT_HDMI_2880X288P_50HZ = 0x411,
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TVIN_SIG_FMT_HDMI_1440X576P_50HZ = 0x412,
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TVIN_SIG_FMT_HDMI_1920X1080P_50HZ = 0x413,
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TVIN_SIG_FMT_HDMI_1920X1080P_24HZ = 0x414,
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TVIN_SIG_FMT_HDMI_1920X1080P_25HZ = 0x415,
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TVIN_SIG_FMT_HDMI_1920X1080P_30HZ = 0x416,
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TVIN_SIG_FMT_HDMI_2880X480P_60HZ = 0x417,
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TVIN_SIG_FMT_HDMI_2880X576P_50HZ = 0x418,
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TVIN_SIG_FMT_HDMI_1920X1080I_50HZ_B = 0x419,
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TVIN_SIG_FMT_HDMI_1920X1080I_100HZ = 0x41a,
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TVIN_SIG_FMT_HDMI_1280X720P_100HZ = 0x41b,
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TVIN_SIG_FMT_HDMI_720X576P_100HZ = 0x41c,
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TVIN_SIG_FMT_HDMI_1440X576I_100HZ = 0x41d,
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TVIN_SIG_FMT_HDMI_1920X1080I_120HZ = 0x41e,
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TVIN_SIG_FMT_HDMI_1280X720P_120HZ = 0x41f,
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TVIN_SIG_FMT_HDMI_720X480P_120HZ = 0x420,
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TVIN_SIG_FMT_HDMI_1440X480I_120HZ = 0x421,
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TVIN_SIG_FMT_HDMI_720X576P_200HZ = 0x422,
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TVIN_SIG_FMT_HDMI_1440X576I_200HZ = 0x423,
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TVIN_SIG_FMT_HDMI_720X480P_240HZ = 0x424,
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TVIN_SIG_FMT_HDMI_1440X480I_240HZ = 0x425,
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TVIN_SIG_FMT_HDMI_1280X720P_24HZ = 0x426,
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TVIN_SIG_FMT_HDMI_1280X720P_25HZ = 0x427,
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TVIN_SIG_FMT_HDMI_1280X720P_30HZ = 0x428,
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TVIN_SIG_FMT_HDMI_1920X1080P_120HZ = 0x429,
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TVIN_SIG_FMT_HDMI_1920X1080P_100HZ = 0x42a,
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TVIN_SIG_FMT_HDMI_1280X720P_60HZ_FRAME_PACKING = 0x42b,
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TVIN_SIG_FMT_HDMI_1280X720P_50HZ_FRAME_PACKING = 0x42c,
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TVIN_SIG_FMT_HDMI_1280X720P_24HZ_FRAME_PACKING = 0x42d,
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TVIN_SIG_FMT_HDMI_1280X720P_30HZ_FRAME_PACKING = 0x42e,
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TVIN_SIG_FMT_HDMI_1920X1080I_60HZ_FRAME_PACKING = 0x42f,
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TVIN_SIG_FMT_HDMI_1920X1080I_50HZ_FRAME_PACKING = 0x430,
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TVIN_SIG_FMT_HDMI_1920X1080P_24HZ_FRAME_PACKING = 0x431,
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TVIN_SIG_FMT_HDMI_1920X1080P_30HZ_FRAME_PACKING = 0x432,
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TVIN_SIG_FMT_HDMI_800X600_00HZ = 0x433,
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TVIN_SIG_FMT_HDMI_1024X768_00HZ = 0x434,
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TVIN_SIG_FMT_HDMI_720X400_00HZ = 0x435,
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TVIN_SIG_FMT_HDMI_1280X768_00HZ = 0x436,
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TVIN_SIG_FMT_HDMI_1280X800_00HZ = 0x437,
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TVIN_SIG_FMT_HDMI_1280X960_00HZ = 0x438,
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TVIN_SIG_FMT_HDMI_1280X1024_00HZ = 0x439,
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TVIN_SIG_FMT_HDMI_1360X768_00HZ = 0x43a,
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TVIN_SIG_FMT_HDMI_1366X768_00HZ = 0x43b,
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TVIN_SIG_FMT_HDMI_1600X1200_00HZ = 0x43c,
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TVIN_SIG_FMT_HDMI_1920X1200_00HZ = 0x43d,
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TVIN_SIG_FMT_HDMI_1440X900_00HZ = 0x43e,
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TVIN_SIG_FMT_HDMI_1400X1050_00HZ = 0x43f,
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TVIN_SIG_FMT_HDMI_1680X1050_00HZ = 0x440,
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/* for alternative and 4k2k */
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TVIN_SIG_FMT_HDMI_1920X1080I_60HZ_ALTERNATIVE = 0x441,
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TVIN_SIG_FMT_HDMI_1920X1080I_50HZ_ALTERNATIVE = 0x442,
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TVIN_SIG_FMT_HDMI_1920X1080P_24HZ_ALTERNATIVE = 0x443,
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TVIN_SIG_FMT_HDMI_1920X1080P_30HZ_ALTERNATIVE = 0x444,
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TVIN_SIG_FMT_HDMI_3840_2160_00HZ = 0x445,
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TVIN_SIG_FMT_HDMI_4096_2160_00HZ = 0x446,
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TVIN_SIG_FMT_HDMI_1600X900_60HZ = 0x447,
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TVIN_SIG_FMT_HDMI_RESERVE8 = 0x448,
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TVIN_SIG_FMT_HDMI_RESERVE9 = 0x449,
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TVIN_SIG_FMT_HDMI_RESERVE10 = 0x44a,
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TVIN_SIG_FMT_HDMI_RESERVE11 = 0x44b,
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TVIN_SIG_FMT_HDMI_720X480P_60HZ_FRAME_PACKING = 0x44c,
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TVIN_SIG_FMT_HDMI_720X576P_50HZ_FRAME_PACKING = 0x44d,
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TVIN_SIG_FMT_HDMI_640X480P_72HZ = 0x44e,
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TVIN_SIG_FMT_HDMI_640X480P_75HZ = 0x44f,
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TVIN_SIG_FMT_HDMI_1152X864_00HZ = 0x450,
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TVIN_SIG_FMT_HDMI_3840X600_00HZ = 0x451,
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TVIN_SIG_FMT_HDMI_720X350_00HZ = 0x452,
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TVIN_SIG_FMT_HDMI_2688X1520_00HZ = 0x453,
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TVIN_SIG_FMT_HDMI_1920X2160_60HZ = 0x454,
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TVIN_SIG_FMT_HDMI_960X540_60HZ = 0x455,
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TVIN_SIG_FMT_HDMI_2560X1440_00HZ = 0x456,
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TVIN_SIG_FMT_HDMI_640X350_85HZ = 0x457,
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TVIN_SIG_FMT_HDMI_640X400_85HZ = 0x458,
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TVIN_SIG_FMT_HDMI_848X480_60HZ = 0x459,
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TVIN_SIG_FMT_HDMI_1792X1344_85HZ = 0x45a,
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TVIN_SIG_FMT_HDMI_1856X1392_00HZ = 0x45b,
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TVIN_SIG_FMT_HDMI_1920X1440_00HZ = 0x45c,
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TVIN_SIG_FMT_HDMI_2048X1152_60HZ = 0x45d,
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TVIN_SIG_FMT_HDMI_2560X1600_00HZ = 0x45e,
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TVIN_SIG_FMT_HDMI_720X480I_60HZ = 0x45f,
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TVIN_SIG_FMT_HDMI_720X576I_50HZ = 0x460,
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TVIN_SIG_FMT_HDMI_MAX,
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TVIN_SIG_FMT_HDMI_THRESHOLD = 0x600,
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/* Video Formats */
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TVIN_SIG_FMT_CVBS_NTSC_M = 0x601,
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TVIN_SIG_FMT_CVBS_NTSC_443 = 0x602,
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TVIN_SIG_FMT_CVBS_PAL_I = 0x603,
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TVIN_SIG_FMT_CVBS_PAL_M = 0x604,
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TVIN_SIG_FMT_CVBS_PAL_60 = 0x605,
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TVIN_SIG_FMT_CVBS_PAL_CN = 0x606,
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TVIN_SIG_FMT_CVBS_SECAM = 0x607,
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TVIN_SIG_FMT_CVBS_NTSC_50 = 0x608,
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TVIN_SIG_FMT_CVBS_MAX = 0x609,
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TVIN_SIG_FMT_CVBS_THRESHOLD = 0x800,
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/* 656 Formats */
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TVIN_SIG_FMT_BT656IN_576I_50HZ = 0x801,
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TVIN_SIG_FMT_BT656IN_480I_60HZ = 0x802,
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/* 601 Formats */
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TVIN_SIG_FMT_BT601IN_576I_50HZ = 0x803,
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TVIN_SIG_FMT_BT601IN_480I_60HZ = 0x804,
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/* Camera Formats */
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TVIN_SIG_FMT_CAMERA_640X480P_30HZ = 0x805,
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TVIN_SIG_FMT_CAMERA_800X600P_30HZ = 0x806,
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TVIN_SIG_FMT_CAMERA_1024X768P_30HZ = 0x807,
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TVIN_SIG_FMT_CAMERA_1920X1080P_30HZ = 0x808,
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TVIN_SIG_FMT_CAMERA_1280X720P_30HZ = 0x809,
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TVIN_SIG_FMT_BT601_MAX = 0x80a,
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TVIN_SIG_FMT_BT601_THRESHOLD = 0xa00,
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TVIN_SIG_FMT_MAX,
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};
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/* tvin signal status */
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enum tvin_sig_status_e {
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TVIN_SIG_STATUS_NULL = 0,
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/* processing status from init to */
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/*the finding of the 1st confirmed status */
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TVIN_SIG_STATUS_NOSIG, /* no signal - physically no signal */
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TVIN_SIG_STATUS_UNSTABLE, /* unstable - physically bad signal */
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TVIN_SIG_STATUS_NOTSUP,
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/* not supported - physically good signal & not supported */
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TVIN_SIG_STATUS_STABLE,
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/* stable - physically good signal & supported */
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};
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enum tvin_trans_fmt {
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TVIN_TFMT_2D = 0,
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TVIN_TFMT_3D_LRH_OLOR,
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/* 1 Primary: Side-by-Side(Half) Odd/Left picture, Odd/Right p */
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TVIN_TFMT_3D_LRH_OLER,
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/* 2 Primary: Side-by-Side(Half) Odd/Left picture, Even/Right picture */
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TVIN_TFMT_3D_LRH_ELOR,
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/* 3 Primary: Side-by-Side(Half) Even/Left picture, Odd/Right picture */
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TVIN_TFMT_3D_LRH_ELER,
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/* 4 Primary: Side-by-Side(Half) Even/Left picture, Even/Right picture*/
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TVIN_TFMT_3D_TB, /* 5 Primary: Top-and-Bottom */
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TVIN_TFMT_3D_FP, /* 6 Primary: Frame Packing */
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TVIN_TFMT_3D_FA, /* 7 Secondary: Field Alternative */
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TVIN_TFMT_3D_LA, /* 8 Secondary: Line Alternative */
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TVIN_TFMT_3D_LRF, /* 9 Secondary: Side-by-Side(Full) */
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TVIN_TFMT_3D_LD, /* 10 Secondary: L+depth */
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TVIN_TFMT_3D_LDGD, /* 11 Secondary: L+depth+Graphics+Graphics-depth */
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/* normal 3D format */
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TVIN_TFMT_3D_DET_TB, /* 12 */
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TVIN_TFMT_3D_DET_LR, /* 13 */
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TVIN_TFMT_3D_DET_INTERLACE, /* 14 */
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TVIN_TFMT_3D_DET_CHESSBOARD, /* 15 */
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};
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enum tvin_color_fmt_e {
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TVIN_RGB444 = 0,
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TVIN_YUV422, /* 1 */
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TVIN_YUV444, /* 2 */
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TVIN_YUYV422, /* 3 */
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TVIN_YVYU422, /* 4 */
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TVIN_UYVY422, /* 5 */
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TVIN_VYUY422, /* 6 */
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TVIN_NV12, /* 7 */
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TVIN_NV21, /* 8 */
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TVIN_BGGR, /* 9 raw data */
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TVIN_RGGB, /* 10 raw data */
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TVIN_GBRG, /* 11 raw data */
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TVIN_GRBG, /* 12 raw data */
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TVIN_YUV420,
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TVIN_COLOR_FMT_MAX,
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};
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enum tvin_aspect_ratio_e {
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TVIN_ASPECT_NULL = 0,
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TVIN_ASPECT_1x1,
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TVIN_ASPECT_4x3_FULL,
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TVIN_ASPECT_14x9_FULL,
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TVIN_ASPECT_14x9_LB_CENTER,
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TVIN_ASPECT_14x9_LB_TOP,
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TVIN_ASPECT_16x9_FULL,
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TVIN_ASPECT_16x9_LB_CENTER,
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TVIN_ASPECT_16x9_LB_TOP,
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TVIN_ASPECT_MAX,
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};
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enum tvin_force_color_range_e {
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COLOR_RANGE_AUTO = 0,
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COLOR_RANGE_FULL,
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COLOR_RANGE_LIMIT,
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COLOR_RANGE_NULL,
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};
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enum tvin_scan_mode_e {
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TVIN_SCAN_MODE_NULL = 0,
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TVIN_SCAN_MODE_PROGRESSIVE,
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TVIN_SCAN_MODE_INTERLACED,
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};
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struct tvin_to_vpp_info_s {
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__u32 is_dv;
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enum tvin_scan_mode_e scan_mode;
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unsigned int fps;
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unsigned int width;
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unsigned int height;
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enum tvin_color_fmt_e cfmt;
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};
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struct tvin_info_s {
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enum tvin_trans_fmt trans_fmt;
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enum tvin_sig_fmt_e fmt;
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enum tvin_sig_status_e status;
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enum tvin_color_fmt_e cfmt;
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unsigned int fps;
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unsigned int is_dvi;
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/*
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* bit 30: is_dv
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* bit 29: present_flag
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* bit 28-26: video_format
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* "component", "PAL", "NTSC", "SECAM", "MAC", "unspecified"
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* bit 25: range "limited", "full_range"
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* bit 24: color_description_present_flag
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* bit 23-16: color_primaries
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* "unknown", "bt709", "undef", "bt601", "bt470m", "bt470bg",
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* "smpte170m", "smpte240m", "film", "bt2020"
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* bit 15-8: transfer_characteristic
|
|
* "unknown", "bt709", "undef", "bt601", "bt470m", "bt470bg",
|
|
* "smpte170m", "smpte240m", "linear", "log100", "log316",
|
|
* "iec61966-2-4", "bt1361e", "iec61966-2-1", "bt2020-10",
|
|
* "bt2020-12", "smpte-st-2084", "smpte-st-428"
|
|
* bit 7-0: matrix_coefficient
|
|
* "GBR", "bt709", "undef", "bt601", "fcc", "bt470bg",
|
|
* "smpte170m", "smpte240m", "YCgCo", "bt2020nc", "bt2020c"
|
|
*/
|
|
unsigned int signal_type;
|
|
/*
|
|
* 0:xvYCC601 1:xvYCC709 2:sYCC601 3:Adobe ycc601
|
|
* 4:Adobe rgb 5:BT2020(ycc) 6:BT2020(rgb or yuv) 7:reserved
|
|
*/
|
|
unsigned int input_colorimetry;
|
|
enum tvin_aspect_ratio_e aspect_ratio;
|
|
/*
|
|
* 0:no dv 1:visf 2:emp
|
|
*/
|
|
__u8 dolby_vision;
|
|
/*
|
|
* 0:sink-led 1:source-led
|
|
*/
|
|
__u8 low_latency;
|
|
};
|
|
|
|
struct tvin_frontend_info_s {
|
|
enum tvin_scan_mode_e scan_mode;
|
|
enum tvin_color_fmt_e cfmt;
|
|
unsigned int fps;
|
|
unsigned int width;
|
|
unsigned int height;
|
|
unsigned int colordepth;
|
|
};
|
|
|
|
struct tvin_buf_info_s {
|
|
unsigned int vf_size;
|
|
unsigned int buf_count;
|
|
unsigned int buf_width;
|
|
unsigned int buf_height;
|
|
unsigned int buf_size;
|
|
unsigned int wr_list_size;
|
|
};
|
|
|
|
struct tvin_video_buf_s {
|
|
unsigned int index;
|
|
unsigned int reserved;
|
|
};
|
|
|
|
struct tvin_parm_s {
|
|
int index; /* index of frontend for vdin */
|
|
enum tvin_port_e port; /* must set port in IOCTL */
|
|
struct tvin_info_s info;
|
|
unsigned int hist_pow;
|
|
unsigned int luma_sum;
|
|
unsigned int pixel_sum;
|
|
unsigned short histgram[64];
|
|
unsigned int flag;
|
|
unsigned short dest_width; /* for vdin horizontal scale down */
|
|
unsigned short dest_height; /* for vdin vertical scale down */
|
|
__u8 h_reverse; /* for vdin horizontal reverse */
|
|
__u8 v_reverse; /* for vdin vertical reverse */
|
|
unsigned int reserved;
|
|
};
|
|
|
|
/* ************************************************************************* */
|
|
|
|
/* *** AFE module definition/enum/struct *********************************** */
|
|
|
|
/* ************************************************************************* */
|
|
struct tvafe_vga_parm_s {
|
|
signed short clk_step; /* clock < 0, tune down clock freq */
|
|
/* clock > 0, tune up clock freq */
|
|
unsigned short phase; /* phase is 0~31, it is absolute value */
|
|
signed short hpos_step; /* hpos_step < 0, shift display to left */
|
|
/* hpos_step > 0, shift display to right */
|
|
signed short vpos_step; /* vpos_step < 0, shift display to top */
|
|
/* vpos_step > 0, shift display to bottom */
|
|
unsigned int vga_in_clean; /* flage for vga clean screen */
|
|
};
|
|
|
|
enum tvafe_cvbs_video_e {
|
|
TVAFE_CVBS_VIDEO_HV_UNLOCKED = 0,
|
|
TVAFE_CVBS_VIDEO_H_LOCKED,
|
|
TVAFE_CVBS_VIDEO_V_LOCKED,
|
|
TVAFE_CVBS_VIDEO_HV_LOCKED,
|
|
};
|
|
|
|
struct vdin_event_info {
|
|
/*enum tvin_sg_chg_flg*/
|
|
__u32 event_sts;
|
|
};
|
|
|
|
enum tvin_sync_pol_e {
|
|
TVIN_SYNC_POL_NULL = 0,
|
|
TVIN_SYNC_POL_NEGATIVE,
|
|
TVIN_SYNC_POL_POSITIVE,
|
|
};
|
|
|
|
struct tvin_format_s {
|
|
/* Th in the unit of pixel */
|
|
unsigned short h_active;
|
|
/* Tv in the unit of line */
|
|
unsigned short v_active;
|
|
/* Th in the unit of T, while 1/T = 24MHz or 27MHz or even 100MHz */
|
|
unsigned short h_cnt;
|
|
/* Tolerance of h_cnt */
|
|
unsigned short h_cnt_offset;
|
|
/* Tolerance of v_cnt */
|
|
unsigned short v_cnt_offset;
|
|
/* Ths in the unit of T, while 1/T = 24MHz or 27MHz or even 100MHz */
|
|
unsigned short hs_cnt;
|
|
/* Tolerance of hs_cnt */
|
|
unsigned short hs_cnt_offset;
|
|
/* Th in the unit of pixel */
|
|
unsigned short h_total;
|
|
/* Tv in the unit of line */
|
|
unsigned short v_total;
|
|
/* h front proch */
|
|
unsigned short hs_front;
|
|
/* HS in the unit of pixel */
|
|
unsigned short hs_width;
|
|
/* HS in the unit of pixel */
|
|
unsigned short hs_bp;
|
|
/* vs front proch in the unit of line */
|
|
unsigned short vs_front;
|
|
/* VS width in the unit of line */
|
|
unsigned short vs_width;
|
|
/* vs back proch in the unit of line */
|
|
unsigned short vs_bp;
|
|
enum tvin_sync_pol_e hs_pol;
|
|
enum tvin_sync_pol_e vs_pol;
|
|
enum tvin_scan_mode_e scan_mode;
|
|
/* (Khz/10) */
|
|
unsigned short pixel_clk;
|
|
unsigned short vbi_line_start;
|
|
unsigned short vbi_line_end;
|
|
unsigned int duration;
|
|
};
|
|
|
|
enum vdin_vrr_mode_e {
|
|
VDIN_VRR_OFF = 0,
|
|
VDIN_VRR_BASIC,
|
|
VDIN_VRR_FREESYNC,
|
|
VDIN_VRR_FREESYNC_PREMIUM,
|
|
VDIN_VRR_FREESYNC_PREMIUM_PRO,
|
|
VDIN_VRR_FREESYNC_PREMIUM_G_SYNC,
|
|
VDIN_VRR_NUM
|
|
};
|
|
|
|
struct vdin_vrr_freesync_param_s {
|
|
enum vdin_vrr_mode_e cur_vrr_status;
|
|
__u8 tone_mapping_en;
|
|
__u8 local_dimming_disable;
|
|
__u8 native_color_en;
|
|
};
|
|
|
|
struct vdin_hist_s {
|
|
__kernel_long_t sum;
|
|
int width;
|
|
int height;
|
|
int ave;
|
|
unsigned short hist[64];
|
|
};
|
|
|
|
enum port_mode {
|
|
capture_osd_plus_video = 0,
|
|
capture_only_video,
|
|
};
|
|
|
|
struct vdin_v4l2_param_s {
|
|
int width;
|
|
int height;
|
|
int fps;
|
|
enum tvin_color_fmt_e dst_fmt;
|
|
int dst_width; /* H scaling down */
|
|
int dst_height; /* v scaling down */
|
|
unsigned int bit_order; /* raw data bit order(0:none std, 1: std)*/
|
|
enum port_mode mode; /*0:osd + video 1:video only*/
|
|
int bit_dep;
|
|
__u8 secure_memory_en; /* 0:not secure memory 1:secure memory */
|
|
};
|
|
|
|
enum tvin_cn_type_e {
|
|
GRAPHICS,
|
|
PHOTO,
|
|
CINEMA,
|
|
GAME,
|
|
};
|
|
|
|
struct tvin_latency_s {
|
|
__u8 allm_mode;
|
|
__u8 it_content;
|
|
enum tvin_cn_type_e cn_type;
|
|
};
|
|
|
|
/* only for keystone use begin */
|
|
struct vdin_set_canvas_s {
|
|
int fd;
|
|
int index;
|
|
};
|
|
|
|
enum tvin_sg_chg_flg {
|
|
TVIN_SIG_CHG_NONE = 0,
|
|
TVIN_SIG_CHG_SDR2HDR = 0x01,
|
|
TVIN_SIG_CHG_HDR2SDR = 0x02,
|
|
TVIN_SIG_CHG_DV2NO = 0x04,
|
|
TVIN_SIG_CHG_NO2DV = 0x08,
|
|
TVIN_SIG_CHG_COLOR_FMT = 0x10,
|
|
TVIN_SIG_CHG_RANGE = 0x20, /*color range:full or limit*/
|
|
TVIN_SIG_CHG_BIT = 0x40, /*color bit depth: 8,10,12 ...*/
|
|
TVIN_SIG_CHG_VS_FRQ = 0x80,
|
|
TVIN_SIG_CHG_DV_ALLM = 0x100,
|
|
TVIN_SIG_CHG_AFD = 0x200,/*aspect ratio*/
|
|
TVIN_SIG_CHG_VRR = 0x1000, /*vrr*/
|
|
TVIN_SIG_CHG_CLOSE_FE = 0x40000000, /*closed frontend*/
|
|
TVIN_SIG_CHG_STS = 0x80000000, /*sm state change*/
|
|
};
|
|
|
|
#define TVIN_SIG_DV_CHG (TVIN_SIG_CHG_DV2NO | TVIN_SIG_CHG_NO2DV)
|
|
#define TVIN_SIG_HDR_CHG (TVIN_SIG_CHG_SDR2HDR | TVIN_SIG_CHG_HDR2SDR)
|
|
|
|
/* ************************************************************************* */
|
|
|
|
/* *** IOCTL command definition ******************************************* */
|
|
|
|
/* ************************************************************************* */
|
|
|
|
#define _TM_T 'T'
|
|
|
|
/* GENERAL */
|
|
#define TVIN_IOC_OPEN _IOW(_TM_T, 0x01, struct tvin_parm_s)
|
|
#define TVIN_IOC_START_DEC _IOW(_TM_T, 0x02, struct tvin_parm_s)
|
|
#define TVIN_IOC_STOP_DEC _IO(_TM_T, 0x03)
|
|
#define TVIN_IOC_CLOSE _IO(_TM_T, 0x04)
|
|
#define TVIN_IOC_G_PARM _IOR(_TM_T, 0x05, struct tvin_parm_s)
|
|
#define TVIN_IOC_S_PARM _IOW(_TM_T, 0x06, struct tvin_parm_s)
|
|
#define TVIN_IOC_G_SIG_INFO _IOR(_TM_T, 0x07, struct tvin_info_s)
|
|
#define TVIN_IOC_G_BUF_INFO _IOR(_TM_T, 0x08, struct tvin_buf_info_s)
|
|
#define TVIN_IOC_START_GET_BUF _IO(_TM_T, 0x09)
|
|
#define TVIN_IOC_G_EVENT_INFO _IOW(_TM_T, 0x0a, struct vdin_event_info)
|
|
|
|
#define TVIN_IOC_GET_BUF _IOR(_TM_T, 0x10, struct tvin_video_buf_s)
|
|
#define TVIN_IOC_PAUSE_DEC _IO(_TM_T, 0x41)
|
|
#define TVIN_IOC_RESUME_DEC _IO(_TM_T, 0x42)
|
|
#define TVIN_IOC_VF_REG _IO(_TM_T, 0x43)
|
|
#define TVIN_IOC_VF_UNREG _IO(_TM_T, 0x44)
|
|
#define TVIN_IOC_FREEZE_VF _IO(_TM_T, 0x45)
|
|
#define TVIN_IOC_UNFREEZE_VF _IO(_TM_T, 0x46)
|
|
#define TVIN_IOC_SNOW_ON _IO(_TM_T, 0x47)
|
|
#define TVIN_IOC_SNOW_OFF _IO(_TM_T, 0x48)
|
|
#define TVIN_IOC_GET_COLOR_RANGE _IOR(_TM_T, 0X49,\
|
|
enum tvin_force_color_range_e)
|
|
#define TVIN_IOC_SET_COLOR_RANGE _IOW(_TM_T, 0X4a,\
|
|
enum tvin_force_color_range_e)
|
|
#define TVIN_IOC_GAME_MODE _IOW(_TM_T, 0x4b, unsigned int)
|
|
#define TVIN_IOC_VRR_MODE _IOW(_TM_T, 0x54, unsigned int)
|
|
#define TVIN_IOC_GET_LATENCY_MODE _IOR(_TM_T, 0x4d,\
|
|
struct tvin_latency_s)
|
|
#define TVIN_IOC_G_FRONTEND_INFO _IOR(_TM_T, 0x4e,\
|
|
struct tvin_frontend_info_s)
|
|
#define TVIN_IOC_S_CANVAS_ADDR _IOW(_TM_T, 0x4f,\
|
|
struct vdin_set_canvas_s)
|
|
#define TVIN_IOC_S_PC_MODE _IOW(_TM_T, 0x50, unsigned int)
|
|
#define TVIN_IOC_S_FRAME_WR_EN _IOW(_TM_T, 0x51, unsigned int)
|
|
#define TVIN_IOC_G_INPUT_TIMING _IOR(_TM_T, 0x52, struct tvin_format_s)
|
|
#define TVIN_IOC_G_VRR_STATUS _IOR(_TM_T, 0x53, struct vdin_vrr_freesync_param_s)
|
|
#define TVIN_IOC_G_VDIN_STATUS _IOR(_TM_T, 0x54, unsigned int)
|
|
|
|
#define TVIN_IOC_S_CANVAS_RECOVERY _IO(_TM_T, 0x0a)
|
|
/* TVAFE */
|
|
#define TVIN_IOC_S_AFE_VGA_PARM _IOW(_TM_T, 0x16, struct tvafe_vga_parm_s)
|
|
#define TVIN_IOC_G_AFE_VGA_PARM _IOR(_TM_T, 0x17, struct tvafe_vga_parm_s)
|
|
#define TVIN_IOC_S_AFE_VGA_AUTO _IO(_TM_T, 0x18)
|
|
#define TVIN_IOC_G_AFE_CVBS_LOCK _IOR(_TM_T, 0x1a, enum tvafe_cvbs_video_e)
|
|
#define TVIN_IOC_S_AFE_CVBS_STD _IOW(_TM_T, 0x1b, enum tvin_sig_fmt_e)
|
|
#define TVIN_IOC_CALLMASTER_SET _IOW(_TM_T, 0x1c, enum tvin_port_e)
|
|
#define TVIN_IOC_CALLMASTER_GET _IO(_TM_T, 0x1d)
|
|
#define TVIN_IOC_G_AFE_CVBS_STD _IOW(_TM_T, 0x1e, enum tvin_sig_fmt_e)
|
|
#define TVIN_IOC_LOAD_REG _IOW(_TM_T, 0x20, struct am_regs_s)
|
|
#define TVIN_IOC_S_AFE_SNOW_ON _IO(_TM_T, 0x22)
|
|
#define TVIN_IOC_S_AFE_SNOW_OFF _IO(_TM_T, 0x23)
|
|
#define TVIN_IOC_G_VDIN_HIST _IOW(_TM_T, 0x24, struct vdin_hist_s)
|
|
#define TVIN_IOC_S_VDIN_V4L2START _IOW(_TM_T, 0x25, struct vdin_v4l2_param_s)
|
|
#define TVIN_IOC_S_VDIN_V4L2STOP _IO(_TM_T, 0x26)
|
|
#define TVIN_IOC_S_AFE_SNOW_CFG _IOW(_TM_T, 0x27, unsigned int)
|
|
#define TVIN_IOC_S_DV_DESCRAMBLE _IOW(_TM_T, 0x28, unsigned int)
|
|
#define TVIN_IOC_S_AFE_ATV_SEARCH _IOW(_TM_T, 0x29, unsigned int)
|
|
|
|
#endif
|
|
|