zhou.han 16f6ad368d hdmitx: Optimize the hdmitx clk source switching process [2/2] ...

PD#SWPL-174933

Problem:
hdmitx encp/pixel clk is directly configured by the pll analog path.

Solution:
Add flag: clk_analog_path, which is 1 by default.
1:Analog frequency division
0:Digital frequency division

Verify:
s7d/s7

Test:
DRM-TX-78

Change-Id: I22e58995b7e073e7458531827ea9bb360402e058
Signed-off-by: zhou.han <zhou.han@amlogic.com>

2025-01-01 22:57:36 -08:00

..

algorithm

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media

hdmitx: Optimize the hdmitx clk source switching process [2/2]

2025-01-01 22:57:36 -08:00

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