Files
kernel_common_drivers/drivers
Chuan Liu dfb83bfa5b clk: s6: Update the axi_clk register bits definition [1/1]
PD#SWPL-183185

Problem:
VLSI updated the axi_clk register bits definition in the document.

Solution:
Fixed

Verify:
s6_bl201

Change-Id: Ibb3e5f9c5a8d7cfce58932568f26ae3dc80e4c3c
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
2024-08-29 19:03:07 +08:00
..
2024-08-05 19:59:07 +08:00
2024-06-13 13:31:48 +08:00
2022-02-22 11:00:37 +08:00
2023-01-04 01:07:19 -08:00
2022-12-26 03:25:43 -08:00
2024-08-22 21:24:30 +08:00
2024-08-08 16:14:25 +08:00
2024-08-28 17:02:14 +08:00
2024-07-18 20:30:33 +08:00
2024-08-22 14:07:34 +08:00
2024-07-13 20:53:28 +08:00
2024-07-13 19:16:37 +08:00
2024-08-20 14:29:09 +08:00
2024-02-19 20:34:48 +08:00