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https://github.com/hardkernel/kernel_common_drivers.git
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yiting.deng
f1b6d97729
PD#SWPL-149396 Problem: a4 and a5 rtc bringup Solution: a4 and a5 rtc bringup Verify: a4_ba400 a5_av400 Change-Id: I6b12773cffcbee522d4c8d0152fea1df5ad1f497 Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
72 lines
2.7 KiB
C
72 lines
2.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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/*******************************************************************/
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#include <linux/types.h>
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#include <linux/mailbox_client.h>
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/* RTC_CTRL Bit[8]: 0 - select 32K oscillator, 1 - select 24M oscillator */
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#define RTC_OSC_SEL_BIT (8)
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/* RTC_CTRL Bit[12]: 0 - disable rtc, 1 - enable rtc */
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#define RTC_ENABLE_BIT (12)
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/* RTC_CTRL Bit[3:0]: 0 - disable rtc alarm, 1 - enable rtc alarm */
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#define RTC_ALRM0_EN_BIT (0)
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#define RTC_ALRM1_EN_BIT (1)
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#define RTC_ALRM2_EN_BIT (2)
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#define RTC_ALRM3_EN_BIT (3)
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/* RTC_INT_MASK Bit[3:0]: 0 - enable alarm irq, 1 - disable alarm irq */
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#define RTC_ALRM0_IRQ_MSK_BIT (0)
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#define RTC_ALRM1_IRQ_MSK_BIT (1)
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#define RTC_ALRM2_IRQ_MSK_BIT (2)
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#define RTC_ALRM3_IRQ_MSK_BIT (3)
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/* RTC_INT_STATUS Bit[7:4]: 0 - alarm is disable, 1 - alarm is enable */
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#define RTC_ALRM0_STATUS_BIT (4)
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#define RTC_ALRM1_STATUS_BIT (5)
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#define RTC_ALRM2_STATUS_BIT (6)
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#define RTC_ALRM3_STATUS_BIT (7)
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/* RTC_INT_STATUS Bit[3:0]: 0 - alarm irq triggered, 1 - alarm irq triggered */
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#define RTC_ALRM0_IRQ_STATUS_BIT (0)
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#define RTC_ALRM1_IRQ_STATUS_BIT (1)
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#define RTC_ALRM2_IRQ_STATUS_BIT (2)
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#define RTC_ALRM3_IRQ_STATUS_BIT (3)
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/* RTC_INT_CLR Bit[3:0]: software write “1” to clean alarm irq, hardware self clear to 0 */
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#define RTC_ALRM0_CLR_STATUS_BIT (0)
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#define RTC_ALRM1_CLR_STAUTS_BIT (1)
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#define RTC_ALRM2_CLR_STATUS_BIT (2)
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#define RTC_ALRM3_CLR_STAUTS_BIT (3)
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/* RTC register address offset */
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#define RTC_CTRL (0) /* Control RTC -RW*/
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#define RTC_COUNTER_REG BIT(2) /* Program RTC counter initial value -RW*/
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#define RTC_ALARM0_REG (2 << 2) /* Program RTC alarm0 value -RW*/
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#define RTC_ALARM1_REG (3 << 2) /* Program RTC alarm1 value -RW*/
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#define RTC_ALARM2_REG (4 << 2) /* Program RTC alarm2 value -RW*/
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#define RTC_ALARM3_REG (5 << 2) /* Program RTC alarm3 value -RW*/
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#define RTC_SEC_ADJUST_REG (6 << 2) /* Control second-based timing adjustment -RW*/
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#define RTC_WIDEN_VAL (7 << 2) /* Cross clock domain widen val -RW*/
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#define RTC_INT_MASK (8 << 2) /* RTC interrupt mask -RW*/
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#define RTC_INT_CLR (9 << 2) /* Clear RTC interrupt -RW*/
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#define RTC_OSCIN_CTRL0 (10 << 2)/* Control RTC clk from 24M -RW*/
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#define RTC_OSCIN_CTRL1 (11 << 2)/* Control RTC clk from 24M -RW*/
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#define RTC_INT_STATUS (12 << 2)/* RTC interrupt status -R*/
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#define RTC_REAL_TIME (13 << 2)/* RTC counter value -R*/
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enum meson_rtc_adj {
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ADJUST_NONE = 0,
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ADJUST_DROP = 1,
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ADJUST_INSERT = 2,
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ADJUST_MAX = 3,
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};
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struct meson_rtc_data {
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void __iomem *reg_base;
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struct rtc_device *rtc_dev;
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struct mbox_chan *mbox_chan;
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bool alarm_enabled;
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int irq;
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u32 freq;
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bool time_storage_format;
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};
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