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8df10c037a
PD#SWPL-172965 Problem: 1 Lost mclk and aclkm clocks 2 Discard meson_clk_pll_v3_ops 3 clk_measure table has been updated 4 hifipll and gp0pll cannot be locked 5 Optimize clock naming Solution: 1 Added mclk and aclkm clocks 2 Replace meson_clk_pll_v3_ops with meson_clk_pll_v4_ops 3 Updated hifipll and gp0pll configuration timing Verify: s6_bl201 Change-Id: Ia5407b3b529c38a241e0a038aad371b5822c0c02 Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>