Chuan Liu 7bde3bb83b clk: s7d: Fix clock issue [1/1] ...

PD#SWPL-163050

Problem:
1 The parent of cecb and hcodec is incorrect
2 The vclk2_div register is incorrectly defined
3 no glitch mux does not work properly under certain circumstances

Solution:
1 Fixed
2 Fixed
3 Add CLK_OPS_PARENT_ENABLE to mux whose model is no glitch mux to
ensure that mux0 is enabled during mux switchover

Verify:
s7d_bm209

Change-Id: Ib78e899f7f1a93e1b9db6860c093dd28f1246491
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>

2024-04-17 19:31:21 +08:00

..

aml_cpufreq_v2.c

clk: s7d: Fix clock issue [1/1]

2024-04-17 19:31:21 +08:00

aml_cpufreq_v2.h

cpufreq: s7d dvfs bringup [1/1]

2024-04-17 19:31:21 +08:00

Kconfig

cpufreq: porting cpufreq driver [1/1]

2021-12-30 10:01:59 +08:00

main.c

cpufreq: dvfs bringup of s7 [1/1]

2024-01-22 12:48:45 +08:00

main.h

cpufreq: dvfs bringup of s7 [1/1]

2024-01-22 12:48:45 +08:00

Makefile

cpufreq: dvfs bringup of s7 [1/1]

2024-01-22 12:48:45 +08:00

meson-cpufreq.c

cpufreq: dvfs bringup of s7 [1/1]

2024-01-22 12:48:45 +08:00

meson-cpufreq.h

dvfs: align cpu frequency in big little clusters [1/1]

2023-06-06 20:58:48 -07:00