mirror of
https://github.com/hardkernel/kernel_common_drivers.git
synced 2026-06-25 12:03:48 +09:00
Long
6a35454196
PD#SWPL-152701 Problem: Currently,we found that the Sanitize/Erase command may take longer than that on the first factory reset after flashing. This will cause the Sanitize/Erase command to timeout before completing. Solution: Enable max timeout in the eMMC controller only for Sanitize. This will allow the factory reset command to always complete successfully with the drawback that on eMMC failures, the device will be stuck unless rebooted. Verify: T5d Change-Id: Ifea2edfe758b2f723f2c02d369468e8ba9629fe3 Signed-off-by: Long <long.yu@amlogic.com>
559 lines
14 KiB
C
559 lines
14 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __AML_SD_H__
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#define __AML_SD_H__
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#include <linux/mmc/card.h>
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#include <linux/interrupt.h>
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/* unknown */
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#define CARD_TYPE_UNKNOWN 0
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/* MMC card */
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#define CARD_TYPE_MMC 1
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/* SD card */
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#define CARD_TYPE_SD 2
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/* SDIO card */
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#define CARD_TYPE_SDIO 3
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/* SD combo (IO+mem) card */
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#define CARD_TYPE_SD_COMBO 4
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/* NON sdio device (means SD/MMC card) */
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#define CARD_TYPE_NON_SDIO 5
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#define aml_card_type_unknown(c) ((c)->card_type == CARD_TYPE_UNKNOWN)
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#define aml_card_type_mmc(c) ((c)->card_type == CARD_TYPE_MMC)
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#define aml_card_type_sd(c) ((c)->card_type == CARD_TYPE_SD)
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#define aml_card_type_sdio(c) ((c)->card_type == CARD_TYPE_SDIO)
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#define aml_card_type_non_sdio(c) ((c)->card_type == CARD_TYPE_NON_SDIO)
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#define EMMC_CMD_FALLING_SML BIT(0)
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#define EMMC_CMD_RISING_SML BIT(1)
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#define EMMC_CMD_CORE_CLK_SML BIT(2)
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#define EMMC_CMD_SD_CLK_SML BIT(3)
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#define EMMC_CMD_LINE_DELAY_MODE BIT(0)
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#define EMMC_CMD_RX_DELAY_MODE BIT(1)
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/* flag is "@ML" */
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#define TUNED_FLAG 0x004C4D40
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/* version is "V1" */
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#define TUNED_VERSION 0x00003156
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/* magic is 0x00487e44 */
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#define TUNED_MAGIC 0x00487e44
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#define MMC_DEVICES_NUM 2
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#define MMC_MULT_DEV_SEQ_SD 1
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#define MMC_MULT_DEV_SEQ_SDIO 2
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struct mmc_phase {
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unsigned int core_phase;
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unsigned int tx_phase;
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unsigned int rx_phase;
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unsigned int tx_delay;
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};
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struct para_e {
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struct mmc_phase init;
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struct mmc_phase hs;
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struct mmc_phase hs2;
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struct mmc_phase hs4;
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struct mmc_phase sdr;
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};
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#define LATCHING_RXPHASE 0
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#define LATCHING_TXPHASE 1
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#define LATCHING_FIXADJ 2
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struct meson_mmc_data {
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unsigned int tx_delay_mask;
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unsigned int rx_delay_mask;
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unsigned int always_on;
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unsigned int adjust;
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u8 latching_mode;
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};
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enum aml_host_bus_fsm { /* Host bus fsm status */
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BUS_FSM_IDLE, /* 0, idle */
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BUS_FSM_SND_CMD, /* 1, send cmd */
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BUS_FSM_CMD_DONE, /* 2, wait for cmd done */
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BUS_FSM_RESP_START, /* 3, resp start */
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BUS_FSM_RESP_DONE, /* 4, wait for resp done */
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BUS_FSM_DATA_START, /* 5, data start */
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BUS_FSM_DATA_DONE, /* 6, wait for data done */
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BUS_FSM_DESC_WRITE_BACK,/* 7, wait for desc write back */
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BUS_FSM_IRQ_SERVICE, /* 8, wait for irq service */
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};
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struct sd_emmc_desc {
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u32 cmd_cfg;
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u32 cmd_arg;
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u32 cmd_data;
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u32 cmd_resp;
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};
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struct meson_mmc_hole {
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u8 start;
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u8 size;
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};
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struct hs400_para {
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unsigned int delay1;
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unsigned int delay2;
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unsigned int intf3;
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unsigned int flag;
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};
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struct hs200_para {
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unsigned int adjust;
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};
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struct hs_para {
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unsigned int adjust;
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};
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struct aml_tuning_para {
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unsigned int chip_id[4];
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unsigned int magic;
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unsigned int vddee;
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struct hs400_para hs4[7];
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struct hs200_para hs2;
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struct hs_para hs;
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unsigned int version;
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unsigned int busmode;
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unsigned int update;
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int temperature;
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long long checksum;
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};
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struct meson_host {
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struct device *dev;
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struct meson_mmc_data *data;
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struct mmc_host *mmc;
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struct mmc_command *cmd;
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struct delayed_work dtbkey;
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void __iomem *regs;
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void __iomem *pin_mux_base;
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void __iomem *clk_tree_base;
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struct resource *res[3];
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struct clk *core_clk;
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struct clk *tx_clk;
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struct clk *mmc_clk;
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struct clk *mux[3];
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struct clk *mux_div;
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struct clk *clk[3];
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unsigned long req_rate;
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unsigned char timing;
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bool ddr;
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bool dram_access_quirk;
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_default;
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struct pinctrl_state *pins_clk_gate;
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unsigned int bounce_buf_size;
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void *bounce_buf;
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dma_addr_t bounce_dma_addr;
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struct sd_emmc_desc *descs;
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dma_addr_t descs_dma_addr;
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int irq;
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bool vqmmc_enabled;
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struct para_e sd_mmc;
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char is_tuning;
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unsigned int delay_cell;
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bool needs_pre_post_req;
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int sd_sdio_switch_volat_done;
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int irq_sdio_sleep;
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int sdio_irqen;
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unsigned int emmc_boot_base;
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u32 pin_mux_val;
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u32 clk_tree_val;
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u32 host_clk_val;
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int debug_flag;
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unsigned int card_type;
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unsigned int card_insert;
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u8 fixadj_have_hole;
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struct meson_mmc_hole hole[3];
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u8 fix_hole;
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u64 align[10];
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char cmd_retune;
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unsigned int win_start;
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u8 *blk_test;
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u8 *adj_win;
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unsigned int cmd_c;
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int cd_irq;
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irqreturn_t (*cd_gpio_isr)(int irq, void *dev_id);
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int is_uart;
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int sd_uart_init;
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int first_temp_index;
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int cur_temp_index;
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int compute_cmd_delay;
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int compute_coef;
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unsigned int save_para;
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unsigned int src_clk_rate;
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struct aml_tuning_para para;
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int run_pxp_flag;
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int nwr_cnt;
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bool auto_clk;
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bool ignore_desc_busy;
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bool use_intf3_tuning;
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bool enable_hwcq;
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int flags;
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spinlock_t lock; /* lock for claim and bus ops */
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bool src_clk_cfg_done;
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bool tdma;
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bool sd_clk_sample;
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struct dentry *debugfs_root;
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struct clk *src_clk;
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unsigned int f_min;
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unsigned int f_max;
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struct completion drv_completion;
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};
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struct amlsd_platform {
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struct meson_host *host;
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struct mmc_host *mmc;
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struct list_head sibling;
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struct para_e sd_mmc;
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u32 ocr_avail;
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u32 port;
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u32 debug_flag;
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unsigned long req_rate;
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struct clk *src_clk;
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struct pinctrl_state *pins_default;
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struct pinctrl_state *pins_clk_gate;
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unsigned char timing;
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bool vqmmc_enabled;
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bool auto_clk;
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bool ddr;
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bool ignore_desc_busy;
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unsigned int card_insert;
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int is_uart;
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unsigned int src_clk_rate;
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char is_tuning;
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struct delayed_work cd_detect;
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unsigned int caps;
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unsigned int caps2;
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unsigned int pm_caps;
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unsigned int card_capacity;
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unsigned int tx_phase;
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unsigned int tx_delay;
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unsigned int runtime;
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unsigned int save_para;
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unsigned int co_phase;
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unsigned int f_min;
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unsigned int f_max;
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unsigned int clkc;
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unsigned int clk2;
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unsigned int clkc_w;
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unsigned int ctrl;
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unsigned int adj;
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unsigned int dly1;
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unsigned int dly2;
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unsigned int intf3;
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unsigned int win_start;
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unsigned int irq_sdio_sleep;
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unsigned int clock;
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/* signalling voltage (1.8V or 3.3V) */
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unsigned char signal_voltage;
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int bus_width;
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int bl_len;
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int stop_clk;
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unsigned int irq_cd;
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unsigned int gpio_cd;
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unsigned int gpio_cd_level;
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unsigned int gpio_cd_sta;
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unsigned int gpio_power;
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unsigned int power_mode;
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unsigned int no_sduart;
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unsigned int scan_val;
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unsigned int vol_switch;
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unsigned int vol_switch_18;
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unsigned int vol_switch_delay;
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unsigned int gpio_ro;
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unsigned int gpio_trigger;
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unsigned int gpio_dat3;
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unsigned int hw_reset;
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unsigned int jtag_pin;
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int is_sduart;
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unsigned int card_in_delay;
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bool is_in;
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/* 0:unknown, 1:mmc card(include eMMC), 2:sd card(include tSD),
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* 3:sdio device(ie:sdio-wifi), 4:SD combo (IO+mem) card,
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* 5:NON sdio device(means sd/mmc card), other:reserved
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*/
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unsigned int card_type;
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unsigned int max_blk_count;
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unsigned int max_blk_size;
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unsigned int max_req_size;
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unsigned int max_seg_size;
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};
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struct wifi_clk_table {
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char m_wifi_name[20];
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unsigned short m_use_flag;
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unsigned short m_device_id;
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unsigned int m_uhs_max_dtr;
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};
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enum wifi_clk_table_e {
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WIFI_CLOCK_TABLE_8822BS = 0,
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WIFI_CLOCK_TABLE_8822CS = 1,
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WIFI_CLOCK_TABLE_QCA6174 = 2,
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WIFI_CLOCK_TABLE_MAX,
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};
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void sdio_reinit(void);
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const char *get_wifi_inf(void);
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int sdio_get_vendor(void);
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void aml_host_bus_fsm_show(struct mmc_host *mmc, int status);
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extern struct mmc_host *sdio_host;
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#define DRIVER_NAME "meson-gx-mmc"
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#define G12A_DRIVER_NAME "meson-g12a-mmc"
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#if CONFIG_AMLOGIC_KERNEL_VERSION == 13515
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void mmc_sd_update_cmdline_timing(void *data, struct mmc_card *card, int *err);
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void mmc_sd_update_dataline_timing(void *data, struct mmc_card *card, int *err);
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#define SD_CMD_TIMING mmc_sd_update_cmdline_timing
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#define SD_DATA_TIMING mmc_sd_update_dataline_timing
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#endif
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#define SD_EMMC_CLOCK 0x0
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#define CLK_DIV_MASK GENMASK(5, 0)
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#define CLK_SRC_MASK GENMASK(7, 6)
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#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
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#define CLK_TX_PHASE_MASK GENMASK(11, 10)
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#define CLK_RX_PHASE_MASK GENMASK(13, 12)
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#define CLK_PHASE_0 0
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#define CLK_PHASE_180 2
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#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
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#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
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#define CLK_V2_ALWAYS_ON BIT(24)
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#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
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#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
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#define CLK_V3_ALWAYS_ON BIT(28)
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#define CFG_IRQ_SDIO_SLEEP BIT(29)
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#define CFG_IRQ_SDIO_SLEEP_DS BIT(30)
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#define CLK_TX_DELAY_MASK(h) ((h)->data->tx_delay_mask)
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#define CLK_RX_DELAY_MASK(h) ((h)->data->rx_delay_mask)
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#define CLK_ALWAYS_ON(h) ((h)->data->always_on)
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#define SD_EMMC_DELAY 0x4
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#define SD_EMMC_ADJUST 0x8
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#define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)
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#define ADJUST_DS_EN BIT(15)
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#define ADJUST_ADJ_EN BIT(13)
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#define SD_EMMC_DELAY1 0x4
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#define SD_EMMC_DELAY2 0x8
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#define DELAY2_CMD_MASK GENMASK(29, 24)
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#define SD_EMMC_V3_ADJUST 0xc
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#define CALI_SEL_MASK GENMASK(11, 8)
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#define CALI_ENABLE BIT(12)
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#define CFG_ADJUST_ENABLE BIT(13)
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#define CALI_RISE BIT(14)
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#define DS_ENABLE BIT(15)
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#define CLK_ADJUST_DELAY GENMASK(21, 16)
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#define ADJ_AUTO BIT(22)
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#define SD_EMMC_CALOUT 0x10
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#define SD_EMMC_ADJ_IDX_LOG 0x20
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#define SD_EMMC_CLKTEST_LOG 0x24
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#define CLKTEST_TIMES_MASK GENMASK(30, 0)
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#define CLKTEST_DONE BIT(31)
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#define SD_EMMC_CLKTEST_OUT 0x28
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#define SD_EMMC_EYETEST_LOG 0x2c
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#define EYETEST_TIMES_MASK GENMASK(30, 0)
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#define EYETEST_DONE BIT(31)
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#define SD_EMMC_EYETEST_OUT0 0x30
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#define SD_EMMC_EYETEST_OUT1 0x34
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#define SD_EMMC_INTF3 0x38
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#define CLKTEST_EXP_MASK GENMASK(4, 0)
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#define CLKTEST_ON_M BIT(5)
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#define EYETEST_EXP_MASK GENMASK(10, 6)
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#define EYETEST_ON BIT(11)
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#define DS_SHT_M_MASK GENMASK(17, 12)
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#define DS_SHT_EXP_MASK GENMASK(21, 18)
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#define SD_INTF3 BIT(22)
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#define EYETEST_SEL BIT(26)
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#define RESP_SEL BIT(27)
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#define CFG_RX_SEL BIT(26)
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#define CFG_RX_PN BIT(27)
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#define RESP_OLD BIT(28)
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#define RESP_PN BIT(29)
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#define RESP_DS BIT(30)
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#define SD_EMMC_START 0x40
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#define START_DESC_INIT BIT(0)
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#define START_DESC_BUSY BIT(1)
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#define START_DESC_ADDR_MASK GENMASK(31, 2)
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#define SD_EMMC_CFG 0x44
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#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
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#define CFG_BUS_WIDTH_1 0x0
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#define CFG_BUS_WIDTH_4 0x1
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#define CFG_BUS_WIDTH_8 0x2
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#define CFG_DDR BIT(2)
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#define CFG_BLK_LEN_MASK GENMASK(7, 4)
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#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
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#define CFG_RC_CC_MASK GENMASK(15, 12)
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#define CFG_STOP_CLOCK BIT(22)
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#define CFG_CLK_ALWAYS_ON BIT(18)
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#define CFG_CHK_DS BIT(20)
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#define CFG_AUTO_CLK BIT(23)
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#define CFG_ERR_ABORT BIT(27)
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#define SD_EMMC_STATUS 0x48
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#define STATUS_BUSY BIT(31)
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#define STATUS_DESC_BUSY BIT(30)
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#define STATUS_DATI GENMASK(23, 16)
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#define SD_EMMC_IRQ_EN 0x4c
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#define IRQ_RXD_ERR_MASK GENMASK(7, 0)
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#define IRQ_TXD_ERR BIT(8)
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#define IRQ_DESC_ERR BIT(9)
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#define IRQ_RESP_ERR BIT(10)
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#define IRQ_CRC_ERR \
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(IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
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#define IRQ_RESP_TIMEOUT BIT(11)
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#define IRQ_DESC_TIMEOUT BIT(12)
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#define IRQ_TIMEOUTS \
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(IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
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#define IRQ_END_OF_CHAIN BIT(13)
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#define IRQ_RESP_STATUS BIT(14)
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#define IRQ_SDIO BIT(15)
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#define CFG_CMD_SETUP BIT(17)
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#define BUS_FSM_MASK GENMASK(29, 26)
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#define IRQ_EN_MASK \
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(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
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IRQ_SDIO)
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#define SD_EMMC_CMD_CFG 0x50
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#define SD_EMMC_CMD_ARG 0x54
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#define SD_EMMC_CMD_DAT 0x58
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#define SD_EMMC_CMD_RSP 0x5c
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#define SD_EMMC_CMD_RSP1 0x60
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#define SD_EMMC_CMD_RSP2 0x64
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#define SD_EMMC_CMD_RSP3 0x68
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#define SD_EMMC_RXD 0x94
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#define SD_EMMC_TXD 0x94
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#define SD_EMMC_LAST_REG SD_EMMC_TXD
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#define SD_EMMC_SRAM_DESC_BUF_OFF 0x200
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#define SD_EMMC_SRAM_DATA_BUF_LEN 1024
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#define SD_EMMC_SRAM_DATA_BUF_OFF 0x400
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#define SD_EMMC_MAX_SEGS 256
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#define SD_EMMC_MAX_REQ_SIZE (128 * 1024)
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#define SD_EMMC_MAX_SEG_SIZE (64 * 1024)
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#define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
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#define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
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#define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
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#define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
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#define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
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#define SD_EMMC_DESC_BUF_LEN (2 * PAGE_SIZE)
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#define SD_EMMC_PRE_REQ_DONE BIT(0)
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#define SD_EMMC_DESC_CHAIN_MODE BIT(1)
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#define MUX_CLK_NUM_PARENTS 2
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#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
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#define CMD_CFG_BLOCK_MODE BIT(9)
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#define CMD_CFG_R1B BIT(10)
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#define CMD_CFG_END_OF_CHAIN BIT(11)
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#define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
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#define CMD_CFG_NO_RESP BIT(16)
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#define CMD_CFG_NO_CMD BIT(17)
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#define CMD_CFG_DATA_IO BIT(18)
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#define CMD_CFG_DATA_WR BIT(19)
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#define CMD_CFG_RESP_NOCRC BIT(20)
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#define CMD_CFG_RESP_128 BIT(21)
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#define CMD_CFG_RESP_NUM BIT(22)
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#define CMD_CFG_DATA_NUM BIT(23)
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#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
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#define CMD_CFG_ERROR BIT(30)
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#define CMD_CFG_OWNER BIT(31)
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#define CMD_DATA_MASK GENMASK(31, 2)
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#define CMD_DATA_BIG_ENDIAN BIT(1)
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#define CMD_DATA_SRAM BIT(0)
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#define CMD_RESP_MASK GENMASK(31, 1)
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#define CMD_RESP_SRAM BIT(0)
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#define EMMC_SDIO_CLOCK_FELD 0Xffff
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#define CALI_HS_50M_ADJUST 0
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#define ERROR 1
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#define FIXED 2
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#define SZ_1M 0x00100000
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#define MMC_PATTERN_NAME "pattern"
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#define MMC_PATTERN_OFFSET ((SZ_1M * (36 + 3)) / 512)
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#define MMC_MAGIC_NAME "magic"
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#define MMC_MAGIC_OFFSET ((SZ_1M * (36 + 6)) / 512)
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#define MMC_RANDOM_NAME "random"
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#define MMC_RANDOM_OFFSET ((SZ_1M * (36 + 7)) / 512)
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#define MMC_DTB_NAME "dtb"
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#define MMC_DTB_OFFSET ((SZ_1M * (36 + 4)) / 512)
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#define CALI_BLK_CNT 80
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#define CALI_HS_50M_ADJUST 0
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#define EMMC_SDIO_CLOCK_FELD 0Xffff
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#define MMC_PM_TIMEOUT (2000)
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#define ERROR 1
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#define FIXED 2
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#define RETUNING 3
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#define DATA3_PINMUX_MASK GENMASK(15, 12)
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#define TUNING_NUM_PER_POINT 40
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#define MAX_TUNING_RETRY 4
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#define AML_FIXED_ADJ_MAX 6
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#define AML_FIXED_ADJ_MIN 5
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#define AML_FIXADJ_STEP 4
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#define ADJ_WIN_PRINT_MAXLEN 256
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#define NO_FIXED_ADJ_MID BIT(31)
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#define AML_MV_DLY2_NOMMC_CMD(x) ((x) << 24)
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#define SD_EMMC_FIXED_ADJ_HS200
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#define EMMC_CMD_WIN_MAX_SIZE 50
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#define EMMC_CMD_WIN_FULL_SIZE 64
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#define DBG_COMMON BIT(0)
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#define DBG_HS200 BIT(1)
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#define Print_dbg(dbg_level, fmt, args...) do {\
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if ((dbg_level) & mmc_debug) \
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pr_info("[%s]" fmt, __func__, ##args); \
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} while (0)
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/* delay_cell=70ps,1ns/delay_cell */
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#define DELAY_CELL_COUNTS 14
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/* emmc partition */
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#define MMC_TUNING_OFFSET 0X14400
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#define RESULT_OK 0
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#define RESULT_FAIL 1
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#define RESULT_UNSUP_HOST 2
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#define RESULT_UNSUP_CARD 3
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/* Host attributes */
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#define AML_USE_64BIT_DMA BIT(0)
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/* Set to 1 for no timeout */
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#define SD_EMMC_CMD_NO_TIMEOUT 1
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/* Set to 32.768s for max timeout */
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#define SD_EMMC_CMD_MAX_TIMEOUT (32768)
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/* Port from block.c */
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#define MMC_EXTRACT_INDEX_FROM_ARG(x) (((x) & 0x00FF0000) >> 16)
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#endif /*__AML_SD_H__*/
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