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PD#SWPL-183850 Problem: 1,low probability crash when dirspi_dma_trig called in isr 2,async need use coherent buf 3,low probability send unexpected data when start dma trig Solution: 1,spicc add controller capability 2,async use coherent buf 3,rm dq2/dq3 for t3x ref board 4,optimize dma trig state management 5,alloc descriptor in controller probe but not in dirspi_dma_trig 6,fix clk div 0 error caused by CFG_BUS clearing by dirspi_dma_trig 7, optimize controller isr 8, add spin lock for smp Verify: t3x/t5m Change-Id: Ic1d5c338ebc65dfa8b33add14cdbf0aff1cc0b46 Signed-off-by: donghui.wang <donghui.wang@amlogic.com>