Chuan Liu b91b2a99f8 clk: s6: Fix mclk0 output exception [1/1] ...

PD#SWPL-172965

Problem:
1 The mclk0 power supply uses the power supply inside the mclk_pll, so the
mclk0 output must ensure that mclk_pll is also enabled.
mclk_pll_clk can output clocks mclk_pll_src and fclk50m. The existence of
these two clock sources is meaningless.
2 If mclk0 uses mclk_pll as the clock source, div2 must be selected for
the clock of the later stage; otherwise, the output clock waveform of
mclk0 is abnormal.

Solution:
1 Delete the mclk_pll_src and fclk50m clock sources and set mclk_pll_clk
as the clock source of mclk0.
2 mclk0 selects div2 by default.

Verify:
s6_bl201

Change-Id: I9a8e3e1616b4c9b3b9c86990f86dc337f9f9c877
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>

2024-07-13 19:17:21 +08:00

..

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clk: s6: Fix mclk0 output exception [1/1]

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