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PD#SWPL-210177 PD#OTT-77737 Problem: after hevcf clk setted rate, the loop is enabled/disabled, and there is a probability that no output after clk is enabled and check pass. Solution: after testing, it is found that it may be related to accuracy of software delay 1ms, and delay of check is increased to 1.2ms Verify: s805x3 Change-Id: I733dd8dbdc6c4849fd3e39c87e34098d08bfe6fa Signed-off-by: yiting.deng <yiting.deng@amlogic.com>