Jian Hu 3e86a15c72 clk: add cpu clock [1/2] ...

PD#SWPL-166006

Problem:
t6d bringup

Solution:
1.fix rtc_32k
2.add cpu clk

Verify:
pxp

Change-Id: If0156b569b577fce2b01a8f8f4d2f1d510cfdd23
Signed-off-by: Jian Hu <jian.hu@amlogic.com>

2024-08-22 14:27:50 +08:00

..

drm

drm: optimize qms_brr_viclist function [1/1]

2024-08-15 04:00:48 -07:00

dt-bindings

clk: add cpu clock [1/2]

2024-08-22 14:27:50 +08:00

linux/amlogic

Merge "hdmitx: add edid_valid property [1/1]" into amlogic-5.15-dev

2024-08-21 21:24:07 -07:00

trace/events

drm: add rdma table for drm osd registers [1/1]

2024-07-17 23:57:23 -07:00

uapi/amlogic

drm: optimize qms_brr_viclist function [1/1]

2024-08-15 04:00:48 -07:00